JP2006278930A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which the dispersion of Cu used as a wiring material is prevented, a leak between interconnect lines is reduced, irregularity is small, reliability is high accordingly, a wiring process is simplified, and therefore, cost becomes low. <P>SOLUTION: The semiconductor device comprises a substrate 1, Cu wiring layers 8, 19 formed on the above-mentioned substrate 1, and interlayer insulating layers 9, 20 formed on the Cu wiring layers 8, 19. The interlayer insulating layers 9, 20 are application-type insulating films having Cu dispersion preventing functions. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device.

  In recent years, integrated circuits have been increasingly integrated. That is, with the miniaturization of semiconductor elements such as transistors constituting an integrated circuit, the degree of integration has improved. In addition, with the miniaturization of semiconductor elements, the operation speed of semiconductor devices is increasing. By the way, the operation speed of a semiconductor device which has been miniaturized has come to be determined by the signal transmission speed (delay time) in the wiring. This delay time depends on the wiring resistance and the wiring capacitance. Therefore, in order to shorten the delay time, it is required to reduce wiring resistance and wiring capacitance.

  This reduction in wiring resistance is achieved by changing the main material of the wiring from Al to Cu. At present, no material having a lower resistance than Cu has been found.

  By the way, with the miniaturization (miniaturization) of semiconductor elements, the number of semiconductor elements mounted on one chip is increasing. Therefore, the number of wirings (distance) is increased because many of these semiconductor elements are connected. That is, the total number of wires is increasing due to an increase in power supply wires for supplying power and signal wires for transmitting signals. The wiring capacity is increasing as the wiring density increases.

  Now, in order to shorten the delay time in wiring, it is required to reduce wiring capacity. Therefore, it is desirable to use a material having a low relative dielectric constant as the interlayer insulating film.

  On the other hand, in Cu / low-dielectric-constant insulating film wiring in a damascene wiring structure, preventing diffusion of Cu, which has been adopted to reduce resistance, into an insulating film is an important element for ensuring wiring reliability. It has become one. In order to achieve this object, a technique is generally used in which a Cu diffusion barrier film is formed on a Cu wiring and a low dielectric constant insulating film is formed on the Cu diffusion barrier film.

  For example, Japanese Patent Laid-Open No. 10-27844 proposes using SiN as a Cu diffusion preventing film.

Japanese Patent Laid-Open No. 2004-14901 proposes using SiCN as a Cu diffusion preventing film.
JP-A-10-27844 JP2004-14901

  By the way, as the above proposal, the conventional technique using the Cu diffusion barrier film and the low dielectric constant insulating film has laminated films made of different materials (Cu diffusion barrier film and low dielectric constant insulating film). The number of interfaces increases accordingly. When an electric field is applied between the parallel wirings, current leakage is likely to occur at the interface, so current leakage is likely to occur as much as the number of interfaces is increased. Therefore, problems are more likely to occur.

  Also, the introduction of SiN or SiCN increases the effective dielectric constant because these materials themselves have a high relative dielectric constant. Therefore, a problem arises from this point. In particular, considering the correspondence to the 65 nm node generation and beyond, the introduction of SiN or SiCN is considered to significantly increase the dielectric constant of the entire wiring, which is not preferable.

  Further, the film formation of SiN or SiCN is usually based on CVD (chemical vapor deposition method). For this reason, in wiring, as the number of laminated films increases, unevenness is more likely to occur. In addition, when the wiring is subjected to CMP (chemical mechanical polishing), unevenness is likely to occur depending on the wiring shape and wiring density.

  Therefore, a first problem to be solved by the present invention is to provide a semiconductor device with less wiring leakage and high reliability.

  The second problem to be solved by the present invention is to provide a semiconductor device with less unevenness and higher reliability.

  The third problem to be solved by the present invention is to provide a semiconductor device in which the wiring process is simplified and the cost is reduced accordingly.

  While eagerly pursuing research to solve the above problems, the present inventor has constituted the interlayer insulating film by a Cu diffusion prevention film such as SiN or SiCN and a low dielectric constant insulating film. It has led to a revelation that there is a problem.

  Therefore, if the two of the Cu diffusion prevention film and the low dielectric constant insulating film can be formed as a single film, the number of interfaces is reduced accordingly, so that the leakage between wirings is reduced. Since the number is reduced, it becomes difficult to make unevenness, the reliability of the semiconductor device is increased, the wiring process is simplified, and the cost of the semiconductor device will be reduced.

  The present invention has been achieved based on such findings.

That is, the subject is a semiconductor device comprising a substrate, a Cu wiring layer provided on the substrate, and an interlayer insulating layer provided on the Cu wiring layer,
This is solved by a semiconductor device wherein the interlayer insulating layer is a coating type insulating film having a Cu diffusion preventing function.

In particular, the semiconductor device includes a substrate, a Cu wiring layer provided on the substrate, an interlayer insulating layer provided on the Cu wiring layer, and a wiring layer provided on the interlayer insulating layer. And
This is solved by a semiconductor device wherein the interlayer insulating layer is a coating type insulating film having a Cu diffusion preventing function.

  In the present invention, the wiring layer is a layer formed by filling a recess formed in the inter-wiring insulating layer with Cu.

  The interlayer insulating layer in the present invention is a coating type insulating film having a Cu diffusion preventing function having a relative dielectric constant of 3.5 or less. Examples of such an insulating film include a coating type insulating film made of an N-containing resin. In particular, a coating type insulating film made of a resin having an N content of 5 to 25 atomic% can be given. More specific examples include polybenzoxazole. Or a polysilazane is mentioned. Or a polyimide is mentioned.

  Further, the problem can be solved by the semiconductor device of the present invention constituted by an inter-wiring insulating layer having a dielectric constant of 2.5 or less.

  In the present invention, since the conventional interlayer insulating film composed of the Cu diffusion preventing film such as SiN or SiCN and the low dielectric constant insulating film is composed of the coating type insulating film having the Cu diffusion preventing function, the film ( The number of interfaces is reduced. By the way, most of the leakage current flows through the interface. Therefore, the leakage current is reduced. Further, the inter-wiring capacity does not increase. And since an interlayer insulation film is comprised with a coating type insulation film, an unevenness | corrugation becomes difficult to be made. As a result, the reliability of the semiconductor device is improved. Furthermore, since the number of films is reduced, the film forming process is reduced. Therefore, the cost is low.

  The coating type insulating film having a Cu diffusion preventing function of the present invention is a coating type insulating film made of N-containing resin. Specifically, for example, at least one selected from the group of polybenzoxazole, polysilazane, and polyimide is used. The excellence of these resins is shown below.

  That is, FIG. 9 and FIG. 10 show a TDDB test apparatus taking SiO as an example. A voltage was applied to this device to conduct a TDDB test. In the case of FIG. 9, a short circuit occurs due to electrical breakdown of the insulating film (SiO). In the case of FIG. 10, since Cu is an electrode, Cu diffuses in the insulating film (SiO), causing a short circuit. In general, in the evaluation of the Cu wiring insulating film, if the TDDB life in the case of FIG. 10 is long, it is determined that the film is highly reliable.

  Therefore, in FIG. 10, instead of the SiO film, an insulating paint containing polybenzoxazole having a relative dielectric constant of 3.0 was applied by spin coating and cured to form an insulating coating film having a thickness of 100 nm. Then, Cu dots having a thickness of 500 nm and 1 mmφ were formed thereon. Al dots having a thickness of 5 μm were formed on the Cu dots. And the Si substrate side was earth | grounded and the TDDB test was done at 125 degreeC and 200 degreeC. The result is shown in FIG. According to this, it can be seen that the lifetime at 0.3 MV / cm is 10 years or more. That is, the insulating film is much longer than that of SiO.

  The same tendency was observed when polysilazane or polyimide was used.

  The inventor considers this phenomenon as follows. That is, the above materials have a high N concentration in the insulating film composition. Then, it is considered that N atoms in the insulating film capture or immobilize Cu that diffuses, and as a result, an effect of preventing Cu diffusion is achieved.

  And since these materials are a coating type, the high planarization property of a film | membrane is acquired. In addition, even with a multilayer wiring structure, the influence of focal depth variation in photolithography is reduced. Furthermore, polishing residues in CMP are prevented.

  1 to 8 are explanatory diagrams in the manufacturing process of the semiconductor device according to the present invention.

  First, as shown in FIG. 1, an insulating film (p-SiO) 2 having a thickness of 500 nm was provided on the Si substrate 1 by CVD. Thereafter, an etching stop film (SiCN: relative dielectric constant = 5.0) 3 having a thickness of 50 nm was provided on the insulating film 2 by CVD. Further, a porous Methylsilsesquioxane (MSQ) coating was applied on the etching stopper film 3 by spin coating to provide a porous insulating film (relative dielectric constant = 2.5: inter-wiring insulating film) 4. Further, a non-porous MSQ paint was applied onto the insulating film 4 by spin coating, and cured at 420 ° C. for 1 hour, thereby providing an insulating film (CMP cap film) 5 having a thickness of 100 nm.

  Next, as shown in FIG. 2, the wiring trench 6 is formed by reactive ion etching. Etching is stopped at the etching stop layer 3.

Thereafter, as shown in FIG. 3, a barrier metal layer 7 was provided by depositing TaN in a thickness of 5 nm in the wiring trench 6 by PVD (physical vapor deposition method), and subsequently depositing Ta in a thickness of 12 nm. Thereafter, a Cu seed was deposited to a thickness of 80 nm by in situ treatment. Then, Cu8 having a thickness of 800 nm was deposited on the Cu seed by electrolytic plating. Thereafter, annealing was performed at 220 ° C. in an H ₂ gas atmosphere. Then, Cu, TaN, and Ta on the insulating film 5 were removed by CMP.

  Next, as shown in FIG. 4, a polybenzoxazole-containing paint was applied from above by spin coating to provide an insulating film (relative dielectric constant = 3.0: interlayer insulating film) 9. Subsequently, a non-porous MSQ coating was applied and cured at 420 ° C. for 1 hour to provide an insulating film (CMP cap film) 10 having a thickness of 100 nm.

Thereafter, as shown in FIG. 5, a via hole 11 is formed by reactive ion etching. Then, the barrier metal layer 12 was provided by depositing 5 nm of TaN in the via hole 11 by PVD and subsequently depositing 12 nm of Ta. Thereafter, a Cu seed was deposited to a thickness of 80 nm by in situ treatment. Then, 800 nm thick Cu13 was deposited on the Cu seed by electrolytic plating. Thereafter, annealing was performed at 220 ° C. in an H ₂ gas atmosphere. Then, Cu, TaN, and Ta on the insulating film 10 were removed by CMP.

  Next, as shown in FIG. 6, a polybenzoxazole-containing paint was applied from above by spin coating to provide an insulating film (relative dielectric constant = 3.0) 14 having a thickness of 50 nm. Subsequently, a porous MSQ coating was applied by spin coating to provide an insulating film (relative dielectric constant = 2.5: insulating film between wirings) 15. On this insulating film 15, MSQ paint was applied and cured at 420 ° C. for 1 hour to provide an insulating film (CMP cap film) 16 having a higher density than the insulating film 15 and having a thickness of 100 nm.

Thereafter, as shown in FIG. 7, wiring trenches 17 are formed by reactive ion etching. Note that the Cu surface is exposed by etching. Then, by PVD, TaN was deposited to a thickness of 5 nm in the wiring groove 17, and then Ta was deposited to a thickness of 12 nm to provide a barrier metal layer 18. Thereafter, a Cu seed was deposited to a thickness of 80 nm by in situ treatment. Then, 800 nm thick Cu 19 was deposited on the Cu seed by electrolytic plating. Thereafter, annealing was performed at 220 ° C. in an H ₂ gas atmosphere. Then, Cu, TaN, and Ta on the insulating film 16 were removed by CMP.

  Subsequently, as shown in FIG. 8, a polybenzoxazole-containing paint is applied from above by spin coating, and cured at 420 ° C. for 1 hour, and an insulating film having a thickness of 100 nm (relative dielectric constant = 3.0: Interlayer insulating film) 20 was provided. Thereafter, a non-porous MSQ coating was applied by spin coating and cured at 420 ° C. for 1 hour to provide an insulating film (CMP cap film) 21 having a thickness of 100 nm.

  FIG. 12 is a schematic diagram of a conventional semiconductor device, and corresponds to FIG. 8 according to the present invention. As can be seen from the comparison between FIG. 8 and FIG. 12, in the semiconductor device of the present invention, it is obvious that the number of interlayer insulating films is small.

  In the semiconductor device of the above embodiment, the interlayer insulating films 9 and 20 are preferably thinner than the inter-wiring insulating films 4 and 15. The thickness is preferably 50 nm or more. That is, the effective dielectric constant is not a problem even if a CMP cap film made of a material having a relatively high dielectric constant is formed on the interlayer insulating films 9 and 20 within such a range. . Also, crosstalk is not a problem. Furthermore, by using an inter-wiring insulating film having a relative dielectric constant of 2.5 or less, the features aimed by the present invention can be greatly achieved.

Manufacturing process diagram of semiconductor device of the present invention Manufacturing process diagram of semiconductor device of the present invention Manufacturing process diagram of semiconductor device of the present invention Manufacturing process diagram of semiconductor device of the present invention Manufacturing process diagram of semiconductor device of the present invention Manufacturing process diagram of semiconductor device of the present invention Manufacturing process diagram of semiconductor device of the present invention Schematic diagram of the semiconductor device of the present invention TDDB test equipment TDDB test equipment Insulation film lifetime graph Schematic diagram of a conventional semiconductor device

Explanation of symbols

1 Si substrate 2 Insulating film 3 Etching stop film 4, 15 Porous insulating film (inter-wiring insulating film)
5, 10, 16, 21 Insulating film (CMP cap film)
6, 17 Wiring grooves 7, 12, 18 Barrier metal layers 8, 13, 19 Cu (wiring)
9,20 Insulating film (interlayer insulating film)
11 Via hole 14 Insulating film

Representative Katsumi Udaka

Claims (10)

A semiconductor device comprising a substrate, a Cu wiring layer provided on the substrate, and an interlayer insulating layer provided on the Cu wiring layer,
A semiconductor device, wherein the interlayer insulating layer is a coating type insulating film having a Cu diffusion preventing function. A semiconductor device comprising: a substrate; a Cu wiring layer provided on the substrate; an interlayer insulating layer provided on the Cu wiring layer; and a wiring layer provided on the interlayer insulating layer,
A semiconductor device, wherein the interlayer insulating layer is a coating type insulating film having a Cu diffusion preventing function.   3. The semiconductor device according to claim 1, wherein the wiring layer is a layer formed by filling a recess formed in the inter-wiring insulating layer with Cu.   4. The semiconductor device according to claim 1, wherein the interlayer insulating layer is a coating type insulating film having a relative dielectric constant of 3.5 or less and having a Cu diffusion preventing function.   5. The semiconductor device according to claim 1, wherein the interlayer insulating layer is a coating type insulating film made of an N-containing resin having a relative dielectric constant of 3.5 or less.   6. The semiconductor according to claim 1, wherein the interlayer insulating layer is a coating type insulating film made of a resin having a relative dielectric constant of 3.5 or less and an N content of 5 to 25 atomic%. apparatus.   The semiconductor device according to any one of claims 1 to 6, wherein the interlayer insulating layer is an insulating film formed using polybenzoxazole.   8. The semiconductor device according to claim 1, wherein the interlayer insulating layer is an insulating film formed using polysilazane.   The semiconductor device according to claim 1, wherein the interlayer insulating layer is an insulating film made of polyimide. 10. The semiconductor device according to claim 1, wherein the inter-wiring insulating layer has a relative dielectric constant of 2.5 or less.

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