WO2008029532A1 - Appareil de traitement de signaux de reproduction - Google Patents

Appareil de traitement de signaux de reproduction Download PDF

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Publication number
WO2008029532A1
WO2008029532A1 PCT/JP2007/056674 JP2007056674W WO2008029532A1 WO 2008029532 A1 WO2008029532 A1 WO 2008029532A1 JP 2007056674 W JP2007056674 W JP 2007056674W WO 2008029532 A1 WO2008029532 A1 WO 2008029532A1
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WO
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Prior art keywords
signal processing
reproduction signal
signal
adaptive
circuit
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PCT/JP2007/056674
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English (en)
Japanese (ja)
Inventor
Hiroyuki Nakahira
Kouji Okamoto
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Panasonic Corporation
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Publication date
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Publication of WO2008029532A1 publication Critical patent/WO2008029532A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10046—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10046—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
    • G11B20/10203—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter baseline correction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10268—Improvement or modification of read or write signals bit detection or demodulation methods
    • G11B20/10287—Improvement or modification of read or write signals bit detection or demodulation methods using probabilistic methods, e.g. maximum likelihood detectors
    • G11B20/10296—Improvement or modification of read or write signals bit detection or demodulation methods using probabilistic methods, e.g. maximum likelihood detectors using the Viterbi algorithm
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10305—Improvement or modification of read or write signals signal quality assessment
    • G11B20/10398—Improvement or modification of read or write signals signal quality assessment jitter, timing deviations or phase and frequency errors
    • G11B20/10425—Improvement or modification of read or write signals signal quality assessment jitter, timing deviations or phase and frequency errors by counting out-of-lock events of a PLL
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B2020/10935—Digital recording or reproducing wherein a time constraint must be met
    • G11B2020/10972—Management of interruptions, e.g. due to editing

Definitions

  • the present invention relates to a reproduction signal processing device, a reproduction signal processing method, and a reproduction signal processing program for reproducing data from a signal read from a recording medium such as an optical disk using adaptive processing.
  • some reproduction signal processing devices improve signal quality by applying adaptive processing to a read signal from a recording medium to invalidate noise and distortion included in the read signal. ing.
  • the start timing of the adaptive processing is embedded in the recording medium, the adaptive processing is started at the fixed start timing, and the data is reproduced. ing.
  • Patent Document 1 Japanese Patent Laid-Open No. 9-306104
  • Patent Document 2 Japanese Patent Laid-Open No. 10-106164
  • noise and distortion due to various factors are added to a signal reproduced from a recording medium. If adaptive processing can be performed appropriately so that these noises and distortions can be invalidated, the signal quality after adaptive processing will be greatly improved as expected.
  • Patent Document 1 For example, in a transient state such as when the power is turned on or an unexpected signal fluctuation occurs due to a defective medium, etc., the adaptive processing starts when the frequency of error occurrence exceeds the specified frequency. Therefore, the tap coefficient of the adaptive process becomes a coefficient value that is significantly different from the tap coefficient in the steady state. There are drawbacks such as a long time required for the tap coefficient value of the adaptive processing in the steady state to reach an appropriate value, and incorrect adaptive processing.
  • the present invention pays attention to the above-mentioned problem, and its purpose is not influenced by the transient state, and the adaptive processing in the stable state can be appropriately performed in a short time to achieve high stability and the adaptive processing. It is to provide a reproduction signal processing apparatus.
  • the state of a read signal from a recording medium is
  • the reproduction signal processing apparatus of the present invention is a reproduction signal processing apparatus that performs adaptive processing on a signal read from a recording medium and reproduces data from the recording medium.
  • An adaptive processing circuit that performs adaptive processing on the read signal and a signal read from the recording medium are input, and it is determined whether the state of the input signal satisfies a preset condition!
  • the present invention provides the reproduction signal processing device, wherein the determination circuit is the recording medium.
  • a signal obtained by filtering the read signal is input, and it is determined whether or not the state of the input signal satisfies a preset condition.
  • the present invention is characterized in that, in the reproduction signal processing device, the input signal is a digital signal of a DC-free code.
  • the present invention provides the reproduction signal processing device, wherein the filter for performing the filter processing is:
  • DC free code digital signal power A band-limiting filter that cuts DC components.
  • the present invention is characterized in that, in the reproduction signal processing device, the execution control circuit controls execution of the adaptive processing by executing, holding or resetting the adaptive processing.
  • the present invention provides the reproduction signal processing device, wherein the determination circuit detects a specific signal within a predetermined time included in the input signal, and the state of the specific signal satisfies the setting condition. It is characterized by determining whether or not.
  • the determination circuit calculates an appearance frequency of a specific signal within the predetermined time, and when the calculated appearance frequency is equal to or higher than a set frequency, It is characterized by determining that it satisfies.
  • the present invention is characterized in that, in the reproduction signal processing device, the specific signal is sampling data determined to be a zero cross point.
  • the present invention provides the reproduction signal processing apparatus, further comprising: a PLL circuit that extracts a clock included in a signal read from the recording medium, and the determination circuit has a state in which the state of the input signal is the PLL It is characterized by determining whether or not the force satisfies the circuit lock condition.
  • the present invention provides the reproduction signal processing apparatus in which the state of the input signal satisfies the set condition by an amplifier that amplifies the analog signal read from the recording medium with a variable gain and the determination circuit. And an analog control circuit for fixing the gain of the amplifier to the value at the time of the determination when it is determined.
  • the present invention provides the reproduction signal processing device, wherein an adder that adds a variable offset value to an analog signal read from the recording medium and the input by the determination circuit An analog control circuit that fixes the offset value of the adder to the value at the time of determination when the signal state satisfies the setting condition and is determined to be ⁇ ! .
  • the present invention is characterized in that, in the reproduction signal processing device, the input signal is supplied via a wireless communication path or a communication path including an optical fiber, a coaxial cable, or a power line.
  • the present invention is characterized in that, in the reproduction signal processing apparatus, the input signal is supplied from an optical disc card including a DVD, CD, or Blu-my disc.
  • the video display device of the present invention is a signal for decoding a reception signal including audio data and video data based on the result of adaptive processing obtained by the reproduction signal processing device and the reproduction signal processing device.
  • An LSI having a processing circuit, and a display terminal that receives a decoded signal from the signal processing circuit of the LSI, generates decoded audio data, and displays the decoded video data .
  • the determination circuit determines whether the state of the read signal from the recording medium satisfies the setting condition, and Since the adaptive processing by the adaptive processing circuit is executed only in a state where the set condition is satisfied, for example, in the steady state, the adaptive processing in the transient state can be stopped as is the case, and the adaptive processing in the steady state can be stably performed. It becomes possible to execute.
  • FIG. 1 is a diagram showing an overall configuration of a reproduction signal processing device according to a first embodiment of the present invention.
  • FIG. 2 is a diagram for explaining a DC-free code for an input signal to the reproduction signal processing apparatus.
  • FIG. 3 is a diagram showing an internal configuration of an adaptive filter provided in the reproduction signal processing apparatus.
  • FIG. 4 is a diagram showing an internal configuration of an adaptive Viterbi decoding circuit provided in the reproduction signal processing apparatus. It is.
  • FIG. 5 is a diagram for explaining how a DC component is included in an input signal
  • FIG. 5 (b) is an explanatory diagram for removing the DC component by a baseline circuit provided in the reproduction signal processing device
  • (c) is a diagram showing a configuration of a band limiting filter provided in the baseline circuit.
  • FIG. 6 is a diagram for explaining PLL lock determination by a determination circuit provided in the reproduction signal processing apparatus.
  • FIG. 7 is a diagram showing a relationship between a control signal output from a determination circuit provided in the reproduction signal processing apparatus and an output signal of a base line control circuit.
  • FIG. 8 is a diagram showing a reproduction signal processing apparatus according to the second embodiment of the present invention.
  • FIG. 9 is a diagram showing the relationship between the abnormal signal waveform of the recording medium and the signal waveform after waveform shaping of the baseline control circuit force in the reproduction signal processing apparatus.
  • FIG. 10 is a diagram showing an overall schematic configuration of a video display device provided with the reproduction signal processing device of the present invention.
  • VGA variable gain amplifier
  • FIG. 1 shows an overall schematic configuration of a reproduction signal processing apparatus according to Embodiment 1 of the present invention.
  • the reproduction signal processing apparatus 100 of the present invention reads out data recorded on a recording medium such as a DVD and performs reproduction signal processing from decoding of the data to an AFE (Analog Front End). 101, ADC (AZD modified ⁇ ) 102, baseline circuit 103, PLL (PLL circuit) 104, decision circuit 105, adaptive filter (first adaptive processing circuit) 106, adaptive Viterbi decoding circuit (Second adaptive processing circuit) 107.
  • AFE Analog Front End
  • Fig. 2 will describe a DC-free code which is one of the characteristics of a CD or DVD code.
  • digital data consisting of 0 and 1 is recorded on the recording medium.
  • the clock is embedded in the data itself, so there are some rules for the 0 and 1 patterns, one of which is called DC-free.
  • DC-free the number of 0's and 1's are the same within a set period of a certain fixed period. In this way, when data is reproduced, if a DC (direct current) component that should not be included in the data is included, the DC component is cut to perform waveform shaping.
  • the signal recorded on the recording medium is read by an optical pickup and a magnetic head (not shown) to become an analog signal.
  • This analog signal is waveform-shaped by AFE101, ADC1 02 is converted to digital data.
  • an unnecessary frequency component such as a direct current component or a low frequency component caused by eccentricity of the recording medium is removed in the baseline circuit 103.
  • the PLL 104 extracts the clock included in the read signal from the recording medium, and supplies it to the digital unit of the reproduction signal processing apparatus 100 and the ADC 102.
  • the output of the baseline circuit 103 is also supplied to the adaptive filter 106.
  • the adaptive filter 106 is adaptive when the waveform shaping of the AFE101 cannot be sufficiently performed due to various factors such as a difference in recording characteristics due to a difference in recording apparatuses, variations in recording media, and variations in characteristics of the AFE101. By adjusting the filter characteristics, ideal waveform shaping is achieved.
  • the adaptive filter 106 includes an FIR filter 1061 and a filter coefficient learning circuit 1062. This will be described with reference to FIG.
  • 2010 to 2014 are D flip-flops
  • 2020 to 2024 are multipliers, which multiply the coefficients 2100 to 2104 of the filter coefficient learning circuit 1062 and the outputs of the D flip-flops 2010 to 2014, respectively.
  • the Karo arithmetic unit 203 calculates the sum of the outputs of the multipliers 2020 to 2024.
  • the output of the adder 203 is the output of the FIR filter 1061 and the output of the adaptive filter 106.
  • the filter coefficient learning circuit 1062 adaptively learns the coefficients 2100 to 2104 used in the FIR filter 1061.
  • the formula for the LMS algorithm is
  • ⁇ ( ⁇ + 1) ⁇ ( ⁇ ) + ⁇ water e ( ⁇ ) water ⁇ ( ⁇ )
  • ⁇ ( ⁇ ) is the ⁇ th filter coefficient
  • ⁇ ( ⁇ + 1) is the ⁇ + 1st filter coefficient
  • ⁇ is the learning coefficient (step size parameter)
  • e (n) is the nth filter coefficient.
  • Error signal difference between ideal value and FIR filter 1061 output value
  • x (n) is the nth FIR filter input signal.
  • the coefficient is updated so that the error signal e (n) is minimum, that is, the output value of the FIR filter 1061 approaches the ideal value.
  • the filter coefficient learning circuit 1062 is an example in which the LMS algorithm is implemented in a circuit.
  • the ideal value generation circuit 204 generates an ideal value of the output force of the FIR filter 1061. For example, some values within a certain range are generated by quantization so that all values are set in advance, or some are generated by judging from the incoming data, here the output sequence of the FIR filter 1061. is there.
  • the subtracter 205 calculates a difference between the output of the FIR filter 1061 and the ideal value generation circuit 204, that is, an error between the FIR filter 1061 and the ideal value.
  • the logical product circuit 206 takes the logical product of the control signal C of the determination circuit 105 and the subtractor 205.
  • this control signal C is 0, the error is not transmitted to the subsequent arithmetic circuits. Therefore, the coefficient is retained without being updated, and the adaptive process is not executed.
  • the coefficient is updated by the LMS algorithm and adaptive processing is executed.
  • An AND circuit 206 that receives the control signal C from the determination circuit 105 constitutes an execution control circuit 110 that controls execution of the adaptive filter processing by the adaptive filter 106.
  • the coefficient update circuits 2110 to 2114 update the coefficients 2100 to 2104, respectively.
  • the coefficient update circuit 2110 will be described as an example.
  • the multiplier 207 multiplies the error from the subtractor 205 and the FIR filter input signal (here, the output of the D flip-flop 2010).
  • the gain 208 multiplies the output of the multiplier 207 by a learning coefficient.
  • the adder 209 adds the output of the gain 208, that is, the coefficient update and the coefficient 2100.
  • Register 210 holds the filter coefficient 2100.
  • Filter coefficient 2100 is one input of multiplier 2020.
  • reset means setting the value of the register 210 to 0 or an initial value. In the case of hold, the same effect can be obtained by setting the control signal C to 0.
  • the method for controlling the propagation of error is not limited to the one disclosed here, and for example, there is a method of setting the learning coefficient to 0 when the control signal C is 0.
  • the force filter coefficient learning circuit 1062 that has described the LMS algorithm may use another adaptive algorithm.
  • the adaptive Viterbi decoding circuit 107 receives the output of the waveform-shaped adaptive filter 106, and searches for the reference value sequence closest to the data sequence, thereby decoding the most probable data. This will be described with reference to FIG. Here, the case where the number of reference values is four is explained.
  • the Viterbi decoder 1071 searches for a sequence of reference values 3100 to 3103 that is closest to the data sequence of the output of the adaptive filter 106 that is an input, and decodes the most accurate data.
  • Reference value learning circuit 1072 updates reference values 3100 to 3103 based on the output of adaptive filter 106.
  • the delay circuit 301 adjusts the time difference between the output of the adaptive filter 106 and the output of the Viterbi decoder 1071, and is constituted by a shift register (not shown).
  • the selection circuit 302 selects a reference value to be updated using the decoded data.
  • the subtractor 303 calculates the difference between the selected reference value and the output of the delay circuit 301.
  • the logical product circuit 304 takes a logical product of the control signal C of the determination circuit 105 and the subtractor 303.
  • the control signal C is 0, the selected reference value and the delay circuit 301 are used. Since the difference from the output of is not propagated to the subsequent arithmetic circuit, the reference value is maintained without being updated, and the adaptation process is not executed.
  • the control signal C is 1, the difference between the selected reference value and the output of the delay circuit 301 is propagated, so that the reference value is updated and adaptive processing is executed.
  • An AND circuit 304 that receives the control signal C from the determination circuit 105 constitutes an execution control circuit 111 that controls the execution of the adaptive Viterbi decoding process by the adaptive Viterbi decoding circuit 107.
  • the result of the AND circuit 304 is amplified by a gain 305.
  • the adder 306 adds the reference value selected by the selection circuit 302 and the output of the gain 305, and updates the selected reference value.
  • the updated reference value is held in registers 307-310.
  • the method for controlling the propagation of the difference between the selected reference value and the output of the delay circuit 301 is not limited to that disclosed here, and for example, when the control signal C is 0, the gain There are also methods such as setting the size of 305 to zero. Also, other adaptive algorithms may be used for reference value learning.
  • the baseline circuit 103 removes a DC component included in the input signal or a frequency component lower than the input signal. If the input signal is a DC free code, the read signal from the recording medium contains no direct current component, so it is determined that this is a signal other than the information that is originally required, and is removed. This is shown in the figure for the input signal shown in Fig. It is an output signal of (b). As an example of a circuit that realizes this, the band limiting filter 103F is shown in FIG. In FIG. 5 (c), the integrator 401 integrates the input signal. Gain 40 2 multiplies the output of integrator 401 by the set value. Assuming that the output of the gain 402 is the baseline error, the subtractor 403 subtracts the input signal power baseline error and becomes the output of the baseline circuit 103.
  • a determination circuit 105 receives an input signal after being filtered so as to remove a direct current component and a low frequency component by the band limiting filter 103 3F of the baseline circuit 103, and receives the input signal. It is determined whether or not the state satisfies a preset condition.
  • a preset condition a condition for determining that the PLL 105 is locked is listed, and it is specifically determined whether or not the input signal state after the filtering process satisfies this setting condition! / This will be described with reference to FIG.
  • ⁇ and ⁇ are digital data sampled by a digital data recovery clock, and ⁇ is a zero cross point.
  • the zero cross point is the point where the digital data becomes 0, but here it is used to mean the digital data closest to the baseline.
  • the baseline is a zero value and is fixed.
  • the lock determination of the PLL 105 is executed in the following sequence. First, the zero cross point is detected. Next, it is determined whether the value is within a preset value (eg, ⁇ 5) and whether the baseline error is within a preset value (eg, ⁇ 10), and the digital data at the zero cross point is ⁇ 5. And the baseline error is within ⁇ 10, the zero crossing point (specific signal) is counted within a predetermined period (for example, 1000T) (T is one clock cycle) Increase the count value by +1.
  • a preset value eg, ⁇ 5
  • a preset value eg, ⁇ 10
  • the PLL It is determined that 104 is locked.
  • control signal C is executed, reset, or Specify a field.
  • FIG. 7 shows the situation. This is because when the waveform is shaped to equalize the force, which is a plot of the output of the baseline circuit 103, the PLL 104 shifts from unlock to lock and the control signal C shifts from 0 to 1. At almost the same time, it can be seen that the output of the baseline circuit 103 is normally equalized to five values as indicated by reference numerals 103a to 103e.
  • FIG. 8 shows a reproduction signal processing apparatus according to the second embodiment of the present invention.
  • the reproduction signal processing apparatus 500 of the present invention reads out data recorded on a recording medium such as a DVD and performs reproduction signal processing until the data is decoded.
  • AFE Analog Front End
  • ADC Analog conversion
  • baseline circuit 103 baseline circuit 103
  • PLL 504 determination circuit 105
  • adaptive filter 106 adaptive Viterbi decoding circuit 107
  • the same reference numerals as those in FIG. 1 denote the same components.
  • the AFE 501 includes a VGA (Variable Gain Amplifier) 5010, a calorie calculator 5011, and an analog filter 5012.
  • the analog control circuit 502 adjusts the performance and functions such as the gain of the VGA 5010, the variable offset value added to the adder 5011, and the cutoff frequency of the analog filter 5012 using the digital data output from the ADC 102. Although this adjustment is not shown here, for example, the peak value and bottom value of the digital data are calculated by tracing the envelope of the output of the ADC 102, and the necessary gain is calculated from the difference from the desired amplitude. Give to the VGA5010.
  • the offset value to be added to the adder 5011 is adjusted by adjusting the variable offset value to be added to the output so that the 0 level of the output of the VGA 5010 is adjusted.
  • the readout signal is processed while changing the setting, and the setting that makes the PLL 504 lock judgment time the earliest is adopted.
  • FIG. 9 shows one of the abnormal waveforms of the read signal found on a DVD.
  • the upper waveform shows the digital signal after AD conversion of the readout signal from the recording medium by the ADC102, that is, the input signal of the baseline circuit 103
  • the lower waveform shows the output signal of the baseline circuit 103.
  • the signal after waveform shaping is plotted. If the reflected light from the laser is weakened due to black dots adhering to the surface of the DVD, the output waveform of the ADC102 temporarily drops significantly, as shown in the figure. There is a period in which the signal level greatly decreases from that of the current and becomes a substantially constant direct current.
  • the baseline circuit 105 has a function of cutting the direct current and low frequency band, and adds a large baseline error value E so as to compensate for the lowered signal level.
  • the output signal of the baseline circuit 105 the output appears near the 0 level even in the DC period.
  • the determination circuit 105 sets the baseline error value added by the baseline circuit 105 to the set value in addition to the determination condition of the lock state of the PLL 104 described in the first embodiment. If exceeded, it has a function to determine that the PLL 504 is unlocked and set the control signal C to “Hold”.
  • the analog control circuit 502 receives the control signal C (hold instruction) from the determination circuit 105 and controls to hold the gain of the VGA 5010 in the AFE 501 and the offset value to be added to the adder 5011.
  • the determination circuit 105 determines that the PLL 504 is locked and sets the control signal C to “execute”, so the gain of the VGA 5010 and the adder 5011 The offset value is again adjusted from each of these holding values.
  • the adaptive filter 106 is also an adaptive Viterbi decoding circuit. 107 is also "hold" adaptive processing Needless to say,
  • FIG. 10 shows a video display device including an LSI incorporating the reproduction signal processing device, using a reproduction signal waveform read out from a recording medium 601 such as an optical disk by a laser of a pickup 602.
  • LSI 603 including a signal processing circuit that performs waveform equalization, error correction, control, modulation, decoding, data extraction, etc., and an audio of analog or digital value based on the decoded reproduction signal output from this LSI 603 Data is pronounced and video data is displayed on the display terminal 604.
  • the power provided by the adaptive filter 106 and the adaptive Viterbi decoding circuit 107 as the adaptive processing circuit may be provided, and either one of these two adaptive processing circuits may be provided.
  • an adaptive processing circuit that adaptively updates the characteristics according to the input signal may be used.
  • the present invention is a program for causing a computer to execute the functions of all or part of the above-described reproduction signal processing device, device, element, circuit, etc., and cooperates with the computer.
  • a recording medium that can be read by a computer that records this program is also included in the present invention.
  • one usage form of the program may be an aspect in which the program is recorded on a computer-readable recording medium and operates in cooperation with the computer.
  • one usage form of the program may be an aspect in which the program is transmitted through a transmission medium, read by a computer, and operated in cooperation with the computer.
  • the recording medium includes optical discs such as DVD, CD, Blu-ray disc and ROM
  • the transmission media include transmission media such as the Internet, wireless communication paths, or light, radio waves, It may be a communication path including an optical fiber that transmits sound waves, a coaxial cable, or a power line.
  • the computer described above is not limited to pure hardware such as a CPU, and may include firmware, an OS, and peripheral devices. Note that the configuration of the present invention may be realized in software or in hardware.
  • the present invention can execute adaptive processing with high stability, so that a reproduction signal processing device for reproducing a read signal from a recording medium on which audio data or video data is recorded is reproduced. It is also useful when applied to video display devices.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

L'invention concerne un appareil de traitement de signaux de reproduction, destiné à soumettre des signaux lus sur un support d'enregistrement à des opérations de traitement adaptatif en vue de les reproduire. Dans cet appareil, le signal lu est filtré par un circuit de base (103) de façon à en supprimer les composantes continues et les composantes basse fréquence. Le signal filtré est ensuite appliqué à l'entrée d'un circuit de détermination (105). Le circuit de détermination (105) contrôle l'état du signal appliqué et, lorsque celui-ci s'est stabilisé, produit un signal de commande (exécution) (C), lequel commande l'exécution des opérations de traitement adaptatif dans un filtre adaptatif (106) et un circuit de décodage Viterbi adaptatif (107). L'invention permet donc de garantir la stabilité des opérations de traitement adaptatif, notamment après un état transitoire dû par exemple à des fluctuations imprévisibles des signaux au moment de la mise sous tension ou du fait d'un support défectueux.
PCT/JP2007/056674 2006-09-05 2007-03-28 Appareil de traitement de signaux de reproduction WO2008029532A1 (fr)

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TWI472151B (zh) * 2011-08-30 2015-02-01 Richwave Technology Corp 自動調整頻寬的濾波器系統及自動調整濾波器頻寬的方法

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