WO2008024221A3 - Micro tag reducing cache power - Google Patents

Micro tag reducing cache power Download PDF

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Publication number
WO2008024221A3
WO2008024221A3 PCT/US2007/017896 US2007017896W WO2008024221A3 WO 2008024221 A3 WO2008024221 A3 WO 2008024221A3 US 2007017896 W US2007017896 W US 2007017896W WO 2008024221 A3 WO2008024221 A3 WO 2008024221A3
Authority
WO
WIPO (PCT)
Prior art keywords
micro tag
tag array
cache
data bits
micro
Prior art date
Application number
PCT/US2007/017896
Other languages
French (fr)
Other versions
WO2008024221A2 (en
Inventor
Ryan C Kinter
Matthias Knoth
Original Assignee
Mips Tech Inc
Ryan C Kinter
Matthias Knoth
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/505,865 external-priority patent/US7650465B2/en
Priority claimed from US11/505,869 external-priority patent/US7657708B2/en
Application filed by Mips Tech Inc, Ryan C Kinter, Matthias Knoth filed Critical Mips Tech Inc
Priority to CN2007800369813A priority Critical patent/CN101523359B/en
Priority to GB0903127A priority patent/GB2456636B/en
Publication of WO2008024221A2 publication Critical patent/WO2008024221A2/en
Publication of WO2008024221A3 publication Critical patent/WO2008024221A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Processors and systems having a micro tag array that reduces data cache access power. The processors and systems include a cache that has a plurality of datarams, a processor pipeline register (Fig. 4 Ref. 402), and a micro tag array (Ref. 410). The micro tag array is coupled to the cache and the processor pipeline register. The micro tag array stores base address data bits or base register data bits, offset data bits, a carry bit, and way selection data bits. When a LOAD or a STORE instruction is fetched, at least a portion of the base address and at least a portion of the offset of the instruction are compared to data stored in the micro tag array. If a micro tag array hit occurs, the micro tag array generates a cache dataram enable signal. This signal enables only a single dataram of the cache.
PCT/US2007/017896 2006-08-18 2007-08-15 Micro tag reducing cache power WO2008024221A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2007800369813A CN101523359B (en) 2006-08-18 2007-08-15 Processor having a micro tag array that reduces data cache access power, and applications thereof
GB0903127A GB2456636B (en) 2006-08-18 2007-08-15 Processor having a micro tag array that reduces data cache access power and applications thereof

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/505,865 US7650465B2 (en) 2006-08-18 2006-08-18 Micro tag array having way selection bits for reducing data cache access power
US11/505,869 2006-08-18
US11/505,865 2006-08-18
US11/505,869 US7657708B2 (en) 2006-08-18 2006-08-18 Methods for reducing data cache access power in a processor using way selection bits

Publications (2)

Publication Number Publication Date
WO2008024221A2 WO2008024221A2 (en) 2008-02-28
WO2008024221A3 true WO2008024221A3 (en) 2008-08-21

Family

ID=39107291

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/017896 WO2008024221A2 (en) 2006-08-18 2007-08-15 Micro tag reducing cache power

Country Status (2)

Country Link
GB (1) GB2456636B (en)
WO (1) WO2008024221A2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6374342B1 (en) * 2000-01-31 2002-04-16 Kabushiki Kaisha Toshiba Translation lookaside buffer match detection using carry of lower side bit string of address addition
US20030225980A1 (en) * 2002-04-29 2003-12-04 Ip-First, Llc. Microprocessor, apparatus and method for selectively associating store buffer cache line status with response buffer cache line status
US20060090034A1 (en) * 2004-10-22 2006-04-27 Fujitsu Limited System and method for providing a way memoization in a processing environment

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6374342B1 (en) * 2000-01-31 2002-04-16 Kabushiki Kaisha Toshiba Translation lookaside buffer match detection using carry of lower side bit string of address addition
US20030225980A1 (en) * 2002-04-29 2003-12-04 Ip-First, Llc. Microprocessor, apparatus and method for selectively associating store buffer cache line status with response buffer cache line status
US20060090034A1 (en) * 2004-10-22 2006-04-27 Fujitsu Limited System and method for providing a way memoization in a processing environment

Also Published As

Publication number Publication date
GB0903127D0 (en) 2009-04-08
GB2456636B (en) 2011-10-26
WO2008024221A2 (en) 2008-02-28
GB2456636A8 (en) 2009-07-22
GB2456636A (en) 2009-07-22

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