GB2456636B - Processor having a micro tag array that reduces data cache access power and applications thereof - Google Patents

Processor having a micro tag array that reduces data cache access power and applications thereof

Info

Publication number
GB2456636B
GB2456636B GB0903127A GB0903127A GB2456636B GB 2456636 B GB2456636 B GB 2456636B GB 0903127 A GB0903127 A GB 0903127A GB 0903127 A GB0903127 A GB 0903127A GB 2456636 B GB2456636 B GB 2456636B
Authority
GB
United Kingdom
Prior art keywords
processor
applications
data cache
cache access
tag array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0903127A
Other versions
GB0903127D0 (en
GB2456636A8 (en
GB2456636A (en
Inventor
Ryan Kinter
Matthias Knoth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MIPS Tech LLC
Original Assignee
MIPS Technologies Inc
MIPS Tech LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/505,865 external-priority patent/US7650465B2/en
Priority claimed from US11/505,869 external-priority patent/US7657708B2/en
Application filed by MIPS Technologies Inc, MIPS Tech LLC filed Critical MIPS Technologies Inc
Publication of GB0903127D0 publication Critical patent/GB0903127D0/en
Publication of GB2456636A8 publication Critical patent/GB2456636A8/en
Publication of GB2456636A publication Critical patent/GB2456636A/en
Application granted granted Critical
Publication of GB2456636B publication Critical patent/GB2456636B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
GB0903127A 2006-08-18 2007-08-15 Processor having a micro tag array that reduces data cache access power and applications thereof Expired - Fee Related GB2456636B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/505,865 US7650465B2 (en) 2006-08-18 2006-08-18 Micro tag array having way selection bits for reducing data cache access power
US11/505,869 US7657708B2 (en) 2006-08-18 2006-08-18 Methods for reducing data cache access power in a processor using way selection bits
PCT/US2007/017896 WO2008024221A2 (en) 2006-08-18 2007-08-15 Micro tag reducing cache power

Publications (4)

Publication Number Publication Date
GB0903127D0 GB0903127D0 (en) 2009-04-08
GB2456636A8 GB2456636A8 (en) 2009-07-22
GB2456636A GB2456636A (en) 2009-07-22
GB2456636B true GB2456636B (en) 2011-10-26

Family

ID=39107291

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0903127A Expired - Fee Related GB2456636B (en) 2006-08-18 2007-08-15 Processor having a micro tag array that reduces data cache access power and applications thereof

Country Status (2)

Country Link
GB (1) GB2456636B (en)
WO (1) WO2008024221A2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6374342B1 (en) * 2000-01-31 2002-04-16 Kabushiki Kaisha Toshiba Translation lookaside buffer match detection using carry of lower side bit string of address addition
US20030225980A1 (en) * 2002-04-29 2003-12-04 Ip-First, Llc. Microprocessor, apparatus and method for selectively associating store buffer cache line status with response buffer cache line status
US20060090034A1 (en) * 2004-10-22 2006-04-27 Fujitsu Limited System and method for providing a way memoization in a processing environment

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6374342B1 (en) * 2000-01-31 2002-04-16 Kabushiki Kaisha Toshiba Translation lookaside buffer match detection using carry of lower side bit string of address addition
US20030225980A1 (en) * 2002-04-29 2003-12-04 Ip-First, Llc. Microprocessor, apparatus and method for selectively associating store buffer cache line status with response buffer cache line status
US20060090034A1 (en) * 2004-10-22 2006-04-27 Fujitsu Limited System and method for providing a way memoization in a processing environment

Also Published As

Publication number Publication date
GB0903127D0 (en) 2009-04-08
WO2008024221A2 (en) 2008-02-28
GB2456636A8 (en) 2009-07-22
GB2456636A (en) 2009-07-22
WO2008024221A3 (en) 2008-08-21

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)

Free format text: REGISTERED BETWEEN 20140612 AND 20140618

PCNP Patent ceased through non-payment of renewal fee

Effective date: 20220815