GB2456636A - Processor having a micro tag array that reduces data cache access power and applications thereof - Google Patents
Processor having a micro tag array that reduces data cache access power and applications thereof Download PDFInfo
- Publication number
- GB2456636A GB2456636A GB0903127A GB0903127A GB2456636A GB 2456636 A GB2456636 A GB 2456636A GB 0903127 A GB0903127 A GB 0903127A GB 0903127 A GB0903127 A GB 0903127A GB 2456636 A GB2456636 A GB 2456636A
- Authority
- GB
- United Kingdom
- Prior art keywords
- tag array
- micro tag
- cache
- data bits
- micro
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
Processors and systems having a micro tag array that reduces data cache access power. The processors and systems include a cache that has a plurality of datarams, a processor pipeline register (Fig. 4 Ref. 402), and a micro tag array (Ref. 410). The micro tag array is coupled to the cache and the processor pipeline register. The micro tag array stores base address data bits or base register data bits, offset data bits, a carry bit, and way selection data bits. When a LOAD or a STORE instruction is fetched, at least a portion of the base address and at least a portion of the offset of the instruction are compared to data stored in the micro tag array. If a micro tag array hit occurs, the micro tag array generates a cache dataram enable signal. This signal enables only a single dataram of the cache.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/505,869 US7657708B2 (en) | 2006-08-18 | 2006-08-18 | Methods for reducing data cache access power in a processor using way selection bits |
US11/505,865 US7650465B2 (en) | 2006-08-18 | 2006-08-18 | Micro tag array having way selection bits for reducing data cache access power |
PCT/US2007/017896 WO2008024221A2 (en) | 2006-08-18 | 2007-08-15 | Micro tag reducing cache power |
Publications (4)
Publication Number | Publication Date |
---|---|
GB0903127D0 GB0903127D0 (en) | 2009-04-08 |
GB2456636A8 GB2456636A8 (en) | 2009-07-22 |
GB2456636A true GB2456636A (en) | 2009-07-22 |
GB2456636B GB2456636B (en) | 2011-10-26 |
Family
ID=39107291
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB0903127A Expired - Fee Related GB2456636B (en) | 2006-08-18 | 2007-08-15 | Processor having a micro tag array that reduces data cache access power and applications thereof |
Country Status (2)
Country | Link |
---|---|
GB (1) | GB2456636B (en) |
WO (1) | WO2008024221A2 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6374342B1 (en) * | 2000-01-31 | 2002-04-16 | Kabushiki Kaisha Toshiba | Translation lookaside buffer match detection using carry of lower side bit string of address addition |
US20030225980A1 (en) * | 2002-04-29 | 2003-12-04 | Ip-First, Llc. | Microprocessor, apparatus and method for selectively associating store buffer cache line status with response buffer cache line status |
US20060090034A1 (en) * | 2004-10-22 | 2006-04-27 | Fujitsu Limited | System and method for providing a way memoization in a processing environment |
-
2007
- 2007-08-15 GB GB0903127A patent/GB2456636B/en not_active Expired - Fee Related
- 2007-08-15 WO PCT/US2007/017896 patent/WO2008024221A2/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6374342B1 (en) * | 2000-01-31 | 2002-04-16 | Kabushiki Kaisha Toshiba | Translation lookaside buffer match detection using carry of lower side bit string of address addition |
US20030225980A1 (en) * | 2002-04-29 | 2003-12-04 | Ip-First, Llc. | Microprocessor, apparatus and method for selectively associating store buffer cache line status with response buffer cache line status |
US20060090034A1 (en) * | 2004-10-22 | 2006-04-27 | Fujitsu Limited | System and method for providing a way memoization in a processing environment |
Also Published As
Publication number | Publication date |
---|---|
WO2008024221A2 (en) | 2008-02-28 |
GB2456636A8 (en) | 2009-07-22 |
GB2456636B (en) | 2011-10-26 |
GB0903127D0 (en) | 2009-04-08 |
WO2008024221A3 (en) | 2008-08-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) |
Free format text: REGISTERED BETWEEN 20140612 AND 20140618 |
|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20220815 |