WO2008016844A3 - Non-volatile memory capable of correcting overwritten cell - Google Patents
Non-volatile memory capable of correcting overwritten cell Download PDFInfo
- Publication number
- WO2008016844A3 WO2008016844A3 PCT/US2007/074564 US2007074564W WO2008016844A3 WO 2008016844 A3 WO2008016844 A3 WO 2008016844A3 US 2007074564 W US2007074564 W US 2007074564W WO 2008016844 A3 WO2008016844 A3 WO 2008016844A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- reset
- resistance
- level
- cells
- volatile memory
- Prior art date
Links
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5685—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using storage elements comprising metal oxide memory material, e.g. perovskites
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
- G11C16/3413—Circuits or methods to recover overprogrammed nonvolatile memory cells detected during program verification, usually by means of a "soft" erasing step
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/009—Write using potential difference applied between cell electrodes
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5641—Multilevel memory having cells with different number of storage levels
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/30—Resistive cell, memory material aspects
- G11C2213/32—Material having simple binary metal oxide structure
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/30—Resistive cell, memory material aspects
- G11C2213/33—Material including silicon
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/30—Resistive cell, memory material aspects
- G11C2213/34—Material includes an oxide or a nitride
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/71—Three dimensional array
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/72—Array wherein the access device being a diode
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Static Random-Access Memory (AREA)
Abstract
A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of resistance to a reset state at a second level of resistance. Certain memory cells in a set of cells that was reset may be deeply reset to a level of resistance beyond a target level for the reset state. A second reverse bias is applied to the set of memory cells to move the resistance of each cell that was deeply reset toward the target level of the reset state. A smaller reverse bias than used for the reset operation can shift the resistance of the cells back toward the set level and out of their deeply reset condition. The operation is self-limiting in that cells stop their resistance shifts upon reaching the target level. Cells that were not deeply reset are not affected.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/461,431 | 2006-07-31 | ||
US11/461,424 | 2006-07-31 | ||
US11/461,424 US7495947B2 (en) | 2006-07-31 | 2006-07-31 | Reverse bias trim operations in non-volatile memory |
US11/461,431 US7492630B2 (en) | 2006-07-31 | 2006-07-31 | Systems for reverse bias trim operations in non-volatile memory |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2008016844A2 WO2008016844A2 (en) | 2008-02-07 |
WO2008016844A3 true WO2008016844A3 (en) | 2008-03-27 |
Family
ID=38863123
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2007/074564 WO2008016844A2 (en) | 2006-07-31 | 2007-07-27 | Non-volatile memory capable of correcting overwritten cell |
Country Status (2)
Country | Link |
---|---|
TW (1) | TWI356415B (en) |
WO (1) | WO2008016844A2 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7522448B2 (en) | 2006-07-31 | 2009-04-21 | Sandisk 3D Llc | Controlled pulse operations in non-volatile memory |
WO2008016833A2 (en) * | 2006-07-31 | 2008-02-07 | Sandisk 3D Llc | Increasing write voltage pulse operations in non-volatile memory |
US7719874B2 (en) | 2006-07-31 | 2010-05-18 | Sandisk 3D Llc | Systems for controlled pulse operations in non-volatile memory |
US7978507B2 (en) | 2008-06-27 | 2011-07-12 | Sandisk 3D, Llc | Pulse reset for non-volatile storage |
TWI480980B (en) * | 2012-09-26 | 2015-04-11 | Lin Chrong Jung | Memory array and non-volatile memory device of the same |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5818749A (en) * | 1993-08-20 | 1998-10-06 | Micron Technology, Inc. | Integrated circuit memory device |
US6483734B1 (en) * | 2001-11-26 | 2002-11-19 | Hewlett Packard Company | Memory device having memory cells capable of four states |
WO2003085675A2 (en) * | 2002-04-04 | 2003-10-16 | Kabushiki Kaisha Toshiba | Phase-change memory device |
EP1426971A2 (en) * | 2002-12-05 | 2004-06-09 | Sharp Kabushiki Kaisha | Semiconductor memory device and metohd for correcting memory cell data |
US20040114419A1 (en) * | 2002-12-13 | 2004-06-17 | Lowrey Tyler A. | Method and system to store information |
US20040264234A1 (en) * | 2003-06-25 | 2004-12-30 | Moore John T. | PCRAM cell operation method to control on/off resistance variation |
US20050226067A1 (en) * | 2002-12-19 | 2005-10-13 | Matrix Semiconductor, Inc. | Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material |
US20060109704A1 (en) * | 2004-11-06 | 2006-05-25 | Sun-Ae Seo | Nonvolatile memory device using resistor having multiple resistance states and method of operating the same |
WO2006121837A2 (en) * | 2005-05-09 | 2006-11-16 | Sandisk 3D Llc | Nonvolatile memory cell comprising a diode and a resistance-switching material |
US20070069276A1 (en) * | 2005-09-28 | 2007-03-29 | Scheuerlein Roy E | Multi-use memory cell and memory array |
-
2007
- 2007-07-27 WO PCT/US2007/074564 patent/WO2008016844A2/en active Application Filing
- 2007-07-27 TW TW96127570A patent/TWI356415B/en not_active IP Right Cessation
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5818749A (en) * | 1993-08-20 | 1998-10-06 | Micron Technology, Inc. | Integrated circuit memory device |
US6483734B1 (en) * | 2001-11-26 | 2002-11-19 | Hewlett Packard Company | Memory device having memory cells capable of four states |
WO2003085675A2 (en) * | 2002-04-04 | 2003-10-16 | Kabushiki Kaisha Toshiba | Phase-change memory device |
EP1426971A2 (en) * | 2002-12-05 | 2004-06-09 | Sharp Kabushiki Kaisha | Semiconductor memory device and metohd for correcting memory cell data |
US20040114419A1 (en) * | 2002-12-13 | 2004-06-17 | Lowrey Tyler A. | Method and system to store information |
US20050226067A1 (en) * | 2002-12-19 | 2005-10-13 | Matrix Semiconductor, Inc. | Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material |
US20040264234A1 (en) * | 2003-06-25 | 2004-12-30 | Moore John T. | PCRAM cell operation method to control on/off resistance variation |
US20060109704A1 (en) * | 2004-11-06 | 2006-05-25 | Sun-Ae Seo | Nonvolatile memory device using resistor having multiple resistance states and method of operating the same |
WO2006121837A2 (en) * | 2005-05-09 | 2006-11-16 | Sandisk 3D Llc | Nonvolatile memory cell comprising a diode and a resistance-switching material |
US20070069276A1 (en) * | 2005-09-28 | 2007-03-29 | Scheuerlein Roy E | Multi-use memory cell and memory array |
WO2007038665A1 (en) * | 2005-09-28 | 2007-04-05 | Sandisk 3D Llc | Memory cell comprising switchable semiconductor memory element with trimmable resistance |
Also Published As
Publication number | Publication date |
---|---|
TWI356415B (en) | 2012-01-11 |
WO2008016844A2 (en) | 2008-02-07 |
TW200830315A (en) | 2008-07-16 |
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