TW200830315A - Method of operating non-volatile storage and non-volatile memory system - Google Patents

Abstract

A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of resistance to a reset state at a second level of resistance. Certain memory cells in a set of cells that was reset may be deeply reset to a level of resistance beyond a target level for the reset state. A second reverse bias is applied to the set of memory cells to move the resistance of each cell that was deeply reset toward the target level of the reset state. A smaller reverse bias than used for the reset operation can shift the resistance of the cells back toward the set level and out of their deeply reset condition. The operation is self-limiting in that cells stop their resistance shifts upon reaching the target level. Cells that were not deeply reset are not affected.

Description

200830315 IX. Description of the Invention: [Technical Field] The embodiments according to the present disclosure relate to an array comprising non-volatile memory cell arrays, in particular, those incorporating passive component memory cells. Body circuit. Μ [Prior Art] A variety of non-volatile semiconductor-based memory devices are formed using materials with a detectable level of state change (such as a resistance or phase change). For example, a simple antifuse is used to store binary data in a field programmable (〇Τρ) memory array by assigning one of the memory cells to the first body state of the resistor. A logic state (e.g., logic "〇,,) assigns one of the higher resistance entity states of the cell to a second logic state (e.g., logic "1"). Some materials can switch their resistance to ^ in the direction of their initial resistance. These materials can be used to form rewritable memory cells. Multiple levels of detectable resistance in the material can be further used to form a multi-state device that may or may not be rewritten. , 'The material with 5 honest effects (such as a detectable resistance level) is often placed in series with the - guiding element to form a _ memory device H • #线9传' current diode or other The device-like system is used as the guiding element ^2 in the Xu Xibei Shi scheme, a group of character lines and bit line systems are configured as one: the vertical group of sadness, the memory cell is in each word line With the bit:: Hand in and out. The memory units of the two terminals may be constructed at the MH terminals (eg, the terminal portion of the unit or the separate layer of the unit) and the conductors forming the individual word lines are in contact with each other and the other terminal is formed with 123008.doc 200830315 The conductor of the bit line is in contact. In such cases, 'a non-volatile memory array having a passive component of a passive component containing a switchable resistive material or a phase change material is implemented as a second, changing element during a read and write operation. Bias conditions are an important test. In a trial production, it is possible to reliably manufacture, program, and read - or a plurality of passive component memory cell arrays - memory devices recapture / rabbit leakage current, program interference, read interference, etc. may cause difficulties. • For example, these factors often limit system performance by reducing the number of cells that can be addressed simultaneously to keep the leakage current at an acceptable level. Small differences between individual "study units may also be difficult when I'm addressing multiple units individually or simultaneously for frequent bandwidth reading and program operations. A particular unit may have characteristics that may cause the resistance to exceed a range associated with one of the post-operational lean states. For example, a particular cell may experience a different amount of resistance offset than other cells that are subjected to the same bias conditions. • SUMMARY OF THE INVENTION The present invention discloses a reverse bias adjustment operation for a reset state of a non-volatile memory system. A non-volatile 'return' body unit including a resistance changing element undergoes a reverse bias reset operation to change its resistance from a position of one of the first resistance levels to a second resistance level Pre-set - reset the status. The specific memory cell depth in a reset cell can be reset to a resistance level that exceeds a target level for the reset state. A second reverse bias is applied to the set of memory cells to move the resistance of each cell that has been depth reset toward the target level of the 123008.doc 200830315 = reset state. The smaller reverse bias voltage compared to the reverse bias used for the weight can be offset from the set level by the offset, and the depth reset operation is self-limiting. Because the unit is reaching the target level: its resistance is offset. Units that are not re-set in depth are not affected by the change. In a specific embodiment, a method of operating a non-material storage is provided, which includes applying a first to a plurality of non-volatile storage elements.

The bias voltage shifts the resistance of each of the storage elements from the first resistance state to the second resistance state in the -first direction. The method then applies a second level of reverse bias to the plurality of scale elements to: the plurality of storage elements having a resistance that exceeds a target resistance level for the second resistance state _ subset - the resistor moves on the _second toward the target resistance level. In a specific embodiment, a method of operating a non-volatile storage is provided that includes including the storage elements by applying a reverse bias to a plurality of non-volatile storage elements. The lower resistance state switches to a higher resistance state. Applying a first: level reverse bias to the storage elements after switching to reduce a subset of the storage elements having a resistance that exceeds a target level corresponding to the second resistive sorrow One resistance. In a specific embodiment, a non-volatile memory system is provided, comprising: a plurality of non-volatile storage elements having at least a resistance change element and a control circuit in communication with the plurality of non-volatile health care cattle . The control circuit performs a reset operation including: resetting the storage elements from a lower resistance state by applying at least one reverse bias reset voltage to the plurality of _123008.doc 200830315 Resetting to a higher power p and resetting the state; and applying at least one reverse bias voltage adjustment voltage to the plurality of non-volatile storage elements to reduce a target value exceeding a reset state for the second higher resistance One of a plurality of subsets of the plurality of non-volatile storage elements of the resistor. [Embodiment] FIG. 1 illustrates an exemplary structure in which one of the non-volatile memory cells can be used in accordance with a specific embodiment of the present disclosure. A two-terminal memory unit 100 as shown in FIG. 1 includes a first terminal portion connected to one of the first conductors 110 and a second terminal portion connected to one of the second conductors 112. The memory unit includes a boot device 102 in series with a state change element 1〇4 and an antifuse 1〇6 to provide non-volatile data storage. The guiding element can take the form of any suitable device (e.g., a simple diode) that exhibits a non-linear conduction current characteristic. The state change element will vary from embodiment to embodiment and may include many types of materials to store data via a representative physical state. The state changing element 1〇4 may include a resistance change material, a phase change electric P, a material, and the like. For example, a passive storage element 形成 is formed in a particular embodiment using a half-body or other material having two levels of detectable resistance change (e.g., low to high and high to low). By assigning the logical data value to a resistor that can be set and changed from the resistance change element 104: various levels, the memory unit can just provide reliable feed/write capability. Conversely, it is possible to further provide a resistance state change capability that can be applied to non-volatile data storage. Anti-(four) system manufacturing 123008.doc 200830315 ^ A high resistance state and can be tripped or melted into a lower resistance. The antifuse is generally non-conductive when in its initial state and exhibits high conductivity under low resistance conditions in its tripped or fused state. Since a dissipative device or component can have a resistance and a different resistance state, the term resistivity and resistivity states are used to indicate the properties of the material itself. A resistivity changing material may have a resistivity state, although a resistive changing element or device may have a t-resistive state. The p-fuse 1〇6 can provide the memory cell 100 with an excellent point beyond its state change capability. For example, an anti-fuse can be used to set the on-resistance of the memory cell to an appropriate level relative to a read write circuit associated with the cell. These circuits are typically used to trip the anti-fuse and have an associated resistance voltage m and other circuit drive voltage and current levels to trip the anti-fuse 'so during the subsequent operation' the anti-solving filament tends The memory cell is set to an appropriate turn-on resistance state for one of the same circuits. Other terminal 35 non- > volatile memory cells may be used in the specific embodiment. For example, a particular embodiment does not have an antifuse 106 and only includes state changing element 1〇4 and guiding element 1〇2. Other embodiments may include additional state changing elements as an alternative to the antifuse * element or additional element. Various suitable memory cells are described in U.S. Patent No. 6,034,882, the disclosure of which is incorporated herein by reference. Various other types of units may be used, including those described in the following patents: U.S. Patent No. 6,420,215 and U.S. Patent Application Serial No. _97,7() 5, entitled "Incorporating Series Chains A three-dimensional memory array of a diode stack is applied at 123008.doc -11- 200830315 on June 29, 20; and in US patents, serial number 〇9/56〇626, whose name is " "Three-dimensional memory arrays and methods of manufacture", which are hereby incorporated by reference in its entirety in its entirety in the entire entire entire entire entire entire entire entire entire disclosure The material exhibits a resistivity change characteristic suitable for implementing the state change element 104. Examples of materials suitable for the resistance state change element 104 include, but are not limited to, doped semiconductors (eg, 'polycrystalline, but more generally Spar), transition metal oxides, composite metal oxides, programmable metallization connections, phase change resistors, organic material variable resistors, carbon polymer film 'doped chalcogenide glass' and include modification a Schottky barrier diode of a variable electrical resistance atom. In some cases, the resistivity of such materials can be set only in a first direction (eg, from high to low). In other cases, the resistivity can be set from a first level (eg, higher resistance) to a second level (eg, a lower level) and then reset back to the first resistivity. A range of resistance values can be assigned to an entity data state to accommodate differences between devices and changes within the device after a set and reset cycle. Term setting and resetting are generally used to indicate that a component is being used. A high resistance physical state changes to a low resistance physical state (set) and a procedure for changing a component from a low resistance physical state to a high resistance physical state (reset). Embodiments in accordance with the present disclosure may be used The memory unit is set to a lower resistance state or the memory unit is set to a higher resistance state. Although a specific specification can be provided with respect to the setting or reset operation 123008.doc - 12-200830315 Example, but it should be understood that the examples such as & are merely examples and the disclosure is not limited thereto. The conductors 110 and 112 are generally orthogonal to each other to form a memory cell array. Array terminal lines. Array terminal lines (also referred to as array lines) in one layer may be referred to as word lines or X lines. Array lines in a vertically adjacent layer may be referred to as bit lines or gamma lines. It can be formed at the intersection of each sub 7G line and each bit line, and is connected between the individual cross sub 7G line and the bit line (as shown in the figure for the formation of the memory unit 1) One of the three-dimensional memory arrays having at least two memory cell levels (ie, two memory planes) may utilize more than one word line and/or more than one bit line. A monolithic three-dimensional memory array is one in which an array of a plurality of memory levels is formed on a single substrate (e.g., a wafer) without an interposed substrate. Figures 2A and 2B are a more detailed illustration of exemplary memory cartridges that may be used in various embodiments. In Fig. 2A, a memory cell 丨 2 形成 is formed between the first and second metal conductive layers 110 and 112. The memory cell includes a p_i-n type dipole having a heavily doped n-type region 122, an intrinsic region 124, and a heavily doped germanium region 126. In other embodiments, region 122 can be p-type and region 126 can be type 11. Region 124 is essential or not intentionally doped, but in some embodiments it may be lightly doped. Undoped regions may not be extremely electrically neutral, but defects, contaminants, etc., which cause their properties to be as mild as n-doping or p-doping. We still consider this diode to be a type of diode with an intrinsic intermediate layer. Other types of diodes can also be used, such as a junction dipole 123008.doc -13 - 200830315 between the doped p-type region 126 and the conductor 110. The anti-fuse 128 exhibits substantially non-conductive properties in its initial state and exhibits substantially conductive characteristics in its $-deuterium state. Each type of anti-solvent can be used depending on the specific & example. In a generally manufactured reverse dissolution filament, a large bias applied across the antifuse will fuse to form a material such that the reversely soluble filament becomes substantially electrically conductive. This operation is generally referred to as tripping the anti-melting φ wire. The memory unit 120 further includes a state changing element formed of one or more of the diodes. It has been found that the material used to form the diode in some memory cells exhibits a resistance change capability. For example, in one embodiment, the essential region of the diode is formed of polysilicon, which is shown to have a lower resistivity state from a higher resistivity state and then from the lower The ability of the resistivity state to return to a higher resistivity state. Therefore, the diode itself or a part thereof can also form the state changing element 104 as shown in Fig. 1. In other embodiments, one or more additional layers may be included in memory unit 120 to form a state change element as shown in FIG. For example, an additional layer of polycrystalline germanium, over-metal oxide, etc. as described above may be included in the cell to provide a state «change memory effect. This additional layer may be included between the diode and conductor 112, between the diode and the antifuse 128 or between the antifuse and conductor 110. Figure 2B illustrates a simple memory cell configuration in which an antifuse 128 is absent. Memory unit 140 includes only heavily doped n-type regions 142, 123008.doc -14 - 200830315 essential regions 144 and heavily doped p-type regions 146. One or more of the diodes formed by such regions are used as the memory effect for the unit as described above. In one embodiment, memory unit 14A may also include other layers to form additional state changing elements for one of the units. Figures 3A through 3B illustrate one portion of an exemplary single-rock three-dimensional memory array that can be used in an embodiment. However, other memory structures can be used in accordance with various embodiments, including two-dimensional memory structures fabricated on, above, or within a semiconductor substrate. However, the word lines and bit line layers are coherent between the memory cells in the structure illustrated in the perspective view of Figure 3A. This group of griefs is often referred to as a completely mirrored structure. A plurality of substantially parallel and coplanar conductors form a first set of bit lines 162 at a first memory level L. A memory cell 152 at level L0 is formed between the bit lines and adjacent word lines. In the configuration of Figures 3A through 3B, word line 164 is shared between memory layers L0 and L1 and thus further coupled to memory unit 170 at memory level L1. A third set of conductors forms a bit line 174 for the cells of level L1. These bit lines 174 are in turn shared between the memory level L1 and the memory level £2, as illustrated in the cross-sectional view of Figure 3B. The memory unit 178 is connected to the bit line and the word line 176 to form a third memory level L2, and the memory unit 182 is connected to the sub-element 176 and the bit line 180 to form a fourth memory level, and the memory The body unit 186 is connected to the bit line U0 and the word line 184 to form the syllabary level L5. The configuration of the polarities of the diodes and the individual configuration of the word lines and bit lines can vary from embodiment to embodiment. In addition, more or less than five memory levels can be used. 123008.doc -15- 200830315 If a p_i-n diode is used as the guiding element of the memory cells in the embodiment of FIG. 3A, the diode of the memory cell 17 can be relative to the first The hierarchical memory unit 152ip_i_n is formed by the diode. For example, if the cell 152 includes an n-type bottom heavily doped region and a P-type top heavily doped region, then in the second-level cell i 7〇, the bottom heavily doped region may be p-type and the top The heavily doped regions are n-type. In an alternate embodiment, an interlevel dielectric can be formed between adjacent memory levels. No conductors are shared between memory levels. Such structures for two-dimensional single stone storage memories are often referred to as a non-mirror structure. In some embodiments, adjacent memory levels of shared conductors and adjacent memory levels of shared conductors may be stacked in the same single-crystal two-dimensional memory array. In other embodiments, some of the conductive systems are shared while other conductors are not shared. For example, in some configurations only these word lines or only those bit lines can be shared. A first memory level can include a memory cell between a bit line level BL0 and a word line level WL. The word lines at level WL0 may be shared to form a unit connected to a second bit line BL1 at a memory level L1. The bit line layers are not shared, so the next layer can include an interlevel dielectric to separate the bit line BL1 from the next level of conductor. This type of configuration is often referred to as semi-mirror. The memory levels do not have to be formed to have similar (four) units. If necessary, the memory level of the material used to change the resistance can be alternated with the memory level of other types of memory cells. The memory array layout of the memory array line is configured as described in the US Patent No. 7, pp. 54, 219 (the name is "for the close spacing application 123008.doc -16 - 200830315, The word line segments are placed using the word line segments placed on the +phan* g sub-layer layer of the array to form the word-mesh by "vertical connection". Each word line resides. On a separate layer and substantially vertically aligned (although on a certain layer, there is a small lateral offset on the display)

The word lines can be collectively referred to as - columns. Preferably, the word lines in the _ column share the 4-bit portion of the column address. Similarly, the bit lines that reside on the separate layer and are substantially vertically aligned (again, although there is a small lateral offset on some layers) can be collectively referred to as a row. Preferably, the bit lines within a row share at least a portion of the row address. 4 is a block diagram of an integrated circuit including a memory array 2〇2. The array terminal lines of the memory array 202 include layers of word lines organized as columns and bit lines of each layer organized into rows. The integrated circuit 2A includes a column control circuit 220, and the output 2〇8 of the column control circuit 22 is connected to individual word lines of the memory array 202. The column control circuit receives a group of M column address signals and one or more various control signals, and may generally include both a column decoder 222, an array terminal driver 224, and a block selection circuit 226 for both capture and A circuit that writes (ie, stylizes) operations. The integrated circuit 200 further includes a row control circuit 21, and the input/output 206 of the row control circuit 21 is connected to individual bit lines of the memory array 202. The row control circuit 206 receives a set of N row address signals and one or more various control signals, and may generally include, for example, a row decoder 212, an array terminal receiver or driver 214, a block selection circuit 216, and a read. / Write circuits and circuits such as I/O multiplexers. Circuitry such as column control circuit 22 and row control circuit 210 may be collectively referred to as a control circuit or as an array termination circuit because it is connected to each of the array terminals of memory 128008.doc -17-200830315 body array 2G2. Integral circuits incorporated into a memory array typically subdivide the array into sub-arrays or blocks that are sometimes large in number. The blocks can be further grouped together into a rack of packages 3, for example, 16, 32 or a different number of blocks. In the case of S, the sub-array is a continuous group of memory cells with characters and bits that are generally not broken by decoders, drivers, sense amplifiers, and input/output circuits. Yuan line. This is based on any of a variety of reasons. For example, signal delays (i.e., RC delays) that traverse along the lines due to the resistance and capacitance of the word lines and bit lines can be quite significant in a large array. These RC delays can be reduced by subdividing a larger array into a smaller group of sub-arrays such that the length of each word line and/or each bit line is reduced. As another example, the power associated with accessing a group of memory cells can indicate an upper limit on the number of memory cells that can be simultaneously accessed during a given memory cycle. Therefore, a larger memory array is often subdivided into smaller sub-arrays to reduce the number of memory cells accessed simultaneously. However, for ease of illustration, the array may also be used synonymously with the sub-array to represent a continuous group of consecutive characters and bit lines that are generally not broken by the decoder, driver, sense amplifier, and input/output circuitry. Group memory unit. An integrated circuit can include one or more memory arrays. Figure 5 is a graph illustrating a resistance distribution for a state of a set of memory cells in a non-volatile memory system, in accordance with an embodiment. The exemplary memory system depicted in Figure 5 utilizes four resistive states, but may be combined with a system utilizing different numbers and/or combinations of resistive states. 123008.doc • 18· 200830315 uses specific embodiments in accordance with the present disclosure. Line 250 is used to illustrate the original (or initial) state of the set of memory cells. The resistance distribution for the cells in their initial state after fabrication is shown as a function of the probability of the conduction current of the cell at a selected voltage bias (e.g., 2 V). The original state of the cells after fabrication is a relatively high resistance state having a conduction current of about 10'A to 1〇-9Α at the selected voltage.

One of the trip states of the device is illustrated on line 252. State 252 corresponds to one of the lowest resistance states of the device. The device in state 252 exhibits a conduction current of about 1 〇 5 在 at the voltage level of 2 V as illustrated in FIG. In one embodiment, the memory cell can be set from its highest resistance initial state to the lowest resistance trip state by tripping an antifuse. In other specific examples, the resistivity of a resistance changing material such as polycrystalline or a metal oxide can be switched to set the cell to this lower resistance state. In one embodiment, tripping an antifuse to set the device to one of the trip states as illustrated by line 252 includes applying a greater forward bias to the cells, such as about 8 volts. Other techniques, bias conditions, and/or voltage levels can also be used for such operations. Line 254 illustrates the resistance distribution for the set of memory cells after resetting to a higher resistance reset state from the lower resistance state illustrated by line 252. The memory cell in this re-stated state exhibits a conduction current of about 10 to 1 〇- at the (iv) plus 电压 voltage level. The reset state is at - lower resistance than the higher resistance initial state, but may be at - higher resistance in other embodiments. In a particular embodiment, a reverse bias reset operation as described below can be used to reset the resistance of the memory cell from state 252 to state 254. For example, in one embodiment, the resistivity of one of the resistivity changing materials in each cell can be increased by subjecting the memory cells to a reverse bias of one of about -10 V to -12 V. Line 256 illustrates one of the set states of the memory cells. The memory cell can be set from its higher resistance reset state 254 to a lower resistance set state 256. The memory cell in the set state 256 has a conduction current of about 1 〇 6 在 at the applied 2 V voltage level. The single turn resistance in the set state 256 is less than the resistance of the cells in the trip state 252 but lower than the resistance of the cells in the reset state 254. In one embodiment, the resistance of a memory cell can be switched from reset state 254 to set state 256 using a forward bias of about +8 V. In other embodiments, other bias conditions and/or voltage levels can be used to set the memory cells. The four resistance states illustrated in Figure 5 can be used to form various types of memory systems. In one embodiment, the reset state transition is used to perform a stylized operation in the secondary programmable memory array. One of the memory cells of a resistance change element is set from the initial state 25 〇 factory to the lower resistance state 252. The memory array including the memory unit is then provided to an end user. The lower resistance state obtained by setting the unit from its initial state of the resistor during manufacture corresponds to the single formatted or unprogrammed state. The memory array is provided to circuitry to reset the selected memory unit to a higher resistance state 254 in accordance with data received from an end user or host device in communication with the memory unit. In another embodiment, the four resistance states are used to form a multi-state memory system. The memory unit can be programmed from the initial state 250 to any of the states 252, 254, or 256 (or retained in state 250) based on the user profile. In one such embodiment, each unit can store 2 bits of data. In another embodiment, a rewritable memory system can be formed. The cell can be set to state 256 and then reset multiple times back to state 254 to form a one-bit rewritable array. Other types of memory systems may also be used in accordance with specific embodiments, including, by way of non-limiting example: US Patent Application No. _% (MD-294Y, attorney docket number 1〇519-141), entitled "Multiple Use memory unit and memory array "; US Patent Application No. - (MD-296Y Lawyer File Number 1〇519-142), the name is "mixed memory array"; US patent application ---- (MD-310Y lawyer file number 10519_149), the name is a mixed memory array with different data status "; and the US patent application No. - 1 (lawyer file number) \ ^ - 163 1), the name is "Method of using a memory cell containing one of the switchable semiconductor memory elements with adjustable resistance". - Biasing a single-array memory array for reading, setting, or resetting states, can cause program disturb, read interference, and high-wave leakage that may affect the power consumption and reliability of such read and program operations = For example, when a particular memory cell within the __ array is selected for a particular stay, the bias conditions can cause an A leakage current that is inadvertently passed through unselected memory 123008.doc -21 - 200830315. Although a guiding element is used within the memory array, there can be such a leakage current. A diode of a memory cell that is not selected may conduct a small amount of current when subjected to a small positive or negative bias condition. For example, the forward bias reset operation will be implemented in some two-terminal memory arrays as an erase operation. In these! Applying a low voltage or grounding condition to a sub-turned line of a 疋1, 疋 by applying a large voltage to a selected bit line under the condition of a bit line to a character state. To generate a #x A (five) positive bias. The unselected bit line can be at - a smaller positive bias and the unselected word it is at - a larger positive bias. In the case of biasing the :: body array in this manner, in some cases there may be via selected cells along the half of the word line or bit line and via the unselected sub-line and An unacceptable level of current in the unselected cells of the bit line, and an unacceptable level of leakage current during the forward bias setting operation (which can be used to program a memory array). The cumulative effect of the smaller $leak current by the unselected single I is limited to the number of selected memory cells that can be operated at time. It has been found that a reverse bias can be applied to a memory cell having a resistance changing element to change the detectable resistance of one of the cells. For example, such materials can be reset from a lower resistivity state to a lower voltage by subjecting a material such as the above-described metal oxide, polysilicon, to a voltage pulse that produces a reverse bias across one of the materials. High resistivity state. In a specific implementation, a reverse bias is applied during a reset operation to minimize leakage current through the array. In some embodiments, a one-way, zero-weight bias can be provided to a particular unselected memory list 123008.doc -22- 200830315 疋. Since these leakage currents are minimized, a larger number of memory cells can be selected for resetting operations. This provides an improvement in the operating instructions by reducing the stylization and/or erasing time. Moreover, such low leakage currents can facilitate more reliable operation by normalizing device performance to an expected level. U.S. Patent Application No.----- (MD-273 Lawyer File Number 023-0048) entitled "Positive Element Memory Array Incorporating Reversible Polar Character Lines and Bit Line Decoders" discloses that Reverse bias operation is minimized by minimizing leakage current through unselected and semi-selected memory cells. Figure 6 is a circuit diagram of a portion of a memory array during a reverse bias operation in accordance with an embodiment. These reverse bias conditions can be used to set the memory cell to a low resistance state or to reset the memory cell to a high resistance state. A specific reference to a reset operation may be made below for convenience, but this does not represent one of the limitations of the bias and technique disclosed in the application. One or more selected word lines are at a positive bias and one or more of the selected bit lines are at a negative bias. For example, the selected word lines can receive one of +1/2 VRR to reset the voltage signal Vwr, and the reset voltage signal VBR drives the selected positioning line with a negative bias of about -1/2 VRR. The VRR resets the number of reverse bias (or negative voltage) required for the memory and can vary from embodiment to embodiment. In an exemplary embodiment, the VRR is about 12 volts such that the selected word line receives +6 volts and the selected locating element lines receive -6 volts to produce a 12 volt reverse bias level. Unselected word lines and bit lines are grounded. The guiding elements for the selected memory cells (denoted as S) are reverse biased, and a reverse current is passed through the resistance changing material for the selected cells. Under this reverse bias condition, the resistance changes material from a first resistance state to a second resistance. The bias conditions illustrated in Figure 6 advantageously provide a zero bias condition for one of the unselected single turns (denoted U). Thus, low leakage current through unselected and semi-selected memory cells during program operation can be obtained. F denotes a selected memory cell along a half of the selected bit line, and η denotes/selects a half selected memory cell of the element line. In addition, the selection of + Λ 1/2 Vrr for the selected array line of the 7th requires a small enough load on the driver circuit to generate the voltage level for the reverse bias reset operation. By dividing the bias voltages across the array lines using positive and negative voltage levels, the driver circuit only needs to produce one-half of the total voltage level required in certain embodiments. Other selected bias conditions can be used to reverse bias the selected memory cells for the -reset operation. For example, in a particular embodiment, a positive voltage bias (e.g., 'VRR) can be applied to selected ground and selected bit lines of ground. Unselected characters and bit lines can each receive + 1/2VRR. This biasing condition will also provide a reverse bias to the selected memory cells. The reverse bias can be reset to return to the higher resistance state after the set operation. For more information on reverse bias operation, please see the US patent application No. _ __ (MD-273 lawyer file number 023 Gu 8), the money is "and the reversible pole (four) characters Passive component memory array for line and bit π line decoders,. / May be in some memory implementations 'targeted-in-re-arranged memory early-array arrays—the resistance distribution may be too wide or include 123008.doc -24 - 200830315 compared to the desired range A wider range of resistors. For example, the resistance distribution for a memory cell in the reset state shown in line 252 of Figure 5 includes a relatively large range of resistance. Some memory cells exhibit a conduction current of about 1 〇-1 at the applied voltage level, while other memory cells in the same solid state exhibit a large conduction current of about 10·7α. These conduction currents demonstrate a large difference in resistance between cells that wish to be in the same reset physical state. Importantly, the depth is reset to a very high-resistance memory cell (the memory cells that are closer to a conduction current of 1〇·8Α) than the memory cells in the original or initial state of 25〇. The separation of the width. In some embodiments, the lack of limits between these two entity states may prove problematic during read and write operations. A larger range of resistance may result in erroneous readings of the data stored in the memory cells. For example, if the depth is reset to a very high resistance unit, the 彳 can not be sufficiently conducted in the case of applying-reading the reference voltage, thereby indicating that it is in the reset physical state. It may be mistaken that these units are in the initial or original state 250. During other operational periods such as stylization F: This may be incorrectly read during a verification step, resulting in an erroneous application of an additional stylized voltage that may not be needed. - According to a specific embodiment, the "adjustment operation or the coincidence-reset operation" provides a smaller resistance distribution for the memory unit in the _reset state. After the memory unit is reset, an adjustment bias can be applied thereto to the set target offset θ_ 〆 - associated with the reset unit. Resetting the memory of the (4) resistor with a ratio of $ can cause its resistance to decrease to 123008.doc •25- 200830315 to match more closely with other units in the reset state. Used in a particular embodiment - self-limiting reverse bias adjustment operation. It has been found that 'applying a small reverse bias voltage to the memory cell increases its resistance without reducing its resistance as in the case of applying a large reverse bias for the reset operation. Figure 5 illustrates the effect of a reverse bias adjustment operation for the -reverse bias reset operation. Line 258 indicates the target resistance (or desired average resistance) of the memory unit in the reset state 2M. . Different resistive materials can provide different target resistance levels depending on their individual characteristics. The target resistance for this reset state can be determined by such characteristics that tend to refer to the resetting level of one of the materials in the most natural case. A certain number of cells have their resistance lower than the target level in Figure 5, while other cells have their resistance above the target level. A reverse bias of a number lower than the reverse bias reset level Vrr is applied, thereby causing the memory cell having a resistance higher than the desired level 258^-resist to shift to a lower resistance. It has been found that a relatively small amount of reverse bias reduces the resistance of the material in a self-limiting manner. A cell having a resistance at or above a particular level will increase its resistance when subjected to a small reverse bias. However, cells below the • Shore fixed resistance level are not affected by this reverse bias. In a real money. 已 'has been shown to have a similar effect on the cell resistance for the level of the reverse bias voltage. For example, during the operation from state 252 to state 254 = set operation period 'about 1 A reverse bias of 〇ν to 12V can increase the resistance of a selected memory cell by an amount as shown in FIG. A reverse bias voltage equal to about 50% to 60% of the reverse bias applied during the reset operation (eg, 123008.doc -26-200830315, eg, 6 V to 7 V) can be used to increase the memory The resistance of a particular memory cell in the bulk cell that is above a certain level of resistance. The increase in resistance in this adjustment operation is self-limiting because the cells stop reducing the resistance when a particularly large number of resistors is reached. In addition, the cells having only one resistance above the critical level are affected by the adjustment operation. A cell that is already in the proper resistance range does not experience a resistance offset, even if it is subjected to the reverse bias regulation voltage. Therefore, as shown in Figure 5

The cells that do not have a resistance below the target level 258 are unaffected by the reverse bias for the adjustment operation. Figure 7 is a circuit diagram showing one of the reverse bias adjustment operations for a non-volatile memory system reset state in accordance with an embodiment. An adjusted voltage signal Vwt is supplied to one or more selected word lines at a positive voltage level + vTT to apply a reverse bias for the adjustment operation. In a specific embodiment, the VTT is the amount of reverse bias applied to the selected cells during the adjustment. In the biasing case shown in Figure 7, the selected bit line is grounded, so a full amount of adjustment bias is applied to the selected word line at +VTT to produce one of the same number as this one. Reverse bias of the selected unit. In a particular embodiment, the number of reverse biases is adjusted to be equal to about 6% of the total reverse reset bias level of the VRR. Continuing with the above example, if the reverse bias reset potential is equal to about 12v, the reverse bias adjustment level νττ can be about 6¥ or 7¥. Thus, in a = embodiment, +6 V or +7 V is applied to the selected word lines. Eight, other biasing conditions may be used for an adjustment operation in accordance with or in various embodiments of the present disclosure. For example, in a specific embodiment, one of M+1/2VTT is applied to the selected word lines of 123008.doc -27-200830315 and one of the -1/2 VTTs is applied to the selected bit lines. The voltage "reverse bias generated across each cell is the same as previously described (VTT), however, individual biases have been distributed across different types of array lines. Since only those cells requiring resistance offset are affected by the reverse bias adjustment, the operation is independent of the data and can be implemented for high frequency £ applications. In a specific embodiment, a high frequency wide operation is used to simultaneously adjust a one-time adjustment for the adjustment operation.

Large group of memory cells. In an example, the individual bit lines from the block are selected for selecting a memory cell block. One word 7G line and repeat this operation for each word line. In addition, a (four) block can be selected in a P train during the adjustment operation, but in one embodiment, a single-block is selected. With this technique, a large number of units are sub-adjusted so as not to unreasonably affect the bandwidth of the reset operation. In other embodiments, other groups may be used. In a particular embodiment, one or more bit lines and one or more word lines from a plurality of blocks across the array may be selected. Figure 8 is a flow diagram of a method for resetting a memory cell incorporating a reverse bias adjustment operation in accordance with an embodiment. The step and row control circuitry for a memory cell array in step 300 receives the address and control information for the selected cell designated for resetting. For example, a rewritable array can receive (d) an erroneous request for the selected cells, and a write request can be received in the 2 multi-state array. Satisfying the write or erase request may include resetting the selected cells as shown. / In step 302, one or more reset voltage signals of 123008.doc -28-200830315 are applied to the reset unit. The reverse reset bias can be applied across the selected cells by using a voltage combination on the selected characters and the bit lines as described above. For example, in a particular embodiment, the word line voltage signal can include a positive voltage pulse (e.g., +1/2Vrr) and the bit line voltage 'voltage signal VBR includes a negative voltage pulse (e.g., -1/). 2Vrr) with reverse bias - these selected units. In step 304, if there is still a memory unit to be reset, the method returns one or more additional pulses, or if all the units to be reset have received a reset voltage pulse. Continue to step 3〇6. In a specific embodiment, a smaller portion of the array can be subjected to individual reset pulses to minimize leakage current through the semi-selected or unselected cells. For example, in one embodiment, each iteration of steps 3〇2 and 3〇4 can be directed to each of a plurality of racks (eg, 16 to 2024 racks or more) from the memory. A pulse (or in more than one of the other cases) applies a pulse until each selected bit line has received a reset voltage pulse. In other embodiments, other numbers of bit lines and/or word lines may be selected in step 302. U.S. Patent Application No. __ (MD-3〇3 Lawyer File No. 023_0052), which is incorporated in the Memory Array of Columns for Memory Array Block Selection. US Patent Application No.--- (MD-307 Lawyer File Number 023-0053) for the name "hierarchical bit line bias bus for block selectable memory arrays A memory array (e.g., array 302) performs techniques for increased parallel access. 123008.doc -29- 200830315 After applying a reverse bias voltage pulse to the selected memory cell, a verify operation is performed by reading back the resistance states of the devices in step 306. Step 306 can include determining whether the resistance of a memory cell has been added to be at or above a minimum critical resistance. Various techniques, including sensing the current or current of a selected cell under a set of reference bias conditions, can be used in step 306 to determine whether to fully reset a memory bank. The device has the name "" for reading a multi-level passive component memory cell array φ, and the US Patent Application No. __ (MD-274 Lawyer File Number 023_0049) description can be used to verify the readback operation. Re-. It is also suitable for reading techniques. In step 3-8, the reset operation is branched for the bit lines having a memory unit that is not sufficiently reset. Applying a retry pulse to the memory cells utilizing the characters and/or bit line voltage signals VwR and Vbr in an optional step 31A, in a particular embodiment, to each of the memory cells having an insufficient reset The pulse is applied simultaneously to the bit line. This bit line can be used to apply individual pulses to various groups. In the particular embodiment, no retry pulses are applied. If a retry pulse is used, then a verification operation is performed for the orders 70 in step 312. If it is determined in step 314 that the unit of the retry operation is not fully re-defined, and the error is corrected in step 3 16 , the unit is managed or the redundant memory is used. Body units are replaced and so on. Due to the reset voltage applied in steps 302 and 314, it is possible to reset the characteristic single-turn depth to a high resistance state as described above. A tighter resistance distribution of the needle to one of the reset states will provide a greater limit between the states 123008.doc -30-200830315, thus providing a more reliable device. Therefore, after successfully verifying the unit in steps 308 and 314 or disposing of any unit that has not been reset in step 316, an adjustment operation is performed in step 3 18 for the unit to be reset. In a specific embodiment, step 3 18 is performed simultaneously for each unit undergoing the reset operation. Since the operation is self-limiting, it is also possible to subject the unit that is not fully or deeply reset to the adjustment bias without negative effects. These units will not experience further resistance shifts. In addition, the cells adjusted to a lower resistance will stop their resistance change when they reach a level associated with the adjustment bias. As described above, in a specific embodiment, a reverse bias voltage VTT is applied to the cells. A small amount of reverse bias is applied in a particular embodiment to reduce the resistance during an adjustment operation rather than increasing the resistance during a reset operation. After the reverse bias adjustment voltage VTT is applied to each cell, the reset operation is completed in step 320. Many variations can be made to the method of Figure 8 in accordance with a particular embodiment. For example, the adjustment operations in step 3 18 may be incorporated after steps 312 and 307 are completed for all of the reconfigured units and before verification is performed in step 306. Figure 9A illustrates one embodiment of a portion of a control circuit 220 that can also be used to apply the reverse bias reset conditions of Figure 6. Column decoder 422 corresponds to a selected word line during the reset pulse and outputs a ground to the NMOS/PMOS word line driver circuit (e.g., 224 in Figure 4). Upper PMOS devices 402 and 404 are turned on for the ground input of the driver circuit. The ground input causes the driver circuit to pass the reverse source 123008.doc • 31- 200830315 select bus signal vWR and _ to the selected word line and each semi-selected word line associated with the decoder, respectively. Each column of decoding 423 corresponding to an unselected word line outputs a v-disc to its individual driver circuit, as shown in Figure 9B. The positive bias of VwR turns on the NMOS devices 416 and 418 of the driver circuits of the unselected word lines. Accordingly, the source selection bus is selected as 'quad (both GND) and driven on each corresponding unselected word line. In one embodiment, as previously described, the word line is reversely re-set φ with a fixed voltage VwR equal to about +1/2 VRR. VWR can also provide other voltage levels. For example, one or more reverse reset voltage pulses having a tilt pulse (e.g., start k + 1/2 Vrr and then increase) can be provided for the reset operation as described below. 10A and 10B are circuit diagrams of portions of a row control circuit 210 that can be used to apply bias conditions for the reverse reset operation. Row decoder 5 12 controls a selected bit line driver to provide the selected bit line voltage pulse VBR. In one embodiment, the vBR provides a voltage pulse of _1/2 Vrr. Row decoder 5 12 may be spread across a plurality of bit line drivers (e.g., 24) and will also connect the semi-selected bit lines to a ground bias just prior to application of the reset pulse. During the application of this pulse, • the semi-selected bit lines float near ground. Semi-selected bit lines • A large number of unselected cells provide leakage current that keeps the semi-selected bit lines close to ground. In a specific embodiment, a memory unit that shares a row of decoders with the selected positioning element during a reset operation may be a semi-selected δ hexon precursor. For example, the cells can be connected to the selected word line during the reset operation. The selected row decoder 512 outputs (}1^) 123008.doc -32 - 200830315 to the input of the driver circuit for the row decoder. The GND input at the NMOS/PMOS pair of the driver circuit will turn on the lower NMOS device 506. The reverse source select bus level VBR is passed to the selected bit line. The unselected column decoders 5 13 provide VBr to the gates of their individual driver circuits, thereby selecting the PMOS devices at the top of each driver pair. The source select bus signal levels (both at GND) are provided to each unselected word line corresponding to decoder 51. Figure 11A illustrates one embodiment of a portion of a column control circuit 220 that can be used to apply the reverse bias adjustment conditions of Figure 7. The selected column decoder 422 outputs a word line adjustment voltage pulse Vwt to the NMOS/PMOS word line driver circuit. Vwt is a positive voltage and turns on the lower NMOS devices 406 and 408. The driver circuit passes the source select bus signal VWT to the selected word line. Each unselected column decoder 423 outputs GND to its individual driver circuit as shown in Figure 11B. The upper PMOS devices 412 and 414 are turned on and the GND signal from the reverse source select bus is passed to each of the unselected word lines. Figure 10A is a circuit diagram of one portion of a row control circuit 210 that can be used to apply bias conditions for the reverse bias adjustment operation. The selected row decoder 512 controls a selected bit line driver, turns on the upper PMOS devices and passes GND to each bit line selected for the reset operation. This adjustment operation is independent of the data, and a large number of units can be selected at one time under the self-limiting condition of the operation. Thus, each bit line in a selected block receives the GND level signal to apply the reverse bias to adjust the voltage level. 123008.doc -33- 200830315

The driver circuit associated with the column and row decoders illustrated in Figures 9A through 10B can include additional NMOS/PMOS skirt pairs that form driver select circuits for additional word lines and bit lines. For example, each driver set for the column control circuit can include 16, NM 〇 s / pM 〇 s pairs connected to the 16 different word lines of the array and tied A single column decoder is associated. Each driver set for the row control circuit can include 12 NMOS/PMOS pairs, which are connected to 12 different word lines and are Associated with a single row decoder. This configuration is exemplary, and other configurations may be used in accordance with a particular embodiment. However, such a set of evils as described above may advantageously provide this at each memory level. One of the array lines has a reasonable fan-out. It also facilitates placing the drive H circuit at the same distance from the array lines associated with the driver circuit. This configuration avoids various driver voltage levels except for a large number of array lines. Long-distance transmission of the array and thus improved power efficiency. More details regarding the driver and control circuitry used to control a memory array (in the specific embodiment include the selection and unselection of pairs suitable for implementing lean materials) word And / or the selection of the bit line of the E < Scheuerlein ^ Luca - Number (MD-295 law

Fasoli's U.S. Patent Application No. 1 file number G23-GG51) is entitled "Data-Related Dual Bus" for Lightning the Read/Write Circuit to a Memory Array. Differences in device characteristics can affect the characteristics of individual memory cells within memory array 202 during a reverse reset operation as described. The memory cells can have different sizes resulting from the process. There may be a lack of specific uniformity between the devices in the composition of the material (eg, polycrystalline stone, day, day, day, and day). ::, compared to the nominal level of the averaging unit in the array, ^:: can be programmed at a lower voltage, other units can be -higher -j based on the present disclosure - the embodiment is adequately Re- fe fe 兀 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( Thus

Gradually add the inverse (4) applied to the selected memory cells. A unit requiring a newer voltage level will be reset to a higher reverse bias after the amplitude of the voltage pulse has changed, and only the unit requiring a lower reset voltage level will be reset to one. A smaller level of reverse bias. This technique accommodates changes between devices while also providing an efficiency program that does not compromise resetting. Since a single reset voltage pulse can be applied to generate a reverse bias reset condition range, time consuming verify operations are avoided or minimized. The single pulse can be applied across each cell and the amplitude changes to increase the reverse bias. The cell reset at the lower value of the reset voltage pulse will automatically turn off when it is reset to the higher resistance state. The higher resistance after reset will reduce or stop the flow of current through these devices, thereby ensuring that it is not damaged by the higher value of the reset voltage. Figures 13A through 13B illustrate resetting voltages applied to selected word lines and bit lines, respectively, during a reset operation as shown in Figure 6, in accordance with an embodiment. Figure 13A illustrates a word line reset voltage signal Vwr that rises to a maximum of about 123008.doc -35 - 200830315 + 1/2 VRR during the duration of the portion of the illustrated operation (eg, +6) V). A bit line re-set voltage signal VBR having a start value of one -1/2 VRR for each reset voltage pulse is illustrated in Fig. 13B. The reset signal on the bit line has an amplitude that varies according to a substantially constant slope. In Fig. 13B, the bit line reset voltage signal is increased from an initial value of about -1/2 VRR to an end value of about - (1/2 VRR + 2 V). The amplitude amplitude of each negative bit line pulse is increased by about 2 V (e.g., to -8 V) such that the reverse bias applied across the selected portion of the array of φ is gradually increased. The amplitude of the Vbr pulse is limited to the biased bias level shown by the dashed line in Fig. 13B by the output of the electric Ho circuit as shown in Fig. 1B. The Vbr bias level returns to its initial value between the application of the vBR pulses by controlling the counter 712 of Figure 14B. Under the condition that the diode of each memory cell is aligned from the bit line to the word line as shown in FIG. 6, the word line resets the constant value of the voltage and the bit line resets the voltage signal < The increased negative voltage increases the reverse bias applied to each memory cell along the selected positioning line and the selected word line. A voltage signal is reset for the bit line, and a plurality of pulses are displayed that can be used to individually reset a smaller portion of the array. For example, a first reset voltage pulse can be applied to one of the bit lines in each of a plurality of selected blocks (sub-arrays), and to each block in a plurality of selected blocks. One of the second bit lines applies a second pulse. More reset pulses are applied to more bit lines until all data provided by the user is encoded. This technique may require 16 to 64 or more reset voltage pulses in inverse proportion to the number of blocks used to store user data for one page. 123008.doc -36- 200830315 The starting and ending values for vBR can vary from implementation to implementation. In a specific embodiment, statistics or experiments are used to select the optimal start and end values for each pulse. For example, the initial value of the pulse can be selected to produce a reverse bias that is determined to be the minimum value that any cell would need before resetting from the lower resistance state to the higher resistance state. . The end value of each pulse can be selected to produce the maximum reverse bias typically required to reset any cells of the array. By gradually applying an increased reverse bias, resetting the memory unit at a lower reset reverse bias level can avoid damage to the increased reverse bias level. When a memory cell is reset to the higher resistance reset state, it will conduct less current and behave in a self-limiting manner. When it has been successfully reset, it shuts itself down or stops conduction to a sufficient extent. This self-limiting cutoff point will avoid damage under these reverse bias conditions. It should be noted that the amplitude of a reset pulse is gradually increased from a starting value to a larger terminating value to thereby increase the reverse bias for the selected memory cell without having a larger starting value with the application. The same electrical effect of the constant pulse. A pulse having a larger starting value can damage the material forming the resistance changing element or cause a permanent deflection of one of the resistors. Accordingly, one embodiment of the disclosed technology utilizes a tilt reverse reset pulse to successfully and safely erase memory cells having different device characteristics. Figures 12A and 12B illustrate portions of a column control circuit and a row control circuit that may provide a reset voltage signal, respectively, in a particular embodiment. A charge pump 706 of FIG. 14A includes a reverse source select bus line 123008, and a doc-37-200830315 burst generator control circuit provides a reverse reset Vwr bias level to the reverse source. The poles are selected (e.g., bus bars 430 in Figures 9-8) and provided directly to the column decoder circuitry (e.g., decoder 322 in Figure 4). The reference voltage generator 702 receives a supply voltage Vcc and supplies a reference voltage Vref to the charge pump controller 7〇4. Using one of the outputs from charge pump 706 to feed back the signal, the controller can provide one of the starting vWR bias levels of about 1/2 VRR as needed. The row control circuit illustrated in Figure 12B utilizes a counter 712 and a digital to analog converter 714 to generate a bit line reset voltage 乂 (10) bias level having a negative ramp output (negative level and slope). Counter 712 receives a pulse start time and uses a clock signal to provide a pulse input to DAC 714 to produce an analog skew output. The DAC 714 receives the digital input and provides a voltage level to the charge pump controller. The charge pump 718 generates a negative bit line reset voltage VBR that is increased by a substantially constant and negative slope generated by the counter. The amplitude of the negative voltage VBR bias level is increased in accordance with the defined slope to gradually increase the reverse bias applied across the memory array. Figures 15A and 15B illustrate a set of voltage signals instead of one of the reverse biases of Figure 6. A positive voltage pulse VWR is applied to the selected word line and increases in accordance with a positive slope. A negative bit line voltage pulse VBR is applied to the (equal) selected bit line. Each word line voltage pulse begins at about one of the +5 V starting values and increases by 2 V to about +7 V. The magnitude of the VWR pulse is limited to the VWR bias bit rate from the output of the charge pump circuit and is shown as the dashed line in Figure 15A. The combination of the word line and bit line reset pulses 123008.doc -38 - 200830315 will provide an increased reverse bias across each selected memory cell. Additional bit line reset voltage pulses are described as available for setting or resetting additional bit line groups. As shown in Figures 9A through 9B, the pulses of Figures 11A through 11B can be used to generate a forward bias in some embodiments. In another embodiment, the pulses are not oblique. For example, a first voltage pulse having a negative polarity can be applied to a first array line and a second voltage pulse having a positive polarity can be applied to a second array line to generate a reverse bias. This configuration can also switch the resistance of the memory cells' but does not include the slope of one of the pulses or the offset produced by one of the applied biases. The embodiment of Figures 15A and 15B includes a retry technique for using a reset pulse level that is slightly higher by one of the VWR bias levels for a memory cell that is not reset when the initial voltage pulse is applied. . For example, the result of the resetting of a selected portion of the array can be verified after the last reset voltage pulses 8〇4 and 814 are applied. A verify operation can include reading back the resistance state of the memory cell and comparing it to a predefined level for the reset state. Any row or bit line that is not reset can be subjected to a higher level one retry pulse. The initial value of the word line voltage pulse 806 is increased to 7 V and increased to a level of 9 V. The value of any retry pulse can vary from embodiment to embodiment and can be selected based on statistics and/or testing as previously described. This retry pulse is applied to each bit line of the array that has not passed the verification for a reset state in Figs. 15A and 15B. In other embodiments, a retry pulse (or more 123008.doc • 39 - 200830315 pulses) may be applied after each of the initial reset voltage pulses is applied. If a row or other group - the early group of a group fails to pass the verification of the target resistance state after a retry pulse (or multiple retry pulses), the column can be disposed of by the error correction (4) technique. Or replace it with redundant memory.

Figures 6A and 16B# a month may be used to provide portions of the column and row control circuits of Figure η a and other pulses. The selected word line θ is provided with a JL-heavy (four) fixed signal having one of the vibrations added in accordance with a positive slope in this particular yoke example. A counter 904 and a digital to analog converter 9 〇 6 are utilized when driving the charge pump controller 9 (10). Control (4) 9〇8 uses the analog output of DAC 906 and generates a positive tilt and bias level via charge pump 91〇. The output of the charge pump 910 is applied directly to the word line decoder and (iv) the reverse source select bus pulse generation circuit is applied to the reverse source selection bus line. Figure (10) illustrates (d) a portion of the row control circuit 210 that provides a negative % bias level. A reference voltage generator 914 delivers a reference voltage vref to the charge pump controller 916. The controller utilizes one of the outputs from the charge pump 918 to return the loop to maintain a stable value of the vBR bias for resetting the voltage signal for the bit line. The foregoing detailed description of the invention has been presented for purposes of illustration It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above principles. The embodiments were chosen to best explain the principles of the invention and its application, and thus, Various modifications. It is intended that the scope of the invention be defined by the scope of the appended claims. 123008.doc -40 - 200830315 [Simplified Schematic] FIG. 4 is an exemplary non-volatile memory H2 as early as 70. 2A and 2B illustrate exemplary non-volatile memory cells in accordance with an embodiment. 3A and 3B are individual perspective and cross-sectional views of a three-dimensional memory array in accordance with a particular embodiment. Figure 4 is a block diagram of one of the non-volatile memory systems in accordance with a particular embodiment. ‘ Figure 5 is a graph of the resistance distribution of various states of the non-volatile memory system according to the specific embodiment. Figure 6 is a simplified circuit diagram of one of the memory arrays in accordance with one of the bias conditions for the reverse bias reset operation. Figure 7 is a simplified circuit diagram of one of the memory arrays for one of the bias conditions for a reverse bias adjustment operation in accordance with an embodiment. Figure 8 is a flow diagram of one of the methods for resetting a memory cell array in accordance with a particular embodiment, incorporating an adjustment operation. Figures 9A and 9B are circuit diagrams of portions of a control circuit for providing a reverse bias reset condition of Figure 6 in accordance with an embodiment. 10A and 10B are circuit diagrams of a portion of a line control circuit for providing a reverse bias re-attack condition of FIG. 6 in accordance with an embodiment. 11A and 11B are circuit diagrams of portions of a control circuit for providing a reverse bias adjustment condition of FIG. 7 in accordance with an embodiment. Figure 12 is a circuit diagram of one portion of a row control circuit for providing a reverse bias voltage of 123008.doc 200830315 of Figure 7 in accordance with an embodiment. 13A and 13B illustrate exemplary bit line and word line reset voltage signals for generating an increased reverse bias during a reset operation in accordance with an embodiment. 14A and 14B are circuit diagrams of portions of a control circuit that can be used to generate a ramp pulse reset voltage signal as shown in Figures ha and 11B. 15A and 15B illustrate other exemplary bit line and word line reset voltages used to generate an increased reverse bias during a reset operation in accordance with an embodiment. Figures 16A and 16B are circuit level diagrams of portions of a control circuit that can be used to generate the ramp reset pulse signals as shown in Figures 9A and 9B. [Main Element Symbol Description] 100 Memory Unit/Passive Storage Element 102 Guide Element 104 State Change Element 106 Anti-Fuse 110 First Conductor/First Metal Conductive Layer 112 Second Conductor/Second Metal Conductive Layer 120 Memory Unit 122 Heavily doped n-type region 124 essential region 126 heavily doped p-type region 128 anti-fuse 140 memory cell 123008.doc • 42- 200830315 142 heavily doped n-type region 144 essential region 146 heavily doped ρ Type area 152 Memory unit 162 First bit line set 164 Word line 170 Memory unit 174 Bit line 176 Word line 178 Memory unit 180 Bit line 182 Memory unit 184 Word line 186 Memory unit 200 Integrated circuit 202 memory array 206 row control circuit 210 input/output 208 column control circuit 220 output 210 row control circuit 212 row decoder 214 array terminal receiver or driver 216 block selection circuit 220 column control circuit 222 column decoding Array 123008.doc -43- 200830315 224 Array Terminal Driver 226 Block Selection Circuit 250 Line / State 252 Line / State 254 Line / State 256 Line / State 258 Line / Target Level 402 Upper PMOS Device 404 Upper PMOS Device 406 Lower NMOS Device 408 Lower NMOS Device 412 Upper PMOS Device 414 Upper PMOS Device 416 NMOS Device 418 NMOS Device 422 Column Decoder 423 Column Decoder 430 Bus 506 Lower NMOS Device 512 Row Decoder 513 Unselected Column Decoder 702 Reference Voltage Generator 704 Charge Pump Controller 706 Charge Pump 123008.doc -44- 200830315

712 714 716 718 804 806 814 904 906 908 910 914 916 918 Counter Digit to Analog Converter / DAC Charge Pump Control Circuit Charge Pump Reset Voltage Pulse Word Line Voltage Pulse Reset Voltage Pulse Counter Digit to Analog Converter / DAC charge pump controller charge pump reference voltage generator charge pump controller charge pump

123008.doc -45-

Claims (1)

200830315 Patent Application: A method of operating non-volatile storage, comprising: applying _ _ bit quasi-money by a plurality of non-volatile storage elements, cutting the storage elements from a lower resistance state: resistance state And applying a second bit to the storage elements after switching the storage elements to reduce a subset of the subset of the storage elements having a resistance exceeding a level corresponding to the second resistance state . The method of claim 1, wherein the first level of reverse bias is higher than the third method of claim 2, wherein: the second level of reverse bias It is about 60% of the first level. Two-level reverse bias A one-order reverse bias 〇 4. According to the method of claim 1, wherein: The plus-first-level reverse bias includes applying a positive-voltage pulse to the -first bus line that is in communication with the storage elements and applying a second array line to one of the communication elements A negative voltage pulse; and applying a second level of reverse bias includes applying a positive voltage pulse to the first array line and applying a fixed bias voltage to the second array line. 5. The method of claim 1, wherein: each of the plurality of non-volatile storage elements comprises a resistivity change material; and the plurality of stores apply the reverse bias of the first level to increase 123008.doc 200830315 兀 = each of the resistivity of the storage element changes the resistivity of the material; adding the second level of reverse bias to reduce the use of 隹I storage element VII, the mother of the subset This resistivity changes the resistivity of the material. 6. The method of claim 5, wherein: the resistivity change material is polycrystalline germanium. 7. The method of claim 5, wherein: the resistivity change material is a metal oxide. 8. The method of claim 5, wherein: = each of the plurality of non-volatile storage members comprises: one of the elements in series with the resistivity changing material ^ H1 ^ ^ ^ guiding member, the resistivity changing material forming the guiding At least a part of a few pieces. 9. The method of claim 5, wherein: each of the components of the stimuli-storing component comprises an anti-fuse in series with the resistive material. 10. The method of claim 1, wherein: ???:: a plurality of non-volatile storage element systems - a three-dimensional single-rock memory array. 11. The method of claim 10, wherein: the first plurality of array lines and The second plurality of array lines of the plurality of array lines; the individual lines shared by at least two of the array lines and the second plurality of array lines. The lower resistance makeup can be set to one of the storage elements 123008.doc • 2 - 200830315; and the higher resistance state corresponds to the state. And one of the storage elements is reset. 13. The method of claim 12, wherein: the lower resistance state is a pinned state. One of the storage elements of the program. 14. The method of claim 13, wherein: The plurality of non-volatile a, such as the method of requesting deduction, includes two or more states. The non-volatile storage element is a multi-state storage element. The method of claim 12, wherein: the plurality of non-volatile storage elements form part of an array of subfield programmable memory; the lower resistance (4) for the storage elements - The method of claim 1, wherein: applying the reverse bias of the second level does not substantially change a resistance of the plurality of storage elements having a resistance within the target level. 18. A non-volatile memory system comprising: a plurality of non-volatile storage elements including a resistance change element; a control circuit in communication with the plurality of non-volatile storage elements, the control circuit being applied A first level of reverse biasing switches the storage elements from a lower resistance state to a higher resistance state to reset the plurality of non-volatile storage elements, the 123008 after switching the storage elements. Doc 200830315 The control circuit applies a reverse-biased reverse bias to the storage elements to reduce one of the storage elements having a resistance beyond a target level corresponding to the second electrical and disgusting Set one of the resistors. 19. The non-volatile memory system of claim 18, wherein: the reverse level of the first level is higher than the reverse of the second level. 20. The non-volatile memory system of claim 19, wherein: the younger one of the opposite reverse biases is about the same as the rabbit. 60% of this level. 21. The non-volatile memory system of claim 18, wherein the control circuit communicates with the memory element by applying a positive voltage pulse to the first array line in communication with the storage elements. The second array line applies a negative voltage pulse to apply a first level of reverse bias; and the control circuit applies a second level of reverse bias comprising applying a positive voltage pulse to the first array line The second array line applies a fixed φ bias. 22. The non-volatile memory system of claim 18, wherein: each of the plurality of non-volatile storage elements comprises a resistance* rate changing material; * applying the first level of reverse bias Increasing a resistivity of the resistivity changing material for each of the plurality of storage elements; applying the second level of reverse bias to reduce the each of the storage elements for the subset The resistivity changes the resistivity of one of the materials. 23. The non-volatile memory system of claim 22, wherein: 123008.doc 200830315 The resistivity change material is polycrystalline germanium. 24. The non-volatile memory system of claim 22, wherein the resistivity changing material is a metal oxide. 25. The non-volatile memory system of claim 22, wherein the component comprises a guiding element in series with each resistivity changing material of the plurality of non-volatile storage elements. At least a portion of the guiding element. 26. The non-volatile memory system of claim 22, wherein: each of the plurality of non-volatile storage elements comprises an anti-fuse in series with the resistivity change material. 27. The non-volatile memory system of claim 1, further comprising: a two-dimensional single stone read, body P train including the plurality of non-volatile storage elements. 28. The non-volatile memory system of claim 27, further comprising: a first plurality of array lines; and a second plurality of array lines substantially perpendicular to the first plurality of array lines; wherein the - at least one of the plurality of array lines and the second plurality of array lines - comprising individual lines shared between the memory levels of the three streams. 29. The non-volatile memory system of claim 18, wherein: the lower resistance state corresponds to setting a state for one of the health storage elements; and the higher resistance state corresponds to a weight for the (four) memory component Newly set 123008.doc 200830315 to determine the status. 3. The non-volatile memory system of claim 29, wherein the lower resistance state is a stylized state for one of the storage elements. 31. The non-volatile memory system of claim 30, wherein: the plurality of non-volatile storage elements are rewritable storage elements. 32. The non-volatile memory system of claim 30, wherein the plurality of non-volatile storage elements comprise more than two states. 33. The non-volatile memory system of claim 29, wherein: the plurality of non-volatile storage elements form part of an array of one field programmable memory; the lower resistance state is for the One of the storage elements is formatted. 34. The non-volatile memory system of claim 18, wherein the applying the second level of reverse bias does not substantially alter one of the plurality of storage elements having a resistance within the target level resistance. 3: The non-volatile memory system of claim 18, wherein the control circuit comprises at least one of a column control circuit and a row control circuit.