TWI455130B - Mixed-use memory array and method for use therewith - Google Patents

Description

Mixed use memory array and method of use thereof

The non-volatile memory array maintains its data even when the device is powered off. In a single-programmable memory array, each memory cell is formed to be in an initial unprogrammed state and can be converted to a programmed state. This change is permanent and these memory units are not erasable. In other types of memory, the memory unit is erasable and can be rewritten multiple times.

The memory unit can also be changed in a number of data states that can be achieved by each memory unit. A data state can be stored by changing a characteristic of the detectable memory cell, such as flowing through the memory cell under a predetermined applied voltage or a threshold voltage of a transistor in the memory cell Current. A data state is a distinct value of one of the memory cells, such as a data "0" or a data "1".

Some solutions for achieving erasable or multi-state memory cells are complex. For example, a floating gate and a SONOS memory cell operate by storing a charge, wherein the stored charge is present, absent, or the amount of charge changes by a transistor threshold voltage. These memory cells are three-terminal devices that are relatively difficult to manufacture and operate in very small sizes required for competitiveness in modern integrated circuits.

Other memory cells operate by changing the resistivity of relatively exotic materials such as chalcogen. In most semiconductor manufacturing facilities, sulfur is difficult to use and can be challenging.

A substantial advantage is provided by a non-volatile memory array having erasable or multi-state memory cells formed using conventional semiconductor materials in a structure that is easily scaled to a small size.

The present invention is defined by the following claims, and nothing in this paragraph should be construed as limiting the claim.

By way of introduction, the preferred embodiments described below provide a hybrid memory array and method of use thereof. In a preferred embodiment, a memory array is provided, comprising: a first set of memory cells operating as a single-programmed memory cell; and a second set of memory cells operating It is a rewritable memory unit. In another preferred embodiment, a memory array is provided, comprising: a first set of memory cells operating as a memory unit programmed with a forward bias; and a second set A memory unit that operates as a memory unit that is programmed with a reverse bias. Other specific embodiments are disclosed, and each specific embodiment can be utilized individually or in combination.

Preferred embodiments will now be described with reference to the drawings.

It is known that by applying an electrical pulse, the resistance of the resistor formed by the doped polysilicon can be trimmed to adjust between stable resistance states. These trimmable resistors have been used as components in an integrated circuit.

However, it is not customary to use a trimtable germanium resistor in a non-volatile memory cell to store the data state. There is a difficulty in fabricating a memory array of a polysilicon resistor. If a resistor is used as a memory cell in a large cross-point memory array, then when a voltage is applied to a selected memory cell, there will be a non-desired leak across the memory array. With non-selected memory cells. For example, referring to FIG. 1, it is assumed that a voltage is applied between the bit line B and the word line A to set, reset or sense the selected memory cell S. The current is intended to flow through the selected memory unit S. However, a leakage current may flow through the non-selected memory cells U1, U2, and U3 over an alternate path (for example, between bit line B and word line A). There are many such alternative paths that can exist.

By forming each memory cell as a two-terminal device including a diode, leakage current can be greatly reduced. The diode has a non-linear I-V (current-voltage) characteristic that allows a very small amount of current flow below the turn-on voltage and a higher current flow above the turn-on voltage. In general, diodes also act as check valves to make it easier to travel in one direction than in the other. Therefore, as long as the selected biasing scheme ensures that only the selected memory cell is subjected to a forward current higher than the turn-on voltage, the non-predetermined path can be greatly reduced (such as U1-U2-U3 of FIG. 1 is abnormal). Leakage current of the path).

"N0n volatile Memory Cell Without a Dielectric Antifuse Having High-and Low-Impedance States", U.S. Patent Application Serial No. 10/955,549, filed on Sep. 29, 2004, which is hereby incorporated by reference. Incorporating herein, a single-piece three-dimensional memory array is described in which the data state of a memory cell is stored in a resistivity state of a polycrystalline semiconductor material of a semiconductor junction diode. This memory unit is a single-programmed memory unit with two data states. The diode is formed to be in a high resistivity state; applying a stylized voltage permanently transforms the diode into a low resistivity state.

In a particular embodiment of the invention, three or four or more types of memory elements (such as the semiconductor diode of the '549 application) formed from the doped semiconductor material can be achieved by applying appropriate electrical pulses. Stable resistivity state. In other embodiments of the invention, the semiconductor material can be converted from an initial high resistivity state to a lower resistivity state; then, upon application of an appropriate electrical pulse, a higher resistivity state can be returned. The specific embodiments may be employed individually or in combination to form a memory unit that can have two or more data states and can be single-programmed or rewritable.

As mentioned, the inclusion of a diode between the conductors of the memory cell allows it to be formed in a high density cross-point memory array. In a preferred embodiment of the invention, the polycrystalline, amorphous or microcrystalline semiconductor memory component is then formed to be connected in series with the diode, or more preferably, to form the diode itself.

In this discussion, the transition from the higher resistivity state to the lower resistivity state will be referred to as the "set" transition, which is affected by the set current, set voltage, or set pulse; from the lower resistivity state to higher The inverse of the resistivity state will be referred to as the "reset" transition, which is affected by the reset current, reset voltage, or reset pulse.

In a preferred single-programmable embodiment, a polycrystalline semiconductor diode is paired with a dielectric rupture anti-fuse, however, in other embodiments, the anti-fuse may be omitted.

2 illustrates a memory cell formed in accordance with a preferred embodiment of the present invention. A bottom conductor 12 is formed of a conductive material (e.g., tungsten) and extends in a first direction. A barrier layer and an adhesive layer may be included in the bottom conductor 12. The polycrystalline semiconductor diode 2 has a bottom heavily doped n-type region 4; an intrinsic region 6, which is intended to be undoped; and a top heavily doped region 8, although the orientation of the diode can be reversed. Regardless of the orientation of this diode, it will be referred to as a p-i-n diode. In some embodiments, a dielectric rupture antifuse 14 is included. The top conductor 16 can be formed in the same manner and material as the bottom conductor 12 and extends in a second direction that is different from one of the first directions. The polycrystalline semiconductor diode 2 is vertically disposed between the bottom conductor 12 and the top conductor 16.

The polycrystalline semiconductor diode 2 is formed to be in a high resistivity state. The memory cell can be formed over a suitable substrate, for example, over a single crystalline germanium wafer. 3 illustrates a portion of a memory hierarchy in which such devices are formed in a cross-point memory array, wherein the diodes 2 are disposed between the bottom conductor 12 and the top conductor 16 (the antifuse 14 is omitted in this figure). . Multiple memory levels can be stacked on a substrate to form a high density monolithic three dimensional memory array.

In this discussion, a region of semiconductor material that is intended to be undoped is described as an essential region. However, those skilled in the art will appreciate that in practice, the intrinsic region may include a low concentration p-type or n-type dopant. The dopant may diffuse from the adjacent region into the intrinsic region, or may be present in the deposition chamber due to contamination from earlier deposition during deposition. It will be further appreciated that the deposited intrinsic semiconductor material, such as germanium, may include defects that cause it to be slightly n-doped. The use of the term "essential" to describe tantalum, niobium, tantalum alloy or some other semiconductor material is not intended to imply that the region does not contain any dopants, nor is it intended to imply that the region is fully electrically neutral.

The resistivity of the doped polycrystalline or microcrystalline semiconductor material (e.g., germanium) can be varied between steady states by applying appropriate electrical pulses. It has been found that in a preferred embodiment, it is advantageous to cooperate with the diode to perform a set transition under forward bias, while the mating diode is easier to achieve and control the reset transition under reverse bias. However, in some cases, the diode can be counter-biased to achieve a set transition, and the diode is forward biased to achieve a reset transition.

Semiconductor switching behavior is complex. For the diode, both the set transition and the reset transition have been achieved with the diode under forward bias. In general, the amplitude of the reset pulse applied by the diode under forward bias (which is sufficient to switch the polycrystalline semiconductor material constituting the diode from a predetermined resistivity state to a higher resistivity state) is low. The corresponding set pulse (which switches the same polycrystalline semiconductor material from the same resistivity state to a lower resistivity state) and has a longer pulse width.

Switching under reverse bias presents a different behavior. It is assumed that a polycrystalline p-i-n diode (such as the diode shown in Figure 2) is subjected to a relatively long switching pulse under reverse bias. After the switching pulse is applied, a smaller read pulse (eg, 2 volts) is applied, and the measurement flows through a current at the read voltage (referred to as a read current). As the voltage of the switching pulse under reverse bias increases in subsequent pulses, the subsequent read current changes by two volts, as shown in FIG. It will be understood that initially, as the current of the reverse voltage and the switching pulse increases, when a read voltage is applied after each switching pulse, the read current increases, that is, in the set direction, the semiconductor material (in this case) The initial transformation of the semiconductor material system is toward a lower resistivity. Once the switching pulse reaches a certain reverse bias voltage (K point in Figure 4, which is about -14.6 volts in this example), the read current suddenly begins to drop because of the reset and the 矽 resistivity increases. When the application of the reverse bias switching pulse is started, the switching voltage (at which the set trend is reversed and the turns of the diodes start to reset) depends on, for example, the resistivity state of the germanium constituting the diode. . Next, it will be understood that the setting or resetting of the semiconductor material constituting the diode can be achieved by the diode in the reverse bias by the appropriate voltage.

The distinct data state of the memory cell of the present invention corresponds to the resistivity state of the polycrystalline or microcrystalline semiconductor material constituting the diode by detecting the flow through the memory cell when a read voltage is applied (between The current between the top conductor 16 and the bottom conductor 12 is discriminated. Preferably, the current flowing between any of the distinct data states and any of the different data states is at least a factor of two to allow for differences between states to be easily detectable.

The memory unit can be used as a single-programmable memory unit or a rewritable memory unit, and can have two, three, four or more different data states. Under forward bias and reverse bias, the memory cells can be converted from any of their data states to any other data state in any order.

Several examples of preferred embodiments will be provided. However, it should be understood that their examples are not intended to be limiting. Those skilled in the art will appreciate that other methods for programming a two-terminal device, including a diode and a polycrystalline or microcrystalline semiconductor material, are within the scope of the present invention.

Single-programmed multi-bit memory unit

In a preferred embodiment of the invention, a diode formed of a polycrystalline semiconductor material and a dielectric rupture antifuse are arranged in series and disposed between the top and bottom conductors. A two-terminal device is used as a single-programmable multi-bit memory, which in the preferred embodiment has three or four data states.

Figure 2 illustrates a preferred memory unit. The diode 2 is preferably formed of a polycrystalline or microcrystalline semiconductor material, for example, tantalum, niobium, or an alloy of tantalum and/or niobium. More preferably, the diode 2 is a multi-layered germanium. In this example, the bottom heavily doped region 4 is n-type and the top heavily doped region 8 is p-type, however the polarity of the diode can be reversed. The memory unit includes a portion of the top conductor, a portion of the bottom conductor, and a diode disposed between the conductors.

When formed, the diode 2 of the polysilicon is in a high resistivity state, and the dielectric rupture antifuse 14 is intact. Figure 5 depicts a probability plot of the current of the memory cells in various states. Referring to FIG. 5, when a read voltage (for example, 2 volts) is applied between the top conductor 16 and the bottom conductor 12 (the mating diode 2 is under forward bias), the top conductor 16 and the bottom conductor 12 are interposed. The read current flowing between is preferably in the range of naamper, for example, less than about 5 nanoamperes. The area V on the graph of Fig. 5 corresponds to one of the first data states of the memory unit. For some memory cells in the memory array, this memory cell will not be pulsed or reset, and this state will be read as one of the data states of the memory cell. This first data state will be referred to as the V state.

A first electrical pulse is applied (preferably with the diode 2 under forward bias) between the top conductor 16 and the bottom conductor 12. This pulse is, for example, between about 8 volts and about 12 volts, for example, about 10 volts. The current system is, for example, between about 80 microamperes and about 200 microamperes. The pulse width is preferably between about 100 nanoseconds and about 500 nanoseconds. The first electrical pulse causes the dielectric rupture antifuse 14 to rupture and switches the semiconductor material of the diode 2 from a first resistivity state to a second resistivity state, the second resistivity state being lower than the first resistivity status. This second data state will be referred to as the P state, and this transition is labeled "V→P" in FIG. The current flowing between the top conductor 16 and the bottom conductor 12 at a 2 volt read voltage is about 10 microamperes or more. The resistivity of the semiconductor material constituting the diode 2 is reduced by a factor of from about 1,000 to about 2,000. In other embodiments, the change in resistivity is small, but will be at least 2 factor between any data state and any other data state, preferably at least a factor of 3 or 5, and more typically 100 or The above factors. Some of the memory cells in the memory array will be read with this data state and will not be pulsed or reset by additional settings. This second data state will be referred to as the P state.

A second electrical pulse is applied (preferably with the diode 2 under reverse bias) between the top conductor 16 and the bottom conductor 12. The pulse is, for example, between about -8 volts and about -14 volts, preferably between about -10 volts and about -12 volts, and more preferably about -11 volts. The current system is, for example, between about 80 microamperes and about 200 microamperes. The pulse width is, for example, between about 100 nanoseconds and about 10 microseconds, preferably between about 100 nanoseconds and about 1 microsecond, more preferably between about 200 nanoseconds and about 800 nanometers. Between seconds. The second electrical pulse causes the semiconductor material of the diode 2 to switch from a second resistivity state to a third resistivity state, the third resistivity state being higher than the second resistivity state. The current flowing between the top conductor 16 and the bottom conductor 12 at a 2 volt read voltage is between about 10 nanoamperes and about 500 nanoamperes, preferably between about 100 nanoamperes and about 500 nanoamperes. Some of the memory cells in the memory array will be read with this data state and will not be pulsed or reset by additional settings. This third data state will be referred to as the R state, and this transition is labeled "P→R" in FIG.

In order to reach the fourth data state, a third electrical pulse (preferably with the diode 2 under forward bias) is applied between the top conductor 16 and the bottom conductor 12. The pulse is, for example, between about 8 volts and about 12 volts (e.g., about 10 volts) and the current system is between about 5 microamperes and about 20 microamperes. The third electrical pulse causes the semiconductor material of the diode 2 to switch from the third resistivity state to a fourth resistivity state, the fourth resistivity state is lower than the third resistivity state, and the preferred resistivity is higher than the second resistivity Resistivity state. The current flowing between the top conductor 16 and the bottom conductor 12 at a 2 volt read voltage is between about 1.5 microamperes and about 4.5 microamperes. Some of the memory cells in the memory array will be read with this data state (which will be referred to as the S state), and this transition is labeled "R -> S" in Figure 5.

The difference in current between any two adjacent data states at a read voltage (e.g., 2 volts) is preferably a factor of at least two. For example, the read current of any memory cell in data state R is preferably at least twice the read current of any memory cell in data state V; the read current of any memory cell in data state S Preferably, at least twice the read current of any of the memory cells in the data state R; and the read current of any of the memory cells in the data state P is preferably at least twice as large as any of the memory cells in the data state S Read current. For example, the read current in the data state R can be twice the read current in the data state V; the read current in the data state S can be twice the read in the data state R The current; and the read current in the data state P can be twice the read current in the data state S. If the ranges are defined as being small, the difference may be quite large; for example, if the memory cell of the highest current V state can have a read current of 5 nanoamperes, and the memory cell of the lowest current R state can be With a read current of 100 nanoamperes, the current difference will be a factor of 20. By selecting other constraints, it is ensured that the difference in read current between adjacent memory states will be at least a factor of three.

This will be described below. A repetitive read-verify-write process can be applied to ensure that the memory cells are in one of the defined data states after a set pulse or reset pulse, and are not in between their data states.

So far, the difference between the highest current in a data state and the lowest current in the second highest adjacent data state has been discussed. The difference in read current of most memory cells in the adjacent data state is still large; for example, the memory cell in the V state can have a read current of 1 nanoamperes; the memory cell in the R state can be It has a read current of 100 nanoamperes; a memory cell in the S state can have a read current of 2 microamperes (2000 nanoamperes); and a memory cell in the P state can have a read current of 20 microamperes. The currents in each of their adjacent states may differ by a factor of 10 or more.

Memory cells having four distinct data states have been described. In order to assist in identifying the status of the data, it may be preferable to select three data states (rather than four data states). For example, a three-state memory unit can be formed to be in the data state V, set to the data state P, and then reset to the data state R. This memory unit does not have a fourth data state S. In this case, the difference between adjacent data states (eg, between R and P data states) may be significantly larger.

As programmed, a single stylized memory array having memory cells as described, each memory cell being programmed to one of three distinct data states (in a particular embodiment) Or one of four distinct data states (in an alternate embodiment). These are merely examples; obviously, there may be three or more identical resistivity states and corresponding data states.

However, in a memory array containing a single-programmable memory cell, the memory cells can be programmed in a variety of ways. For example, referring to FIG. 6, the memory unit of FIG. 2 can be formed to be in a first state (V state). A first electrical pulse (preferably under forward bias) ruptures the rupture antifuse 14 and switches the polysilicon of the diode from a first resistivity state to a second resistivity state (second resistance) The rate state is lower than the first resistivity state; the memory cell is in the P state, in this example, the P state is the lowest resistivity state. A second electrical pulse (preferably under reverse bias) switches the polysilicon of the diode from a second resistivity state to a third resistivity state (the third resistivity state is higher than the second resistivity state) , so that the memory unit is in the S state. A third electrical pulse (preferably under reverse bias) switches the polysilicon of the diode from a third resistivity state to a fourth resistivity state (fourth resistivity state) Above the third resistivity state), the memory cell is in the R state. For any given memory unit, any data state (V state, R state, S state, and P state) can be read as one of the data states of the memory cell. Each transition is labeled in Figure 6. The four different states are shown in the figure; there may be three or more states as needed.

In other embodiments, each successive electrical pulse can switch the semiconductor material of the diode to a successive lower resistivity state. As shown in FIG. 7, for example, the memory cell can progress from an initial V state to an R state, from an R state to an S state, and from a S state to a P state, for each state, the read current is at least The read current is twice the previous state, and each corresponds to a different data state. This scheme is more advantageous when the memory unit does not contain any antifuse. In this example, a pulse is applied under forward bias or reverse bias. In alternative embodiments, there may be three data states or more than four data states.

In a specific embodiment, the memory cell comprises a polysilicon or microcrystal diode 2 as shown in FIG. 8, the diode comprising a bottom heavily doped p-type region 4, an intermediate or lightly doped region 6 And the top heavily doped n-type region 8. As in the previous embodiment, the diode 2 can be arranged in series with a dielectric rupture antifuse and disposed between the top and bottom conductors. The bottom heavily doped p-type region 4 may be doped in situ, that is, by doping the dopant atoms by flowing a gas (such as boron) that supplies a p-type dopant during deposition of the germanium. Incorporate into the film that is formed.

Referring to Figure 9, it is found that the memory cell is formed to be in a V state where the current between the top conductor 16 and the bottom conductor 12 is less than about 80 nanoamperes at a 2 volt read voltage. A first electrical pulse (preferably applied under forward bias) ruptures the dielectric rupture antifuse 14 (if present) and switches the polysilicon of the diode 2 from a first resistivity state Up to a second resistivity state (the second resistivity state is lower than the first resistivity state); causing the memory cell to be in the data state P. In data state P, the current between top conductor 16 and bottom conductor 12 at the read voltage is between about 1 microamperes and about 4 microamperes. A second electrical pulse (preferably applied under reverse bias) switches the polysilicon of the diode 2 from a second resistivity state to a third resistivity state, the third resistivity state being lower than the first resistance Rate status. The third resistivity state corresponds to the data state M. In data state M, the current between top conductor 16 and bottom conductor 12 at the read voltage is about 10 microamperes. As in the previous embodiment, between any of the memory cells of the adjacent data state (between the highest current memory cell of the V state and the lowest current memory cell of the P state, or between the P states) The current difference between the highest current memory cell and the lowest current memory cell of the M state is preferably at least 2, preferably 3 or more. Any data status (V, P or M) can be detected as one of the data status of the memory unit.

Figure 4 shows that when the semiconductor diode is subjected to a reverse bias, in general, the semiconductor material initially undergoes a set transition to a lower resistivity, and then, as the voltage increases, the reset to a higher resistivity is experienced. change. For this particular diode, the top heavily doped n-type region 8 is used, and the bottom heavily doped region 4 formed by in-situ doping with a p-type dopant is preferably used, with an increase in the reverse direction. Switching from a set transition to a reset transition with a bias voltage does not occur suddenly or abruptly as with the diodes of other embodiments. This means that it is easier to control the set transition under reverse bias using this diode.

Rewritable memory unit

In a specific embodiment, the memory unit acts as a rewritable memory unit that can be repeatedly switched between two or three data states.

FIG. 10 illustrates a memory unit that can function as a rewritable memory unit. This memory cell is identical to the memory cell shown in Figure 2 except that it does not contain a dielectric rupture antifuse. Most rewritable embodiments do not include an antifuse in the memory unit, but may include an antifuse if desired.

Referring to FIG. 11, in the first preferred embodiment, the memory cell is formed to be in a high resistivity state V, and the current at 2 volts is about 5 nanoamperes or less. For most rewritable embodiments, the initial V state is not used as a data state for one of the memory cells. A first electrical pulse is applied (preferably with the diode 2 under forward bias) between the top conductor 16 and the bottom conductor 12. This pulse is, for example, between about 8 volts and about 12 volts, preferably about 10 volts. The first electrical pulse causes the semiconductor material of the diode 2 to switch from a first resistivity state to a second resistivity state, the second resistivity state being lower than the first resistivity state. In a preferred embodiment, the P state is also not used as a data state for one of the memory cells. In other embodiments, the P state will be used as a data state for one of the memory cells.

A second electrical pulse is applied (preferably with the diode 2 under reverse bias) between the top conductor 16 and the bottom conductor 12. The pulse is, for example, between about -8 volts and about -14 volts, preferably between about -9 volts and about -13 volts, more preferably about -10 volts or -11 volts. The required voltage will vary with the thickness of the intrinsic zone. The second electrical pulse causes the semiconductor material of the diode 2 to switch from the second resistivity state to a third resistivity state R, the third resistivity state being higher than the second resistivity state. In a preferred embodiment, the R state corresponds to a data state of one of the memory cells.

A third electrical pulse can be applied between the top conductor 16 and the bottom conductor 12, preferably under forward bias. The pulse is, for example, between about 5.5 volts and about 9 volts, preferably about 6.5 volts, and the current system is between about 10 microamperes and about 200 microamps, preferably about 50 microamps and about Between 100 microamperes. The third electrical pulse causes the semiconductor material of the diode 2 to switch from the third resistivity state R to a fourth resistivity state, and the fourth resistivity state is lower than the third resistivity state. In a preferred embodiment, the S state corresponds to a data state of one of the memory cells.

In this rewritable, two-state embodiment, the R state and the S state are sensed or read as a data state. The memory unit can be repeatedly switched between the two states. For example, a fourth electrical pulse (preferably with the diode 2 under reverse bias) switches the semiconductor material of the diode from the fourth resistivity state S to the fifth resistivity state R (which is substantially the same) At the third resistivity R). A fifth electrical pulse (preferably with the diode 2 under forward bias) switches the semiconductor material of the diode from a fifth resistivity state R to a sixth resistivity state S (which is substantially identical to the fourth Resistivity S), and so on. It may be more difficult to return the memory cells to the initial V state and the second P state; therefore, in a rewritable memory cell, their states may not be used as a data state. It may be preferable to perform a first electrical pulse (which causes the memory cell to switch from the initial V state to the P state) and the second power before the memory array reaches the user (for example, in a manufacturing plant or a test facility) Both pulses (which cause the memory cells to switch from the P state to the R state). In other embodiments, it may be preferred that only the first electrical pulse (which causes the memory cell to switch from the initial V state to the P state) is performed before the memory array reaches the user.

As shown in Figure 11, in the example provided, any memory cell in a data state is in a neighboring data state (in this case, the R data state (between about 10 Nai and 500 Nai) Reading voltage between the top conductor 16 and the bottom conductor 12 between any memory cells between the amps and the R data state (between about 1.5 microamps and 4.5 microamps) (eg, 2 The difference between the currents flowing under volts is at least a factor of three. Depending on the range selected for the state of the data, the difference may be a factor of 2, 3, 5 or more.

In an alternate embodiment, a rewritable memory unit can be switched between three or more data states in any order. The set transition or reset transition can be performed with the diode in forward bias or reverse bias.

In both the single programmable embodiment and the rewritable embodiment described, the data state is indicated to correspond to the resistivity state of the polycrystalline or microcrystalline semiconductor material comprising the diode. The data state does not correspond to the resistivity switching metal oxide or nitride resistivity state, as described in U.S. Patent Application Serial No. 11/395,995, filed on March 31, 2006. The description in the Resistance-Switching Material, which is owned by the assignee of the present application, is hereby incorporated by reference.

Reverse bias setting and reset

In the memory cell array formed and programmed according to the specific embodiments described so far, any step in which the memory cell is subjected to a large voltage in the reverse bias has reduced the leakage current compared to the reverse biasing step.

Referring to Figure 12, assume that 10 volts of forward bias is applied across the selected memory cell S. (The actual voltage to be used will depend on a number of factors, including the configuration of the memory cell, the amount of dopant, the height of the intrinsic zone, etc.; 10 volts is merely an example). Bit line B0 is set to 10 volts, and word line W0 is set to ground. In order to ensure that the half-selected memory cell F (which shares the bit line B0 with the selected memory cell S) maintains the turn-on voltage lower than the diode, the word line W1 is set to be lower than but relatively close to the bit line B0. Voltage; for example, word line W1 can be set to 9.3 volts such that 0.7 volts is applied across memory cell F (only one memory cell F is shown, but can have hundreds, thousands, or more). Similarly, in order to ensure that the half-selected memory cell H (which shares the word line W0 with the selected memory cell S) maintains the turn-on voltage lower than the diode, the bit line B1 is set higher than but relatively close to the word line W0. The voltage; for example, the bit line B1 can be set to 0.7 volts such that 0.7 volts is applied across the memory cell H (again, there can be thousands of memory cells H). The unselected memory unit U (which does not share the word line W0 and the common bit line B0 with the selected memory unit S) is subjected to -8.6 volts. Since there are millions of unselected memory cells U, significant leakage currents in the memory array result.

Figure 13 illustrates an advantageous biasing scheme for applying a large reverse bias across a memory cell (e.g., as a reset pulse). Bit line B0 is set to -5 volts, and word line W0 is set to 5 volts such that -10 volts is applied across selected memory cell S; the two-pole system is in reverse bias. In order to make the low-reverse bias of the half-selected memory cells F and H unintentionally set or reset, the word line W1 and the bit line B1 are set to ground, and the half-selected memory cells F and H are subjected to -5. Volt. In general, setting or resetting with a reverse bias appears to occur at or near the voltage at which the diode is converted to reverse breakdown (which is typically above -5 volts).

Using this scheme, there is no voltage across the unselected memory unit U, resulting in no reverse leakage. As a result, for example, the "Dual Data-Dependent Busses for Coupling Read/Write Circuits to a Memory Array" of the U.S. Patent Application Serial No. 11/461,352, which is incorporated herein by reference in its entirety in its entirety in Further description in "Agent File Number No. 023-0051" can significantly increase the bandwidth.

The biasing scheme of Figure 13 is merely an example; obviously, many other schemes can be used. For example, bit line B0 can be set to 0 volts, word line W0 can be set to -10 volts, and bit line B1 and word line W1 can be set to -5 volts. In the scheme of FIG. 13, the voltage across the selected memory cell S, the half selected memory cells H and F, and the unselected memory cell U will be the same. In another example, bit line B0 can be set to ground, word line W0 can be set to 10 volts, and bit line B1 and word line W1 can be set to 5 volts.

Repeated setting and resetting

So far, this discussion has described the application of an appropriate electrical pulse to switch the semiconductor material of the diode from a resistivity state to a different resistivity state, thereby switching the memory cell between two distinct data states. . In practice, their setting steps and resetting steps can be repeated processing.

As mentioned, the difference between the currents flowing during the reading in the adjacent data state is preferably a factor of at least 2; in many embodiments, it may be preferred to set each data state. The current range is separated by a factor of 3, 5, 10 or more.

Referring to FIG. 14, as described, the voltage is read at 2 volts, and the data state V can be defined as a read current of 5 nanoamperes or less. The data state R can be defined as about 10 nanoamperes and about 500 nanoamperes. The data state S can be defined as between about 1.5 microamperes and about 4.5 microamperes, and the data state P can be defined as greater than about 10 microamperes. Those skilled in the art should understand that they are merely examples. In another embodiment, for example, the data state V can be defined in a smaller range, wherein the voltage is read at 2 volts and the read current is 5 nanoamperes or less. The actual read current will vary with the characteristics of the memory cell, the configuration of the memory array, the selected read voltage, and many other factors.

It is assumed that the single-programmed memory cell is in the data state P. A reverse biased electrical pulse is applied to the memory cell to switch the memory cell to the data state S. However, in some cases, the read current may not be in the desired range after the application of the electrical pulse; that is, the resistivity state of the semiconductor material of the diode is above or below the desired state. For example, assume that after applying an electrical pulse, the read current of the memory cell is at the Q point shown on the graph, between the S state and the P state current range.

After an electrical pulse is applied to switch the memory cell to the desired data state, the memory cell can be read to determine if the desired data state is reached. If the desired data status is reached, an additional pulse is applied. For example, when current Q is sensed, an additional reset pulse is applied to increase the resistivity of the semiconductor material, reducing the read current into a range corresponding to the S data state. As described above, this set pulse can be applied under forward bias or reverse bias. The pulse width (voltage or current) of the extra pulse may be longer or shorter than the original pulse. After the additional set pulse, the memory cell is read again, and then the set pulse or reset pulse is applied as appropriate until the read current is in the desired range.

In a two-terminal device, such as a memory unit including the described diodes, this would be particularly advantageous for reading to verify settings or resets and adjustments if needed. Applying a large reverse bias across the diode can damage the diode; therefore, it is advantageous to minimize the reverse bias voltage when the mating diode is set or reset in reverse bias.

Manufacturing considerations

"Nonvolatile Memory Cell Operating by Increasing Order in Polycrystalline Semiconductor Material", U.S. Patent Application Serial No. 11/148,530, the entire disclosure of which is incorporated herein by No. 10/954, 510, "Memory Cell Comprising a Semiconductor Junction Diode Crystallized Adjacent to a Silicide" (all of which are owned by the assignee of the present invention and hereby incorporated herein by reference) The crystallization of the polycrystalline germanium affects the properties of the polycrystalline germanium. The lattice structure of certain metal halides, such as cobalt telluride and titanium telluride, is very close to the lattice structure of germanium. When the amorphous or microcrystalline germanium is crystallized to contact one of the tellurides, the lattice structure of the telluride provides a stencil during the crystallization. The resulting polycrystalline germanium will be highly ordered and the defects will be quite low. When doped with a conductivity enhancing dopant, the high quality polycrystalline germanium is relatively highly conductive when formed.

In contrast, when an amorphous or microcrystalline material is crystallized to be in contact with a crucible having a crystal lattice that is well matched to germanium, for example, only in contact with, for example, cerium oxide. With titanium nitride (the crystal lattice of cerium oxide and titanium nitride is significantly mismatched to yttrium), the resulting eutectic lanthanum will have many more defects, and the doped polycrystalline crystallization crystallized in this way It will be very low in conductivity when formed.

In the aspect of the invention, the semiconductor material forming the diode is switched between two or more resistivity states, and the current flowing through the diode is changed at a predetermined read voltage, and different currents (with resistivity) Status) corresponds to the status of the different data. It has been found that a diode formed by a highly defective germanium (or other suitable semiconductor material such as tantalum or niobium-niobium alloy) that has not been crystallized adjacent to a telluride or a similar material that provides a crystallized template exhibits a greater Favorable switching behavior.

Without wishing to be bound by any particular theory, it is believed that one possible mechanism to support the observed change in resistivity is that a set pulse above the threshold amplitude causes the dopant atoms to move out of the grain boundary (where the dopant atoms are not Active) enters the crystal body (where dopant atoms will increase conductivity and reduce the resistance of the semiconductor material). In contrast, resetting the pulse can cause the dopant atoms to move back to the grain boundaries, reducing conductivity and increasing resistance. However, there may be other mechanisms that operate or are substituted, such as increasing or decreasing the degree of sequencing of the polycrystalline material.

It has been found that the resistivity state of the crystallized very low defect tantalum adjacent to the appropriate telluride is not as easy to switch as when the semiconductor material has a higher degree of defects. The presence of defects or the presence of a large number of grain boundaries may allow for easier switching. In a preferred embodiment, then the polycrystalline or microcrystalline material forming the diode is not crystallized adjacent to the material with which it has a small lattice mismatch. The small lattice mismatch system (for example) has a lattice mismatch of about 3 percent or less.

Evidence has suggested that switching behavior can focus on changes in the essential area. Switching behavior has been observed in resistors and p-i-n diodes and is not limited to p-i-n diodes, but the use of p-i-n diodes may be particularly advantageous. Specific embodiments described so far include p-i-n diodes. However, in other embodiments, the diodes may alternatively be p-n diodes and have negligible or no intrinsic regions.

Detailed examples describing the fabrication of preferred embodiments of the invention will be provided. U.S. Patent Application Serial No. 10/320,470, entitled "An Improved Method for Making High Density Nonvolatile Memory", filed on Dec. 19, 2002, which is incorporated herein by reference. Manufacturing details will help to form the diodes of their specific embodiments with information from the '549 application. No. 11/015,824, "Nonvolatile Memory Cell Comprising a Reduced Height Vertical Diode", which is owned by the assignee of the present invention and is hereby incorporated by reference. Incorporate this article) to derive useful information. In order to avoid obscuring the present invention, all details from the applications are not included, but it should be understood that it is not intended to exclude information from their applications.

example

A single memory level will be fabricated in detail. Additional memory levels can be stacked, each formed in a monolithic manner above the memory level below it. In this embodiment, the polycrystalline semiconductor diode will be used as a switchable memory element.

Referring to FIG. 15a, the formation of the memory begins at the substrate 100. The substrate 100 can be any semi-conductive substrate well known in the art, such as a single crystalline germanium, an IV-IV compound (such as a ruthenium-iridium or osmium-rhenium-carbon), a III-V compound, a II-VII compound, An epitaxial layer or any other semiconductive material on the substrate. The substrate may include an integrated circuit fabricated therein.

An insulating layer 102 is formed on the substrate 100. The insulating layer 102 can be a tantalum oxide, tantalum nitride, high dielectric film, Si-C-O-H film, or any other suitable insulating material.

A first conductor 200 is formed over the substrate and the insulator. An adhesive layer 104 may be included between the insulating layer 102 and the conductive layer 106 to assist in the adhesion of the conductive layer 106 to the insulating layer 102. If the upper conductive layer is tungsten, titanium nitride is preferred as the adhesive layer 104.

The layer to be deposited next is the conductive layer 106. Conductive layer 106 can comprise any conductive layer material well known in the art, such as tungsten or other materials, including tantalum, titanium, copper, cobalt, or any alloy thereof.

Once all of the layers that will form the conductor tracks have been deposited, any suitable masking and etching process will be used to pattern and etch the layers to form substantially parallel, substantially coplanar conductors 200, as shown in the cross-sectional view of Figure 15a. Show. In a specific embodiment, the photoresist is deposited and patterned by lithography and their etched layers, and then the photoresist is removed using standard process techniques. The conductor 200 can alternatively be formed by a damascene method.

Next, a dielectric material 108 is deposited over and between the conductor tracks 200. Dielectric material 108 can be any known electrically insulating material such as hafnium oxide, tantalum nitride, and/or hafnium oxynitride. In a preferred embodiment, germanium dioxide can be used as the dielectric material 108.

Finally, excess dielectric material 108 on the topmost portion of conductor track 200 is removed, exposing the topmost portion of conductor track 200 separated by dielectric material 108, and leaving a substantially planar surface 109. Figure 15a depicts the resulting structure. Excessive dielectric removal is performed by any process well known in the art, such as chemical mechanical polishing (CMP) or etch back to form a planar surface 109. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; in. At this stage, a plurality of substantially parallel first conductors have been formed on the substrate 100 at a first height.

Next, referring to Figure 15b, a vertical column will be formed over the completed conductor track 200. (To save space, the substrate 100 is not shown in Figure 15b; the substrate will be identified). Preferably, a barrier layer 110 is deposited as the first layer following the planarization of the conductor tracks. Any suitable material can be used in the barrier layer, including tungsten nitride, tantalum nitride, titanium nitride, or a combination of these materials. In a preferred embodiment, titanium nitride is used as the barrier layer. If the barrier layer is titanium nitride, the barrier layer can be deposited in the same manner as described above for depositing the adhesion layer.

Next, a semiconductor material that will be patterned into a pillar is deposited. The semiconductor material can be a tantalum, niobium, tantalum-niobium alloy or other suitable semiconductor or semiconductor alloy. For the sake of brevity, this sub-directive refers to semiconductor materials as germanium, but those skilled in the art will appreciate that any other suitable materials may be selected as an alternative.

In a preferred embodiment, the post comprises a semiconductor junction diode. The term "junction diode" is used herein to refer to a device having a non-ohmic conduction property, having a two-terminal electrode, and being made of a semiconductor material having a p-type at one electrode and an n-type at the other electrode. Semiconductor device. Examples include p-n diodes and n-p diodes (having a contact p-type semiconductor material and an n-type semiconductor material such as a Zener diode) and a p-i-n diode (wherein The undoped semiconductor material is interposed between the p-type semiconductor material and the n-type semiconductor material.

The bottom heavily doped region 112 can be formed by any deposition doping method well known in the art. The germanium may be deposited and subsequently doped, but is preferably doped in situ by flowing a donor gas that provides n-type dopant atoms (eg, phosphorus) during deposition of germanium. The thickness of heavily doped region 112 is preferably between about 100 angstroms and about 800 angstroms.

The intrinsic layer 114 can be formed by any method known in the art. Layer 114 can be a tantalum, niobium or any alloy of niobium or tantalum and has a thickness between about 1100 angstroms and about 3300 angstroms, preferably about 2,000 angstroms.

Referring again to FIG. 15b, the just deposited semiconductor layers 114 and 112 will be patterned and etched along with the underlying barrier layer 110 to form the pillars 300. The post 300 should have a pitch and width that are about the same as the conductors 200 below, such that each post 300 is formed at the very top of the conductor 200. Some misplacements can be tolerated.

The post 300 can be formed using a suitable masking and etching process. For example, a photoresist can be deposited, patterned using standard lithography techniques, and etched, followed by removal of the photoresist. Alternatively, a hard mask of some other material (e.g., hafnium oxide) can be formed on the topmost of the stack of semiconductor layers (with a bottom anti-reflective coating (BARC) on top), followed by patterning and etching. Likewise, a dielectric anti-reflective coating (DARC) can be used as the hard mask.

U.S. Patent Application Serial No. 10/728,436, filed on Jan. 5, 2003, to the entire entire entire entire entire entire entire entire entire entire entire entire entire entire The lithography technique described in "Photomask Features with Chromeless Nonprinting Phase Shifting Window", which is owned by the assignee of the present invention and which is hereby incorporated by reference herein, Any lithographic step used in the memory array of the present invention.

A dielectric material 108 is deposited over and between the semiconductor pillars 300 to fill the gaps between the pillars. Dielectric material 108 can be any known electrically insulating material such as hafnium oxide, tantalum nitride, and/or hafnium oxynitride. In a preferred embodiment, cerium oxide is used as the insulating material.

Next, the dielectric material on the very top of the pillar 300 is removed, exposing the topmost portion of the pillar 300 separated by the dielectric material 108, and leaving a substantially flat surface. Excessive dielectric removal is performed by any process well known in the art, such as CMP or etch back. After CMP or etch back, ion implantation is performed to form a top heavily doped p-type region 116. The p-type dopant is preferably boron or BCl ₃ . This implantation step completes the formation of the diode 111. Figure 15b shows the resulting structure. In the diode just formed, the bottom heavily doped region 112 is n-type and the top heavily doped region 116 is p-type; obviously, the polarity can be reversed.

Referring to Figure 15c, next, a dielectric rupture antifuse layer 118 is formed on top of each heavily doped p-type region 116. The antifuse 118 is preferably a layer of ruthenium dioxide formed by oxidizing underlying iridium in rapid thermal annealing (e.g., about 600 degrees). The thickness of the antifuse 118 can be about 20 angstroms. Alternatively, an antifuse 118 can be deposited.

The top conductor 400 can be formed in the same manner as the bottom conductor 200, for example, by depositing an adhesive layer 120 (preferably made of titanium nitride) and a conductive layer 122 (preferably made of tungsten). Next, the conductive layer 122 and the adhesion layer 120 are patterned and etched using any suitable masking and etching process to form a substantially parallel, substantially coplanar conductor 400, as shown by the left to right spread of FIG. 15c. In a preferred embodiment, the photoresist is deposited and patterned by lithography and their etched layers, and then the photoresist is removed using standard process techniques.

Next, a dielectric material (not shown) is deposited over and between the conductor tracks 400. The dielectric material can be any known electrically insulating material such as hafnium oxide, tantalum nitride and/or hafnium oxynitride. In a preferred embodiment, cerium oxide can be used as the dielectric material.

It has been described to form a first memory level. Additional memory levels can be formed at this first memory level to form a single piece of three dimensional memory array. In some embodiments, the conductors can be shared between memory levels; that is, the top conductor 400 will serve as the bottom conductor of the next memory level. In other embodiments, an inter-layer dielectric (not shown) is formed over the first memory level of FIG. 15c, the surface of which is planarized, and the construction of a second memory level begins here. The layers are dielectrically and have no shared conductors.

A monolithic three dimensional memory array is a memory array in which multiple memory levels are formed over a single substrate, such as a wafer, and without an interposer. The layers forming a memory level are deposited or grown directly over an existing layer or layers of multiple levels. In contrast, stacked memory is constructed by forming memory levels on separate substrates and bonding their memory levels to each other, as in "Three dimensional structure memory" by Leedy, U.S. Patent No. 5,915,167. Presented in the article. The substrates may be thinned or removed from the memory levels prior to bonding, but when initially forming their memory layers on separate substrates, the memories are not true monolithic three dimensional memory arrays.

The monolithic three-dimensional memory array formed over the substrate includes at least a first memory level (which is formed at a higher level than the first height of the substrate) and a first memory level (which is different from the first height) The second height is formed). In this multi-level memory array, three, four, eight or even any number of memory levels can be formed over the substrate.

An alternative method for forming a similar memory array is described in US Patent Application Serial No. 11/444,936, entitled "Conductive Hard Mask to Protect Patterned Features During Trench Etch", which is incorporated by reference. The tessellation is used to form a conductor, which is owned by the assignee of the present invention and is hereby incorporated by reference. The method of Radigan et al. can alternatively be used to form a memory array in accordance with the present invention.

Alternative embodiment

In addition to the specific embodiments that have been described, many alternative embodiments of a memory cell that stores its data state in the resistivity state of a polycrystalline or microcrystalline semiconductor material are also within the scope of the present invention. A few other possible specific embodiments will be mentioned, but this list is not intended to be exhaustive.

FIG. 16 illustrates the switchable memory element 117 formed in series with the diode 111. Switchable memory element 117 is formed from a semiconductor material that is switched between resistive states using electrical pulses as described. As noted above, the diodes are preferably crystallized adjacent to the telluride (such as cobalt telluride, which provides a crystallization template) such that the semiconductor material defects of the diode are extremely low and exhibit negligible or no switching behavior. Preferably, the switchable memory device 117 is doped and should be doped to the same conductivity type as the top heavily doped region 116. The manufacturing method of this device is described in the '167 application.

Detailed manufacturing methods have been described herein, but any other method of forming the same structure may be used, with the results falling within the scope of the present invention.

Exemplary application

The foregoing specific embodiments describe how memory cells can be used as two data state memory cells, two or more data state memory cells, a single stylized memory cell, or a rewritable memory cell. This versatility allows the use of a common memory cell architecture to provide multiple types of memory products. The versatile nature of memory cells and their potential to provide a versatile memory array are discussed below.

The memory cell described above has a memory component that includes a switchable resistive material, such as a semiconductor material configurable to one of at least three resistivity states. The memory element can be "configured" to a resistivity state (eg, the initial, unprogrammed state of the memory element has an initial resistivity state) during formation of the memory element, or by subsequent memory element processing Set the pulse or reset pulse to "configure" the memory component to a resistivity state. Because of this feature, a single memory cell can operate in two different ways: as a single-programmable memory cell or a rewritable memory cell. Moreover, because of this characteristic, a single memory unit can use two data states or two or more data states. Accordingly, any predetermined memory cell has the potential to operate as a single-programmed memory cell or a rewritable memory cell having two or more data states.

As shown and as described above, when the memory cell operates as a single-programmable memory cell, a resistivity state is used to represent a data state of the memory cell; however, when the memory cell operates as a heavy When writing a memory cell, the resistivity state is not used to indicate a data state of the memory cell. In other words, when a memory cell is used as a single-programmable memory cell, there may be an "extra" state in the memory cell. For example, with respect to the memory unit described above and described in conjunction with FIGS. 5 and 11, the memory cell is fabricated to be in an initial resistivity state (V state), and when the memory cell operates as a single program This initial resistivity state is used when the memory cell is used; however, when the memory cell operates as a rewritable memory cell, this initial resistivity state is not used. When the memory unit operates as a rewritable memory unit, two other data states (R state and S state) are used to represent the data state of the memory cell. (As described below, they can also be used in a single-programmed memory unit). The state of the data is achieved by changing the resistance of the switchable resistive material. Again, their other data states do not include data states that are used to indicate the status of the data only when the memory unit operates as a single-programmable memory unit. Additional data states (eg, an "R2" state between the R state and the S state) may be used to allow the rewritable memory cells to achieve three or more than three different data states.

It should be noted that in a preferred embodiment, the memory component includes a switched resistive material (e.g., a semiconductor material) connected in series with the antifuse, and the V state is only a single stylized operation of the memory cell. The resistivity state used when the memory cell is used. The reason is that once the antifuse is blown, the memory component cannot return to the V state. However, even when no antifuse is used, a resistivity state can be designated as a state that is used only when the memory cell operates as a single stylized memory cell. It should also be noted that the P state can also be a resistivity state that is used when the memory cell operates as a single-programmable memory cell but is not used when the memory cell operates as a rewritable memory cell. However, in some embodiments, instead of or in addition to the P state, one or both of the R state and the S state are used to represent a data state of the single-programmable memory cell, such as when When the sub-programmed memory unit stores three or four data states. In this case, the single-program and rewritable uses of the memory cells will have a resistivity state in common. For example, instead of a single-programmed memory unit and a rewritable memory unit having a unique state state (eg, V-state and P-state are used for a single-programmed memory unit, and R-state and S The state is for a rewritable memory unit), and the single-programmed memory unit and the rewritable memory unit can have a state together (for example, there is no difference between the S state and the P state). However, when the memory unit operates as a single-programmable memory unit, at least one resistivity state (eg, V-state) will still be used to represent a data state of the memory cell; however, when the memory cell operates as This is not the case when overwriting the memory unit.

An advantage of this versatility is that a single integrated circuit having such memory cells can be designated as a single-programmable memory array or as a rewritable memory array. This provides manufacturing flexibility and yield improvement. To determine if a memory array is being used as a single-programmable memory array or as a rewritable memory array, a set of test memory cells in the memory array can be tested during (or after) manufacturing. For example, test memory cells can be utilized by repeating stylization, resetting, and setting up their test memory cells. A suitable test technique is described in U.S. Patent No. 6,407,953, the disclosure of which is incorporated herein by reference. Based on the test results, it is predicted whether the memory array will be properly programmed to act as a rewritable memory array. For example, if the test exhibits an indistinguishable R-state and S-state (these states are used when the memory array operates as a rewritable memory array), then the component will most likely not be properly programmed to be Overwrite the memory array. However, because the memory cells in the memory array can operate as a single-programmable memory array or as a rewritable memory array, instead of being discarded because the component does not provide the expected rewritable results, it can be specified This part acts as a single-programmable memory array. Accordingly, the common backbone memory cell architecture provides manufacturing flexibility and yield improvement.

At this point, there may be manufacturing differences. The tested memory array can continue to be further formatted (eg, program all memory cells from the V state to the P state, then apply between the R state and the S state as a final qualification test), and then Shipped to a warehouse or user as a rewritable memory array (eg, a memory card for a digital camera). Untested memory arrays can be packaged and sent to different parts of the manufacturer to stylize single-programmed content. Alternatively, the component can be sent to a warehouse where the warehouse staff or user can program the content in a single program (for example, using kiosk). Unprogrammed parts can also be sold to users for use as archive memory.

Preferably, a flag is used to send a signal to a device for reading and writing to the memory array (for example, a controller on a memory device including a memory array or a hardware/software in the host device). The memory array is told to be a single-programmed memory array or a rewritable memory array. A "flag" may be one or more bits stored in a memory array. For example, a flag can be set in a particular address location (eg, address 0000) in the memory array. When the host device detects the flag, it can adapt to the single-programmable nature of the memory array by not attempting to reprogram the memory array.

Instead of using the entire memory array as a single-programmable memory array or as a rewritable memory array, the memory array can be a "multi-purpose" memory array. In this embodiment, since all of the single memory cells in the memory array can be used as a single-programmable memory cell or as a rewritable memory cell, a first group of memory cells can operate as A single stylized memory unit, and a second set of memory units operate as rewritable memory units. In this manner, the memory cells and the rewritable memory cells can be programmed once on the same integrated circuit. As described above, a test can be performed to determine if a given set of memory cells should be designated as a single-programmable memory cell or a rewritable memory cell.

17 is a diagram of a hybrid memory array 200 of a preferred embodiment. A first set of memory cells 210 operates as a single-programmable memory cell, and a second set of memory cells 220 operates as a rewritable memory cell. In this embodiment, the memory cells in the two sets 210, 220 all contain the same number of memory cell data states, but the number of memory cell data states is feasible, as described below. In a specific embodiment, the first set of memory cells stores data that is considered permanent and can be related to the operation of the memory array. Examples of this information include, but are not limited to, one or more of the following items: content management bits, trim bits, manufacturer data, and formatted material.

"Content Management Bits" refer to information related to the management of stylized content. "Trimming Bits" are custom information that sets various options in the circuit on the wafer. In operation, the on-wafer circuit reads the trim bits in the first set of memory cells 210 and the read trim bit control circuitry further operates. For example, the trim bit can include a setting of a preferred write/read value (current or voltage) for the write/read circuit of the memory device. "Manufacturer Information" may include the manufacturer's name and serial number. "Formatted data" indicates a bad portion of the memory array; specifically, one of the particular columns and/or rows of memory arrays and redundant columns and/or row locations. For further information on redundancy, please refer to U.S. Patent Application Serial Nos. 10/402,385, issued to the assignee of . Of course, their information is merely an example, and other forms of information may be stored in the single-programmable memory unit 210. For example, the first set of memory units 210 can include game content material (ie, the computer code of the game), and the second set of memory units 220 can include game state data (ie, when the user requests to save the game, An indication of the location of the user in the game). Furthermore, the data in the first set of memory cells 210 or the second set of memory cells 220 can be programmed at the manufacturing facility or by subsequent users.

In Fig. 17, there is only one segment of a single-programmed memory cell and only one segment of a rewritable memory cell. In another embodiment, at least one additional set of memory cells operates as a single-programmable memory cell or a rewritable memory cell. Figure 18 illustrates this embodiment in which two singularly stylized sections 230, 250 are interleaved with two rewritable sections 240, 260 (i.e., two adjacent sets of memory cells are not available) Single stylized or both are rewritable). Any data can be stored in any section as described above. For example, the game content material can be stored in the singular stylized sections 230, 250, and the game state data can be stored in the rewritable sections 240, 260.

It should be noted that while Figures 17 and 18 illustrate the orientation of the sets of memory cells in a horizontal manner, in an alternative embodiment, one or more sets of memory cells can be oriented in a vertical manner. For example, instead of having formatted data in a horizontal column of memory cells (as shown in Figure 17), the formatted material can be tied to a vertical column of memory cells. In this way, redundant data will span many pages. Mixed horizontal orientation and vertical orientation information can also be used. For example, manufacturing materials can be oriented horizontally, while formatted materials can be oriented vertically.

As shown in FIG. 18, each page of material may include one or more flag bits 270 that indicate whether a page is single-programmable or rewritable. In Fig. 18, the "1" flag indicates that it can be single-stylized, and the "0" flag indicates that it is rewritable. Preferably, the flag is stored in a single-programmable memory unit (even if the memory unit is in a rewritable section). Furthermore, a preferred method is to optimize the preset read conditions for the single-programmed data (so that the single-programizable flag bits stored in the single-programizable section can be successfully read and Trim the bits, manufacturing materials, etc., and if the flag indicates rewritable material, modify their reading conditions. One advantage of using flag bits is that it is virtually impossible to use a single-programmed memory cell as a rewritable memory cell, and vice versa, because the on-wafer write circuit interprets the flag. The write-once circuit on the wafer is programmed to prevent more than one write to the memory cell if the flag bit indicates that a memory cell is single-programmable.

As an alternative to using flag bits, address space calculations and write control can be moved out of the chip, for example, to hardware/software in the host device. For example, if a memory device is used as the game device, the software in the host device can use a pre-specified address space for storing game state data (the host device knows the address space, but the memory is not known. Address space). Alternatively, another monolithic portion of the memory array (eg, a special address location in the memory array (eg, address 0000) may be stored in the game content data stored in the memory array. )) or information in the device controller in the memory device that is separate from the memory array to inform the host device of the address space for the game state data.

In the specific embodiment shown in FIGS. 17 and 18, the memory array is "mixed" in the sense that some memory cells can be single-programmed memory cells and others are rewritable memory cells. ". In other embodiments, the "hybrid" memory array includes other "hybrid" features instead of or in addition to the single-programmable/rewritable features. As described above, flag bits or other mechanisms can be used to determine the properties of a given set of memory cells. For example, a first set of memory cells in the same memory array can be more reliable than a second set of memory cells and have a wider temperature and voltage range.

As another example, using the preferred memory cell structure described above, a given memory cell can be: (i) programmed with forward bias (eg, the same single-programmed memory) Unit or rewritable memory unit); or (ii) stylized with reverse bias (eg, as the same rewritable memory unit, but different from the two-state single-programmed memory unit). In other words, a single-programmed memory cell can only accept forward bias programming, while a rewritable memory cell can accept both forward bias programming and reverse bias programming. This is shown in the circuit diagrams of FIGS. 19 and 20. For a detailed description of forward bias writes, see U.S. Patent No. 6,618,295; and for a detailed description of reverse bias writes, see U.S. Patent Application Serial No. 11/461,339 (Attorney Docket No. 023-0048) entitled "Passive Element Memory Array Incorporating Reversible Polarity Word Line and Bit Line Decoders" and U.S. Patent Application Serial No. 11/461,364 (Attorney Docket No. 023-0054) entitled "Method for Using a Passive Element Memory Array Incorporating Reversible Polarity Word Line and Bit Line Decoders, each of which has been assigned to the assignee of the present application, is hereby incorporated by reference. Accordingly, a "hybrid" memory array can include: a first set of memory cells that are programmed with forward bias; and a second set of memory cells that are stylized with reverse bias. . A memory cell that is programmed with a reverse bias can also be erased with a forward bias. In an erase operation (as compared to a write operation), individual data bits in a page are not variables because all bits are erased during the erase operation. For a detailed description of the erasing operation, please refer to U.S. Patent Application Serial No. 11/461,339 (Attorney Docket No. 023-0048) entitled "Passive Element Memory Array Incorporating Reversible Polarity Word Line and Bit Line Decoders" and the United States. Patent Application No. 11/461,364 (Attorney Docket No. 023-0054) entitled "Method for Using a Passive Element Memory Array Incorporating Reversible Polarity Word Line and Bit Line Decoders", all of which have been assigned to this The assignee of the invention is hereby incorporated by reference.

The discussion so far has been on the use of memory cells as a single-programmable memory cell or as a rewritable memory cell, and the memory array has a single-programmable memory cell and a rewritable memory cell. mixing. However, as described above, another preferred embodiment of the memory unit is that the memory unit (whether a single-programmed memory unit or a rewritable memory unit) can store two types of data. Status or two or more data states. Multiple test memory cells can be tested for each possible data state to determine how much data state can be stored in a memory array. For example, the test memory cells can be tested in the V, P, S, and R data states to infer whether the memory cells are desirably functioning as a four-state, single-programmable memory cell. If the memory array fails the test, it can be used as a two-state memory array in which the appropriate flags are stored.

A hybrid memory array can be used in conjunction with a set of memory cells using X resistivity states to represent X data states, and used in conjunction with a second set of memory cells using Y resistivity states to represent Y species Data status, where X≠Y. In this manner, the number of data states stored in a memory cell in the memory array can vary between groups of memory cells. The various versatile and mixed versatility described above can be combined. For example, the first set of memory cells and the second set of memory cells in the memory array can use different numbers of data states, and both can be single-programmed, both can be rewritten, or Can be a single stylized and rewritable mix. In other words, portions of the memory array can be any combination of a single-programmed memory unit and a rewritable memory unit, with one portion storing X data states (eg, two data states) and another portion storing Y The status of the data (for example, two or more data states). For example, the memory array can have: a first set of memory cells that can be single-programmed and have more than two data states (eg, for stylized data); and a second set of memory cells It is rewritable and has more than two data states (for example, for use as a scratch pad memory). There can be more than two parts.

As described above, the choice of how many data states to use in any group of memory cells can be determined by testing. For example, if the read circuit cannot distinguish the V, P, and R states, the four-state single-programmed memory cell fails the test. The memory array portion containing their test memory cells can then be used as a two-state rewritable portion. In this case, the write circuit can be verified using a repetitive write stylization (as described above) and then re-programmed again to "push" the R state to the V state and "push" the S state to the P state. In other words, the repeated feedback mechanism "opens" the "space" between the R state and the S state.

Multi-purpose memory arrays with different data states: In fact, although each memory cell has the potential to store more than two data states, the most efficient use of memory cells in a memory array occurs in a memory array. When all memory units are stored in more than two states. For example, in a preferred embodiment, a first set of memory cells is a single-programmable memory cell and a second set of memory cells is a rewritable memory cell. Figure 21 illustrates this particular embodiment. In this particular embodiment, the optimal circuit configuration settings for reading the four state memory cells are stored in the two state memory cells. For example, as shown in FIG. 21, the configuration bit in page 0 indicates a page that is read with respect to each memory cell four-state read circuit operation with a two-state read circuit operation per memory cell. . The configuration bits also determine the limits of the available bits in the two state pages of each memory cell. When page 0 is written, the portion of the wafer for the two-state data and the four-state data is configured. For the single-programmable memory unit usage, page 0 can be written several times to include additional configuration bits indicating the extra portion for the two-state data because the configuration bits are set to logic" 1', so all pages except page 0 are read as four-state data (ie, the default configuration reads only page 0 as two-state data). Native single-programmed memory The unit status (V status) is logic "1". The default configuration and interpretation of the configuration bits is performed by logic coding on the memory chip. The number of columns is not necessarily equal to the number of pages, but is better. Simple multiples (for example, four pages to one column).

Of course, other configurations are possible. For example, another application may have a third portion of the two-state data as per memory unit, which is based on the manufacturing test indicating the next best memory cell in the third portion of the memory array. In still another application, the memory array has a single-programmable memory unit in the first portion and two or more state-of-the-art rewritable memory units (eg, using R, S, and R1 states). The optimal circuit configuration is preferably stored in a two-state, single-programmable memory unit. Additionally, the memory array can have two state rewritable memory cells in the first portion and two or more state rewritable memory cells in the second portion.

Referring again to the drawings, FIG. 22 is a diagram showing a memory array of a preferred embodiment in which a portion of each state of the memory cell and each memory cell are indicated by a flag bit on each physical page. Part of the four states. The flag bit is preferably two state data per memory unit. An even number of pages are associated with each column. A flag bit for an odd page read as "1" indicates that the page is not available. Unusable pages are also stored in control logic or software outside of the memory chip and can be reassigned by known redundant/bad block mechanisms. Alternatively, each column of shared flag bits can be used, where the flag is associated with multiple pages and indicates the number of states per memory cell for that column and the unavailability of several pages. Preferably, an even number of pages per column is used. For several adjacent columns, the block used for the bad block table is preferably defined as one-half of the column.

23 is a diagram of a preferred embodiment of a memory array in which portions of each state of each memory cell and portions of four states of each memory cell are indicated by a translation table stored in the memory array. The translation table has a correspondence between a logical page address and an entity column in the memory array. The translation table also contains flag bits for the number of bits stored in a physical column. Optionally, the translation table also has a flag indicating that certain pages are single-programmable or rewritable. The flag bit preferably controls the read and write circuits for the optimal settings for the type of data indicated.

24 is a diagram showing a memory array of a preferred embodiment, wherein the two-state single-programmed portion of each memory unit, each memory unit, is indicated by a flag bit on each physical page. The state rewritable portion and the four states per memory unit can be a single stylized portion. In this particular embodiment, the flag bit is stored as two state data per memory unit. An even number of pages are associated with each column. The off-chip controller scans the flag information to create a bad block table. A flag bit for some pages indicates that the page is not available. The flag bit also preferably controls the on-wafer read and write circuitry to provide optimal configuration for both stateful operation of each memory cell and rewritable versus single-programmable operation. In this case, the flag bit indicated in FIG. 24 includes at least one bit for indicating the number of states per memory unit and a bit for indicating that it can be single-programmed or rewritable. In some embodiments, more than two bits can be used.

Figure 25 depicts a flow diagram of a preferred embodiment of the use of wafer flags and off-chip bad block mechanisms. A logical page address is provided (step 300). A bad block table in the controller chip of the memory device and the translation logic determine a preliminary physical address associated with the logical page address (step 310). Next, the flag bit located at the preliminary physical address is read with a preset of two states per memory unit (step 320). If the page is not available, a feedback mechanism is used to update the write status for the unavailable page (step 330), which causes the controller wafer to update the bad block table. Otherwise, the read or write circuit is set to two state modes or two or more state modes (step 340). The page material is then read or written (step 350).

Although any suitable memory unit can be used with their specific embodiments, it is presently preferred that the memory unit includes a passive memory element (which includes a switchable resistive material, preferably a semiconductor), in particular, Compound crystal dipole. Other switchable resistive materials include, but are not limited to, binary metal oxides, phase change materials (as shown in U.S. Patent No. 5,751,012 and U.S. Patent No. 4,646,266), and organic material resistors, for example. In other words, a memory cell comprising a plurality of layers of organic material includes at least one layer having conductivity-like conductivity and at least one organic material that applies an electric field to change conductivity. An array of organic passive components is described in U.S. Patent No. 6,055,180. Another varistor material is an amorphous ruthenium doped with V, Co, Ni, Pd, Fe or Mn, as described more fully in U.S. Patent No. 5,541,869. Another class of materials is taught in U.S. Patent No. 6,473,332. These materials are perovskite materials such as Pr _1-X Ca _X MnO ₃ (PCMO), La _1-X Ca _X MnO ₃ (LCMO), LaSrMnO ₃ (LSMO) or GdBaCo _X O _Y (GBCO). Another option for this varistor material is a carbon polymer film comprising, for example, carbon black particles or graphite mixed in a plastic polymer, as taught in U.S. Patent No. 6,072,716. Another switchable resistive material is taught in U.S. Patent Application Serial No. 09/943, 190, and U.S. Patent Application Serial No. 09/941,544. This material is a chalcogenide glass of the doped molecular formula A _X B _Y , wherein A contains at least one of the following elements of the periodic table: Group IIIA (B, Al, Ga, In, Ti), Group IVA (C, Si) , Ge, Sn, Pb), Group VA (N, P, As, Sb, Bi) or Group VIIA (F, Cl, Br, I, At); wherein the B is selected from the group consisting of S, Se and Te and mixture. The dopant is selected from the group consisting of noble metals and transition metals, including Ag, Au, Pt, Cu, Cd, Ir, Ru, Co, Cr, Mn or Ni. The chalcogenide glass (amorphous chalcogenide, not crystalline) is preferably formed in a memory cell adjacent to the moving metal ion reservoir. Some other solid electrolyte material may be substituted for the chalcogenide glass.

In a preferred embodiment, the component comprises an antifuse in series with a semiconductor material. In another preferred embodiment, the memory component comprises an antifuse, a binary metal oxide, and a polysilicon germanium isolation device. In addition, although the memory unit can be a component of the two-dimensional memory array, it is preferable that the memory unit is a component of a single-chip three-dimensional memory array, wherein the memory unit is arranged in a plurality of layers of memory, each A memory level is formed over a single substrate and without any interposer.

It is presently preferred that the memory component be non-volatile. However, in an alternate embodiment, the memory component can be volatile in the state of the data used when the memory component operates as a rewritable memory cell. For example, the memory component may allow the V state and the P state to be permanent, but may allow the R state and the S state to slowly fade. With this memory component, the R state and the S state will be refreshed over time.

The foregoing detailed description describes only a few of the many forms in which the invention may be employed. For the sake of this reason, the detailed description is intended to be illustrative, and not to limit the invention. Only the following claims (including all equivalents) are intended to define the scope of the invention.

2. . . Polycrystalline semiconductor diode

4. . . Bottom heavily doped n-type region (Figure 2)

4. . . Bottom heavily doped p-type region (Figure 8)

6. . . Essential area

8. . . Top heavily doped area (Figure 2)

8. . . Top heavily doped n-type zone (Figure 8)

12. . . Bottom conductor

14. . . Dielectric rupture antifuse

16. . . Top conductor

100. . . Substrate

102. . . Insulation

104. . . Adhesive layer

106. . . Conductive layer

108. . . Dielectric material

109. . . Flat surface

110. . . Barrier layer

111. . . Dipole

112. . . Bottom heavily doped region

114. . . Essential layer

116. . . Top heavily doped p-type region

117. . . Switchable memory component

118. . . Dielectric rupture antifuse layer

120. . . Adhesive layer

122. . . Conductive layer

200. . . Conductor (first conductor; conductor rail; bottom conductor) (Fig. 15a to 15c)

200. . . Memory array (Figure 17)

210. . . First set of memory cells

220. . . Second set of memory cells

230,250. . . Single stylized section

240,260. . . Rewritable section

270. . . Flag bit

300. . . column

400. . . Conductor (conductor rail; top conductor)

A, A0, A1. . . Word line

B, B0, B1. . . Bit line

F, H. . . Semi-selected memory unit

U. . . Non-selected memory unit

M, P, R, S, V. . . Data status of the memory unit

U1, U2, U3. . . Non-selected memory unit

Figure 1 illustrates a circuit diagram required for electrical isolation between memory cells in a memory array.

2 is a cross-sectional view of a multi-state or rewritable memory cell formed in accordance with a preferred embodiment of the present invention.

3 is a cross-sectional view showing a portion of a memory level including the memory cell shown in FIG. 2.

4 is a graph showing changes in the read current of the memory cell of the present invention as the reverse bias voltage across the diode increases.

FIG. 5 illustrates a probability plot of a memory cell transitioning from a V state to a P state, from a P state to an R state, and from a R state to an S state.

6 illustrates a probability plot of a memory cell transitioning from a V state to a P state, from a P state to an S state, and from a S state to an R state.

FIG. 7 illustrates a probability plot of a memory cell transitioning from a V state to an R state, from an R state to an S state, and from a S state to a P state.

Figure 8 is a cross-sectional view of a vertically oriented p-i-n diode that can be used in a particular embodiment of the invention.

FIG. 9 illustrates a probability plot of a memory cell transitioning from a V state to a P state and from a P state to an M state.

10 is a cross-sectional view of a multi-state or rewritable memory cell formed in accordance with a preferred embodiment of the present invention.

FIG. 11 illustrates a probability plot of a memory cell transitioning from a V state to a P state, from a P state to an R state, and from an R state to an S state, and then repeatable between an S state and an R state.

Figure 12 is a circuit diagram showing a biasing scheme for biasing the S memory cell with a forward bias.

Figure 13 is a circuit diagram showing a biasing scheme for biasing the S memory cell with a reverse bias.

Figure 14 illustrates a repetitive read-verify-write cycle to move the memory cells into the data state.

15a through 15c are cross-sectional views showing stages in the formation of a memory level formed in accordance with an embodiment of the present invention.

Figure 16 is a cross-sectional view of a diode and a resistive switching element that can be used in an alternate embodiment of the present invention.

17 is a diagram showing a preferred embodiment of a mixed-use memory array in which a first set of memory cells operate as a single-programmable memory cell, and a second set of memory cells operate as a rewritable Memory unit.

18 is a diagram of a preferred embodiment of a mixed-use memory array in which a plurality of sets of single-programmable memory cells and rewritable memory cells are interleaved.

19 is a diagram of a circuit of a preferred embodiment showing a group of memory cells programmed with forward bias.

20 is a diagram of a circuit of a preferred embodiment showing the programming of a set of memory cells with reverse bias.

21 is a diagram of a memory array of a preferred embodiment, wherein a first portion of the memory array stores two data states per memory cell and one of the memory arrays stores a first portion of each memory cell. Data status.

22 is a diagram of a preferred embodiment of a memory array in which portions of each state of each memory cell and portions of four states of each memory cell are indicated by flag bits on each physical page.

23 is a diagram of a preferred embodiment of a memory array in which portions of each state of each memory cell and portions of four states of each memory cell are indicated by a translation table stored in the memory array.

24 is a diagram showing a memory array of a preferred embodiment, wherein the two-state single-programmed portion of each memory unit, each memory unit, is indicated by a flag bit on each physical page. The state rewritable portion and the four states per memory unit can be a single stylized portion.

Figure 25 depicts a flow diagram of a preferred embodiment of the use of wafer flags and off-chip bad block mechanisms.

2. . . Polycrystalline semiconductor diode

4. . . Bottom heavily doped n-type region

6. . . Essential area

8. . . Top heavily doped area

12. . . Bottom conductor

14. . . Dielectric rupture antifuse

16. . . Top conductor

Claims (23)

A memory array includes: a plurality of memory cells operable to be a single-programmed memory cell or a rewritable memory cell, each memory cell including a memory component, the memory The component includes a semiconductor material configurable to one of at least three resistivity states, wherein when the memory cell operates as a single-programmable memory cell, a first resistivity state is used to represent the memory a data state of the body unit; but when the memory unit operates as a rewritable memory unit, the first resistivity state is not used to represent a data state of the memory unit; wherein the plurality of memory cells The method includes: a first set of memory cells operating as a single-programmed memory cell; and a second set of memory cells operating as rewritable memory cells, wherein the plurality of memory cells are A plurality of pages are organized, and each of the pages includes: a first flag bit indicating whether the page is single-programmable or rewritable; and a second flag bit, Information indicating the number of states of each memory cell. The memory array of claim 1, wherein the first group of memory cells stores one or more of the following items: a content management bit, a trim bit, a manufacturer profile, or a formatted material. The memory array of claim 1, wherein the first group of memory cells is used for stylized data, wherein the second group of memory cells is used for Information. The memory array of claim 1, wherein the first group of memory cells uses X resistivity states to represent X respective data states, wherein the second group of memory cells uses Y resistivity states to represent Y species Data status, and where X=Y. The memory array of claim 1, wherein the first group of memory cells uses X resistivity states to represent X respective data states, wherein the second group of memory cells uses Y resistivity states to represent Y species Data status, and where X≠Y. The memory array of claim 5, wherein X is 3 or more, and Y is 2. The memory array of claim 5, wherein X is 3 or more, and Y is 3 or more. The memory array of claim 1, wherein the plurality of memory cells comprise at least one of the following: an additional set of memory cells operating as a single-programmed memory cell; or an additional set of memory a unit that operates as a rewritable memory unit, wherein the first group of memory cells, the second group of memory cells, and the additional group of memory cells are interleaved such that two adjacent sets of memory cells are not both It can be single-programmed or both can be rewritten. The memory array of claim 1, wherein the first and second flag bits are stored as a single-programmable material. The memory array of claim 1, wherein the memory component comprises an antifuse connected in series to the semiconductor material. The memory array of claim 10, wherein the semiconductor material comprises a complex Crystal germanium diode. The memory array of claim 1, wherein the memory component comprises an antifuse, a binary metal oxide, and a polysilicon germanium isolation device. The memory array of claim 1, wherein the memory array comprises a single-chip three-dimensional memory array, wherein the plurality of memory cells are arranged in a plurality of memory levels, each memory level being formed in a single Above the substrate and without any interposer. The memory array of claim 1, wherein the single-programmed memory unit can only accept forward bias programming, and wherein the rewritable memory unit can accept forward bias programming and reverse bias programming Both. A method of using a memory array, the method comprising: (a) providing a memory array, the memory array comprising a plurality of memory cells, each memory cell operable as a single-programmed memory cell Or a rewritable memory unit and comprising a memory component comprising a semiconductor material configurable to one of at least three resistivity states, wherein the memory cell operates as a single time When staging the memory cell, a first resistivity state is used to indicate a data state of the memory cell; but when the memory cell operates as a rewritable memory cell, the first resistivity state is not used. Representing a data state of the memory cell; (b) using a first set of memory cells as a single-programmable memory cell; and (c) using a second set of memory cells as rewritable memory unit, Wherein the plurality of memory cells are organized in a plurality of pages, and the method further comprises: staging a first flag bit in each of the pages, indicating whether a predetermined page is Sub-stylized or rewritable; and stylized a second flag bit indicating the number of data states per memory unit. The method of claim 15, further comprising before (b) and (c): testing a set of test memory cells in the memory array; predicting that the first set of memory cells in the memory array will be incorrect Stylized as a rewritable memory unit; and predicting that the second set of memory cells in the memory array will be properly programmed as a rewritable memory unit. The method of claim 15, further comprising: stabilizing one or more of the following items in the first set of memory units: a content management bit, a trim bit, a manufacturer profile, or a formatted material. The method of claim 15, wherein the first and second flag bits are stored as a single-programmable material. The method of claim 15, further comprising: determining, by a controller, a address space of the first set of memory cells and the second set of memory cells in a memory device including the memory array. The method of claim 15, further comprising: using a host in communication with a memory device including the memory array The device determines an address space of the first group of memory cells and the second group of memory cells. The method of claim 15, further comprising: using an additional group of memory cells operating as a single-programmable memory cell, or an additional group of memory cells operating as a rewritable memory cell, wherein two adjacent Group memory cells are not both stylized or both rewritable. The method of claim 15, wherein the memory array comprises a single-chip three-dimensional memory array, wherein the plurality of memory cells are arranged in a plurality of memory levels, each memory level being formed over a single substrate And without any interposer. The method of claim 15, wherein the single-programmed memory unit can only accept forward bias programming, and wherein the rewritable memory unit can accept both forward bias programming and reverse bias programming. .