WO2008016419A2 - Réseau de mémoires polyvalent et procédé d'utilisation correspondant - Google Patents

Réseau de mémoires polyvalent et procédé d'utilisation correspondant Download PDF

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Publication number
WO2008016419A2
WO2008016419A2 PCT/US2007/013769 US2007013769W WO2008016419A2 WO 2008016419 A2 WO2008016419 A2 WO 2008016419A2 US 2007013769 W US2007013769 W US 2007013769W WO 2008016419 A2 WO2008016419 A2 WO 2008016419A2
Authority
WO
WIPO (PCT)
Prior art keywords
memory
memory cells
state
array
data
Prior art date
Application number
PCT/US2007/013769
Other languages
English (en)
Other versions
WO2008016419A3 (fr
Inventor
Roy E. Scheuerlein
Original Assignee
Sandisk 3D Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/496,983 external-priority patent/US7450414B2/en
Priority claimed from US11/496,874 external-priority patent/US20080023790A1/en
Application filed by Sandisk 3D Llc filed Critical Sandisk 3D Llc
Publication of WO2008016419A2 publication Critical patent/WO2008016419A2/fr
Publication of WO2008016419A3 publication Critical patent/WO2008016419A3/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5641—Multilevel memory having cells with different number of storage levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/33—Material including silicon

Definitions

  • a substantial advantage would be provided by a nonvolatile memory array having erasable or multi-state memory cells formed using conventional semiconductor materials in structures that are readily scaled to small size.
  • Fig. 4 is a graph showing change in read current for a memory cell of the present invention as voltage in reverse bias across the diode increases.
  • Fig. 19 is an illustration of a circuit of a preferred embodiment showing a set of memory cells that are programmed with forward bias.
  • Fig. 20 is an illustration of a circuit of a preferred embodiment showing a set of memory cells that are programmed with reverse bias.
  • FIG. 23 is an illustration of a memory array of a preferred embodiment in which two-state-per-cell portions and four-state-per-cell portions are indicated by a translation table stored in the memory array.
  • a polycrystalline semiconductor diode is paired with a dielectric rupture antifuse, though in other embodiments the antifuse may be omitted.
  • a third electrical pulse preferably also under reverse bias, switches the polysilicon of the diode from the third resistivity state to a fourth resistivity state, the third resistivity state higher resistivity than the second, placing the memory cell in the R state.
  • any of the data states, the V state, the R state, the S state, and the P state can be read as a data state of the memory cell.
  • Each transition is labeled in Fig. 6. Four distinct states are shown; there could be three or more than four states as desired.
  • a memory cell includes the polysilicon or microcrystalline diode 2 shown in Fig. 8, including bottom heavily doped p-type region 4, middle intrinsic or lightly doped region 6, and top heavily doped n-type region 8.
  • this diode 2 can be arranged in series with a dielectric rupture antifuse, the two disposed between top and bottom conductors.
  • Bottom heavily doped p- type region 4 may be in situ doped, i.e. doped by flowing a gas that provides a p-type dopant such as boron during deposition of the polysilicon, such that dopant atoms are incorporated into the film as it forms.
  • a substrate 100 can be any semiconducting substrate as known in the art, such as monocrystalline silicon, IV-IV compounds like silicon-germanium or silicon-germanium- carbon, III-V compounds, II- VII compounds, epitaxial layers over such substrates, or any other semiconducting material.
  • the substrate may include integrated circuits fabricated therein.
  • Top conductors 400 can be formed in the same manner as bottom conductors 200, for example by depositing adhesion layer 120, preferably of titanium nitride, and conductive layer 122, preferably of tungsten. Conductive layer 122 and adhesion layer 120 are then patterned and etched using any suitable masking and etching technique to form substantially parallel, substantially coplanar conductors 400, shown in Fig. 15c extending left-to-right across the page. In a preferred embodiment, photoresist is deposited, patterned by photolithography and the layers etched, and then the photoresist removed using standard process techniques.
  • Fig. 16 shows a switchable memory element 117 formed in series with a diode 111.
  • the switchable memory element 117 is formed of semiconductor material which is switched between resistivity states using electrical pulses as described.
  • the diode is preferably crystallized adjacent to a suicide such as cobalt suicide, which provides a crystallization template, as described earlier, such that the semiconductor material of the diode is very low-defect and exhibits little or no switching behavior.
  • Switchable memory element 117 is preferably doped, and should be doped to the same conductivity type as top heavily doped region 116. Methods to fabricate this device are described in the '167 application.
  • the above embodiments describe how a single memory cell can be used as a two-data-state memory cell, a more-than-two-data-state memory cell, a one-time programmable memory cell, or a rewritable memory cell.
  • This versatility allows a common memory cell architecture to be used to provide multiple types of memory products. The following is a discussion of the multi-use nature of the memory cell and its potential to provide a mixed-use memory array.
  • the memory cell is manufactured in an initial resistivity state (the V state), and this resistivity state is used when the memory cell operates as a one-time programmable memory cell but not when the memory cell operates as a rewritable memory cell.
  • Two other data states are used to represent data states of the memory cell when the memory cell operates as a rewritable memory cell. (As described below, these data states can also be used in a one-time programmable memory cell.) These data states are achieved by varying the resistance of the switchable resistance material. Again, these other data states do not include the data state that is only used to represent a data state when the memory cell operates as a one-time programmable memory cell. Additional data state(s) (e.g., an "R2" data state between the R state and the S state) can be used to allow a rewritable memory cell to achieve three or more respective data states.
  • the memory array can be a "mixed-use" memory array. Since every single memory cell in the array can act either as a one-time programmable memory cell or as a rewritable memory cell, in this embodiment, a first set of memory cells operates as one-time programmable memory cells and a second, different set of memory cells operates as rewritable memory cells. In this way, one-time programmable memory cells and rewritable memory cells can be provided on the same integrated circuit. As above, testing can be performed to determine whether a given set of memory cells should be designated as one-time programmable memory cells or rewritable memory cells.
  • the discussion so far has related to the use of a memory cell as either onetime programmable or rewritable and memory arrays having a mixture of one-time programmable and rewritable memory cells.
  • the memory cell (whether one-time programmable or rewritable) can store two data states or more than two data states.
  • Multiple test memory cells can be tested for each possible data state to determine how many data states can be stored in a memory array. For example, test memory cells can be tested at the V, P, S, and R data states to project whether the memory cell operates acceptably as a four-state one-time programmable memory array. If the test fails, the memory array can be used as a two-state memory array, with the appropriate flag being stored in the memory array.
  • a mixed-use array of different data states recognizes the fact that, although each memory cell has the potential of storing more than two data states, the most efficient use of memory cells in a memory array may occur when not all the memory cells in the memory array store more than two states.
  • a first set of memory cells are used as two-state one-time programmable memory cells, and a second set of memory cells are used as four-state one-time programmable memory cells.
  • Fig. 21 In this embodiment, optimum circuit configuration settings for reading the four-state memory cells are stored in the two-state memory cells. For example, as shown in Fig.
  • variable resistance material is amorphous silicon doped with V, Co, Ni, Pd, Fe or Mn, for example as described more fully in U.S. Patent No. 5,541,869.
  • Another class of material is taught by U.S. Patent No. 6,473,332.
  • perovskite materials such as Pri. ⁇ Ca ⁇ Mn ⁇ 3 (PCMO), La ! . ⁇ Ca ⁇ Mn ⁇ 3 (LCMO), LaSrMnO 3 (LSMO), or GdBaCo x Oy (GBCO).
  • PCMO Perovskite materials
  • LCMO La ! . ⁇ Ca ⁇ Mn ⁇ 3
  • LSMO LaSrMnO 3
  • GBCO GdBaCo x Oy
  • Another option for this variable-resistance material is a carbon-polymer film comprising carbon black particulates or graphite, for example, mixed into a plastic polymer, as taught in U.S. Patent No. 6,072,716.
  • This chalcogenide glass (amorphous chalcogenide, not in as crystalline state) is preferably formed in a memory cell adjacent to a reservoir of mobile metal ions. Some other solid electrolyte material could substitute for chalcogenide glass.
  • the element comprises an antifuse in series with the semiconductor material.
  • the memory element comprises an antifuse, a binary metal oxide, and a polysilicon diode isolation device.
  • the memory cells can be part of a two-dimensional array, it is preferred that the memory cells be part of a monolithic three-dimensional memory array, with the memory cells arranged in a plurality of memory levels, each formed above a single substrate with no intervening substrates.

Abstract

La présente invention concerne un réseau de mémoires polyvalent et un procédé d'utilisation correspondant. Dans un mode de réalisation préféré, on utilise un réseau de mémoires comprenant un premier ensemble de cellules mémoire fonctionnant comme des cellules mémoire programmables une seule fois et un deuxième ensemble de cellules mémoire fonctionnant comme des cellules mémoire réinscriptibles. Dans un autre mode de réalisation préféré, on utilise un réseau de mémoires comprenant un premier ensemble de cellules mémoire fonctionnant comme des cellules mémoire qui sont programmées avec une polarisation directe et un deuxième ensemble de cellules mémoire fonctionnant comme des cellules mémoire qui sont programmées avec une polarisation inverse.
PCT/US2007/013769 2006-07-31 2007-06-12 Réseau de mémoires polyvalent et procédé d'utilisation correspondant WO2008016419A2 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/496,983 US7450414B2 (en) 2006-07-31 2006-07-31 Method for using a mixed-use memory array
US11/496,983 2006-07-31
US11/496,874 US20080023790A1 (en) 2006-07-31 2006-07-31 Mixed-use memory array
US11/496,874 2006-07-31

Publications (2)

Publication Number Publication Date
WO2008016419A2 true WO2008016419A2 (fr) 2008-02-07
WO2008016419A3 WO2008016419A3 (fr) 2008-05-22

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TW (1) TWI455130B (fr)
WO (1) WO2008016419A2 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0788113A1 (fr) * 1996-01-31 1997-08-06 STMicroelectronics S.r.l. Circuits de mémoire multi-niveau et méthodes de lecture et d'écriture correspondants
US6483734B1 (en) * 2001-11-26 2002-11-19 Hewlett Packard Company Memory device having memory cells capable of four states
WO2005066969A1 (fr) * 2003-12-26 2005-07-21 Matsushita Electric Industrial Co., Ltd. Dispositif memoire, circuit memoire et circuit integre semi-conducteur a resistance variable

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6034882A (en) * 1998-11-16 2000-03-07 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
US7003619B1 (en) * 2001-04-09 2006-02-21 Matrix Semiconductor, Inc. Memory device and method for storing and reading a file system structure in a write-once memory array
US6768661B2 (en) * 2002-06-27 2004-07-27 Matrix Semiconductor, Inc. Multiple-mode memory and method for forming same
JP3875153B2 (ja) * 2002-07-04 2007-01-31 Ｎｅｃエレクトロニクス株式会社 不揮発性半導体記憶装置およびその書き換え禁止制御方法
EP1450261A1 (fr) * 2003-02-18 2004-08-25 STMicroelectronics S.r.l. Mémoire semiconductrice avec mécanisme de protection d'accès
JP4282529B2 (ja) * 2004-04-07 2009-06-24 株式会社東芝 半導体集積回路装置及びそのプログラム方法
US7398348B2 (en) * 2004-08-24 2008-07-08 Sandisk 3D Llc Method and apparatus for using a one-time or few-time programmable memory with a host device designed for erasable/rewritable memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0788113A1 (fr) * 1996-01-31 1997-08-06 STMicroelectronics S.r.l. Circuits de mémoire multi-niveau et méthodes de lecture et d'écriture correspondants
US6483734B1 (en) * 2001-11-26 2002-11-19 Hewlett Packard Company Memory device having memory cells capable of four states
WO2005066969A1 (fr) * 2003-12-26 2005-07-21 Matsushita Electric Industrial Co., Ltd. Dispositif memoire, circuit memoire et circuit integre semi-conducteur a resistance variable

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
BANDYOPADHYAY A ET AL: "Vertical p-i-n Polysilicon Diode With Antifuse for Stackable Field-Programmable ROM" IEEE ELECTRON DEVICE LETTERS, IEEE SERVICE CENTER, NEW YORK, NY, US, vol. 25, no. 5, May 2004 (2004-05), pages 271-273, XP011112176 ISSN: 0741-3106 *

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TW200811865A (en) 2008-03-01
WO2008016419A3 (fr) 2008-05-22
TWI455130B (zh) 2014-10-01

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