WO2008013341A1 - Alignment of semiconducting nanowires on metal electrodes - Google Patents

Alignment of semiconducting nanowires on metal electrodes Download PDF

Info

Publication number
WO2008013341A1
WO2008013341A1 PCT/KR2006/005054 KR2006005054W WO2008013341A1 WO 2008013341 A1 WO2008013341 A1 WO 2008013341A1 KR 2006005054 W KR2006005054 W KR 2006005054W WO 2008013341 A1 WO2008013341 A1 WO 2008013341A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal electrode
set forth
nanowire
nanowires
semiconducting nanowires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2006/005054
Other languages
French (fr)
Inventor
Kyung Soo Park
Seok Joon Kwon
Jae Gwan Park
Jae Hwan Park
Young Jin Choi
Hae Yong Kang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Korea Institute of Science and Technology KIST
Original Assignee
Korea Institute of Science and Technology KIST
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Korea Institute of Science and Technology KIST filed Critical Korea Institute of Science and Technology KIST
Priority to DE112006003964T priority Critical patent/DE112006003964T5/en
Priority to US12/374,750 priority patent/US20090317943A1/en
Publication of WO2008013341A1 publication Critical patent/WO2008013341A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82B—NANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
    • B82B3/00—Manufacture or treatment of nanostructures by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y15/00—Nanotechnology for interacting, sensing or actuating, e.g. quantum dots as markers in protein assays or molecular motors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/122—Nanowire, nanosheet or nanotube semiconductor bodies oriented at angles to substrates, e.g. perpendicular to substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • H10P14/271—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition
    • H10P14/274—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition using seed materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • H10P14/279—Vapour-liquid-solid growth
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2923—Materials being conductive materials, e.g. metallic silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3424—Deposited materials, e.g. layers characterised by the chemical composition being Group IIB-VIA materials
    • H10P14/3426—Oxides
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures

Definitions

  • the present invention relates to a method for aligning semiconducting nanowires on a metal electrode, more particularly to a method for aligning semiconducting nanowires on a metal electrode by which a zinc oxide nanowire and a silicon nanowire are synthesized on a specific region of an electrode made of Al, Ti, Pt, etc. and the nanowires are aligned on the wafer scale instantly as they are synthesized.
  • the nanowires are made of GaAs, GaN, InP, ZnO, etc. and researches are actively carried out on their use such as a light-emitting device.
  • GaN, GaAs, ZnO, etc. are used to develop blue light-emitting devices.
  • InAs and InP are utilized in the region of 1.3 to 1.5 mm.
  • the nanowires can be utilized in a variety of electronic devices, optoelectronic devices, sensors, etc.
  • ZnO zinc oxide
  • One-dimensional nanoscale objects with a variety of forms have been synthesized by carbothermal reduction method, chemical vapor deposition (CVD), wet chemical method, pulsed laser deposition (PLD), etc. and their applicability for use as optoelectronic devices, laser devices, chemical sensors, etc. have been identified.
  • Silicon nanowire can be used in various electronic devices. Typically, silicon nanowire is synthesized by chemical vapor deposition using a gold catalyst and a certain precursor vapor phase source (e.g., silane gas).
  • a certain precursor vapor phase source e.g., silane gas.
  • the alignment of the nano wires has been raised as a major obstacle.
  • an independent process such as electron beam lithography must be performed. Then, electrodes are adhered thereto to obtain an operable device.
  • This process undesirably, is complicated and expensive and thus not suitable for mass production at low cost.
  • an object of the present invention is to solve this problem and provide a method for aligning semiconducting nanowires on a metal electrode by which a zinc oxide nanowire and a silicon nanowire are synthesized on a specifically defined region of an electrode made of aluminum, titanium, platinum, etc. and the nanowires are aligned on the wafer scale instantly as they are synthesized.
  • it is possible to manufacture multiple nanowire devices at once at low cost.
  • the method in accordance with the present invention can be effectively utilized to produce various nano devices, including electronic devices, optoelectronic devices, laser devices, chemical sensors, etc., in large quantity.
  • the method for aligning semiconducting nanowires on a metal electrode in accordance with the present invention comprises: [22] a first step of patterning a gold catalyst layer on a conducting electrode made of aluminum (Al), titanium (Ti) and platinum (Pt); and [23] a second step of synthesizing a zinc oxide nanowire and a silicon nanowire in the region where the gold catalyst layer is patterned, as the nanowires are aligned at the same time. [24]
  • Fig. 1 illustrates the devices regularly aligned on a wafer and the nanowires that have grown with patterns as aligned on a conducting electrode in accordance with the present invention.
  • Fig. 2 illustrates the process of patterning a conducting electrode and a gold catalyst layer using a mask in accordance with the present invention.
  • Fig. 3 shows the metals that help the growth of the zinc oxide (ZnO) nanowire and the silicon (Si) nanowire depending on the composition of the reaction gas and the reaction temperature in accordance with the present invention.
  • Fig. 4 shows that the zinc oxide (ZnO) nanowire grows only on the gold catalyst, not on a conductive electrode made of aluminum in accordance with the present invention.
  • Fig. 5 shows that the silicon (Si) nanowire grows only on the gold catalyst, not on a conductive electrode made of titanium in accordance with the present invention.
  • Fig. 6 shows that the zinc oxide nanowire grows both on a conductive electrode made of platinum in accordance with the present invention and the gold catalyst.
  • Fig. 1 illustrates the devices regularly aligned on a wafer and the nanowires that have grown with patterns as aligned on a conducting electrode in accordance with the present invention.
  • Fig. 2 illustrates the process of patterning a conducting electrode and a gold catalyst layer using a mask in accordance with the present invention.
  • a conducting electrode (11) made of aluminum (Al), titanium (Ti), platinum (Pt), etc. is used on a semiconductor wafer (10), as illustrated in Fig. 1.
  • a gold catalyst layer (12) is patterned on the conducting electrode (11).
  • the conducting electrode (11) is processed to a thickness of 3000-8000 A and a line width of 100 ⁇ m by RF sputtering using a shadow mask (20), as illustrated in Fig. 2.
  • the patterning by the RF sputtering is performed under the condition of
  • a gold catalyst layer (12) is formed on the resultant conducting electrode (11).
  • the gold catalyst layer (12) is selectively patterned so that nanowires may grow only on the specific region of the conducting electrode (Al, Ti, Pt) (11).
  • nanowires may grow as aligned on the desired site of the zinc oxide (ZnO) and silicon (Si) substrate.
  • ZnO zinc oxide
  • Si silicon
  • the source material reacts with the gold catalyst to form a eutectic alloy by the vapor-liquid-solid (VLS) mechanism.
  • the gold catalyst layer (12) is patterned to a thickness of
  • Nanowires are synthesized after the gold catalyst layer (12) has been patterned on the conducting electrode (11) to a desired thickness by ion sputtering.
  • a zinc oxide nanowire is synthesized by the carbothermal reduction method.
  • Zinc oxide and graphite powder (99.9 %; -325 mesh; 1:1 mixture) are used as a source material.
  • the reaction is performed at 800-1000 °C for 1-120 minutes.
  • reaction temperature is below 800 °C, the eutectic alloy of the source material and the gold catalyst is not formed easily. In contrast, if the reaction temperature is above 1000 °C, a 3D, rather than ID, nanowire in the form of a large plate is obtained. If the reaction time is outside the above range, a ID nanowire is not synthesized well or a 3D, rather than ID, nanowire in the form of a large plate is obtained.
  • Argon (10-200 seem) is used as a carrier gas and oxygen (0.1-10 seem) is injected as a reaction gas.
  • a silicon nanowire is synthesized by the chemical vapor deposition using a silane gas.
  • reaction pressure is outside the above range, the silicon nanowire is not synthesized properly. If the flow rate of the silane gas and the hydrogen gas is outside the above range, it is difficult to obtain a ID nanowire or an amorphous SiO nanowire is obtained.
  • Fig. 3 shows the metals that help the growth of the zinc oxide (ZnO) nanowire and the silicon (Si) nanowire depending on the composition of the reaction gas and the reaction temperature.
  • the silicon nanowire grows only on gold (Au). If the ratio of silane (SiH )/hydrogen (H ) of the reaction gas is 70-120 and the reaction temperature is 550-700 °C, the silicon nanowire grows only on aluminum (Al). If the ratio of silane (SiH )/hydrogen (H ) of the reaction gas is 10-100 and the reaction temperature is 600-750 °C, the silicon nanowire grows on gold (Au) and platinum (Pt). If the ratio of silane (SiH )/hydrogen (H ) of the reaction gas is 20-120 and the reaction temperature is 750-950 °C, the silicon nanowire grows on platinum (Pt).
  • the zinc oxide nanowire grows only on gold (Au). If the ratio of oxygen/argon of the reaction gas is 1-10 and the reaction temperature is about 850-950 °C, the zinc oxide nanowire grows on platinum (Pt) and gold (Au). And, if the ratio of oxygen/argon of the reaction gas is 2-12 and the reaction temperature is about 950-1000 °C, the zinc oxide nanowire grows only on platinum (Pt).
  • the zinc oxide nanowire can be synthesized on gold (Au) within a broad temperature range of 800-950 °C. But, the nanowire is hardly synthesized on aluminum (Al) or titanium (Ti) as the Al 2 O 3 and TiO 2 oxides are formed.
  • titanium (Ti) the synthesis of the silicon nanowire is very difficult because the eutectic temperature of silicon (Si) and titanium (Ti) is very high at no less than 1300 °C.
  • Fig. 4 shows that the zinc oxide (ZnO) nanowire grows only on the gold catalyst, not on the aluminum conducting electrode (11).
  • the zinc oxide nanowire shown in the figure was obtained by using an aluminum (Al, 5000 A) conducting electrode (11), a part of which is patterned with a gold catalyst layer (12) (Au, 100 A) under the synthesis condition C-(J) of Fig. 3.
  • the zinc oxide nanowire selectively grew only on the region where the gold catalyst layer (12) was patterned.
  • Fig. 5 shows that the silicon (Si) nanowire grows only on the gold catalyst, not on the titanium conducting electrode (11).
  • the silicon nanowire shown in the figure was obtained by using a titanium (Ti, 5000 A) conducting electrode (11), a part of which is patterned with a gold catalyst layer (12) (Au, 100 A) under the synthesis condition C- (3) of Fig. 3.
  • the silicon nanowire selectively grew only on the region where the gold catalyst layer (12) was patterned.
  • Fig. 6 shows that the zinc oxide nanowire grows both on the platinum conducting electrode (11) and the gold catalyst.
  • the zinc oxide nanowire shown in the figure was obtained by using a platinum (Pt, 5000 A) conducting electrode (11), a part of which is patterned with a gold catalyst layer (12) (Au, 100 A) under the synthesis condition C- (6) of Fig. 3.
  • the zinc oxide nanowire grew not only on the region where the gold catalyst layer (12) was patterned but also on the platinum electrode (11).
  • a zinc oxide nanowire and a silicon nanowire are synthesized on a specific region of an electrode made of aluminum, titanium, platinum, etc. and the nanowires are aligned on the wafer scale instantly as they are synthesized. Accordingly, it is possible to manufacture multiple nanowire devices at once at low cost.
  • the method in accordance with the present invention can be effectively utilized to produce various nano devices, including electronic devices, optoelectronic devices, laser devices, chemical sensors, etc., in large quantity.
  • the method for aligning semiconducting nanowires on a metal electrode in accordance with the present invention makes it possible to manufacture multiple nanowire devices at once at low cost.
  • the method in accordance with the present invention can be effectively utilized to produce various nano devices, including electronic devices, optoelectronic devices, laser devices, chemical sensors, etc., in large quantity.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Molecular Biology (AREA)
  • General Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Catalysts (AREA)
  • Inorganic Compounds Of Heavy Metals (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The present invention relates to a method for aligning semiconducting nanowires on a metal electrode (12), more particularly to a method for aligning semiconducting nanowires on a metal electrode (12) by which a zinc oxide nanowire and a silicon nanowire are synthesized on a specific region of an electrode made of Al, Ti, Pt, etc. and the nanowires are aligned on the wafer scale instantly as they are synthesized. The method for aligning semiconducting nanowires on a metal electrode (12) in accordance with the present invention makes it possible to manufacture multiple nanowire devices at low cost. Thus, the method in accordance with the present invention can be effectively utilized to produce various nano devices, including electronic devices, optoelectronic devices, laser devices, chemical sensors, etc. in large quantity.

Description

Description ALIGNMENT OF SEMICONDUCTING NANOWIRES ON
METAL ELECTRODES
Technical Field
[1]
[2] The present invention relates to a method for aligning semiconducting nanowires on a metal electrode, more particularly to a method for aligning semiconducting nanowires on a metal electrode by which a zinc oxide nanowire and a silicon nanowire are synthesized on a specific region of an electrode made of Al, Ti, Pt, etc. and the nanowires are aligned on the wafer scale instantly as they are synthesized.
[3]
Background Art
[4]
[5] With the recent advance in semiconductor techniques, electronic devices are becoming more and more integrated.
[6] Especially, in the field of ultra large-scale integrated circuits including CMOS, etc., the line width of the devices is becoming smaller with the high-level integration.
[7] As the size of devices becomes small, the importance of the nanowires that electrically connect them has been increasingly emphasized.
[8] The nanowires find a multitude of applications in the field of optics, mechanics, electronics, etc.
[9] In general, the nanowires are made of GaAs, GaN, InP, ZnO, etc. and researches are actively carried out on their use such as a light-emitting device.
[10] Particularly, GaN, GaAs, ZnO, etc. are used to develop blue light-emitting devices.
And, InAs and InP are utilized in the region of 1.3 to 1.5 mm.
[11] Because of the advantageous features attained within nano size range and superior crystallinity, the nanowires can be utilized in a variety of electronic devices, optoelectronic devices, sensors, etc.
[12] The semiconducting nanowire that has been researched most is zinc oxide (ZnO) nanowire. One-dimensional nanoscale objects with a variety of forms (nanowire, nanorod, nanosheet, etc.) have been synthesized by carbothermal reduction method, chemical vapor deposition (CVD), wet chemical method, pulsed laser deposition (PLD), etc. and their applicability for use as optoelectronic devices, laser devices, chemical sensors, etc. have been identified.
[13] Silicon nanowire can be used in various electronic devices. Typically, silicon nanowire is synthesized by chemical vapor deposition using a gold catalyst and a certain precursor vapor phase source (e.g., silane gas). [14] However, with the utilization of nanowire devices in the semiconductor field, as compared with the conventional thin film-based technology, the alignment of the nano wires has been raised as a major obstacle. [15] In the conventional method, after each nanowire is synthesized, an independent process such as electron beam lithography must be performed. Then, electrodes are adhered thereto to obtain an operable device. [16] This process, undesirably, is complicated and expensive and thus not suitable for mass production at low cost. [17] Accordingly, an object of the present invention is to solve this problem and provide a method for aligning semiconducting nanowires on a metal electrode by which a zinc oxide nanowire and a silicon nanowire are synthesized on a specifically defined region of an electrode made of aluminum, titanium, platinum, etc. and the nanowires are aligned on the wafer scale instantly as they are synthesized. In accordance with the present invention, it is possible to manufacture multiple nanowire devices at once at low cost. Thus, the method in accordance with the present invention can be effectively utilized to produce various nano devices, including electronic devices, optoelectronic devices, laser devices, chemical sensors, etc., in large quantity. [18]
Disclosure [19]
[20] Hereunder is given a detailed description of the present invention.
[21] The method for aligning semiconducting nanowires on a metal electrode in accordance with the present invention comprises: [22] a first step of patterning a gold catalyst layer on a conducting electrode made of aluminum (Al), titanium (Ti) and platinum (Pt); and [23] a second step of synthesizing a zinc oxide nanowire and a silicon nanowire in the region where the gold catalyst layer is patterned, as the nanowires are aligned at the same time. [24]
Description of Drawings [25] [26] Fig. 1 illustrates the devices regularly aligned on a wafer and the nanowires that have grown with patterns as aligned on a conducting electrode in accordance with the present invention. [27] Fig. 2 illustrates the process of patterning a conducting electrode and a gold catalyst layer using a mask in accordance with the present invention. [28] Fig. 3 shows the metals that help the growth of the zinc oxide (ZnO) nanowire and the silicon (Si) nanowire depending on the composition of the reaction gas and the reaction temperature in accordance with the present invention. [29] Fig. 4 shows that the zinc oxide (ZnO) nanowire grows only on the gold catalyst, not on a conductive electrode made of aluminum in accordance with the present invention. [30] Fig. 5 shows that the silicon (Si) nanowire grows only on the gold catalyst, not on a conductive electrode made of titanium in accordance with the present invention. [31] Fig. 6 shows that the zinc oxide nanowire grows both on a conductive electrode made of platinum in accordance with the present invention and the gold catalyst. [32]
Best Mode [33]
[34] Now, the present invention is described in more detail referring to the accompanying drawings. [35] Fig. 1 illustrates the devices regularly aligned on a wafer and the nanowires that have grown with patterns as aligned on a conducting electrode in accordance with the present invention. [36] Fig. 2 illustrates the process of patterning a conducting electrode and a gold catalyst layer using a mask in accordance with the present invention. [37] In a preferred embodiment of the present invention, a conducting electrode (11) made of aluminum (Al), titanium (Ti), platinum (Pt), etc. is used on a semiconductor wafer (10), as illustrated in Fig. 1. [38] A gold catalyst layer (12) is patterned on the conducting electrode (11). First, the conducting electrode (11) is processed to a thickness of 3000-8000 A and a line width of 100 μm by RF sputtering using a shadow mask (20), as illustrated in Fig. 2. [39] Typically, the patterning by the RF sputtering is performed under the condition of
30-80 W, argon (Ar) atmosphere and 10-20 mTorr. [40] A gold catalyst layer (12) is formed on the resultant conducting electrode (11). The gold catalyst layer (12) is selectively patterned so that nanowires may grow only on the specific region of the conducting electrode (Al, Ti, Pt) (11). [41] It is well known by those skilled in the art that, when gold is used in the catalyst layer (12), nanowires may grow as aligned on the desired site of the zinc oxide (ZnO) and silicon (Si) substrate. [42] It is because the source material reacts with the gold catalyst to form a eutectic alloy by the vapor-liquid-solid (VLS) mechanism. [43] In the present invention, the gold catalyst layer (12) is patterned to a thickness of
20-100 A by ion sputtering. [44] Nanowires are synthesized after the gold catalyst layer (12) has been patterned on the conducting electrode (11) to a desired thickness by ion sputtering. A zinc oxide nanowire is synthesized by the carbothermal reduction method.
[45] Zinc oxide and graphite powder (99.9 %; -325 mesh; 1:1 mixture) are used as a source material. The reaction is performed at 800-1000 °C for 1-120 minutes.
[46] If the reaction temperature is below 800 °C, the eutectic alloy of the source material and the gold catalyst is not formed easily. In contrast, if the reaction temperature is above 1000 °C, a 3D, rather than ID, nanowire in the form of a large plate is obtained. If the reaction time is outside the above range, a ID nanowire is not synthesized well or a 3D, rather than ID, nanowire in the form of a large plate is obtained.
[47] Argon (10-200 seem) is used as a carrier gas and oxygen (0.1-10 seem) is injected as a reaction gas.
[48] If the flow rate of the argon gas is smaller than 10 seem, the source material is not fully vaporized, thus causing difficulty in nanowire synthesis. Also, a flow rate larger than 200 seem makes the nanowire synthesis difficult. If the flow rate of the reaction gas oxygen is outside the above range, a ID nanowire is not synthesized well or a 3D, rather than ID, nanowire in the form of a large plate is obtained.
[49] Further, a silicon nanowire is synthesized by the chemical vapor deposition using a silane gas.
[50] At a pressure of 1-100 Torr, a silane (SiH ) gas and a hydrogen (H ) gas diluted to
5 % are injected to a metal-organic gas helium (He) at a flow rate of about 10-100 seem and 10-200 seem, respectively.
[51] If the reaction pressure is outside the above range, the silicon nanowire is not synthesized properly. If the flow rate of the silane gas and the hydrogen gas is outside the above range, it is difficult to obtain a ID nanowire or an amorphous SiO nanowire is obtained.
[52] The metals that can give rise to zinc oxide and silicon nanowires under specific composition and reaction temperature are illustrated in Fig. 3.
[53] That is, Fig. 3 shows the metals that help the growth of the zinc oxide (ZnO) nanowire and the silicon (Si) nanowire depending on the composition of the reaction gas and the reaction temperature.
[54] For example, if the ratio of silane (SiH )/hydrogen (H ) of the reaction gas is 10-80 and the reaction temperature is 500-600 °C, the silicon nanowire grows only on gold (Au). If the ratio of silane (SiH )/hydrogen (H ) of the reaction gas is 70-120 and the reaction temperature is 550-700 °C, the silicon nanowire grows only on aluminum (Al). If the ratio of silane (SiH )/hydrogen (H ) of the reaction gas is 10-100 and the reaction temperature is 600-750 °C, the silicon nanowire grows on gold (Au) and platinum (Pt). If the ratio of silane (SiH )/hydrogen (H ) of the reaction gas is 20-120 and the reaction temperature is 750-950 °C, the silicon nanowire grows on platinum (Pt).
[55] Also, if the ratio of oxygen/argon of the reaction gas is 0.5-12 and the reaction temperature is about 800-850 °C, the zinc oxide nanowire grows only on gold (Au). If the ratio of oxygen/argon of the reaction gas is 1-10 and the reaction temperature is about 850-950 °C, the zinc oxide nanowire grows on platinum (Pt) and gold (Au). And, if the ratio of oxygen/argon of the reaction gas is 2-12 and the reaction temperature is about 950-1000 °C, the zinc oxide nanowire grows only on platinum (Pt).
[56] The reason of elucidating the growth of the zinc oxide nanowire and the silicon nanowire on different metals depending on the composition and reaction gas is stated as follows: the eutectic temperature and the eutectic composition change when the source elements zinc (Zn) and silicon (Si) of the nanowires are mixed with the platinum (Pt), aluminum (Al) and titanium (Ti) metals of the conducting electrode (11), as shown in Table 1 below.
[57] For example, because the eutectic temperature of zinc (Zn) and gold (Au) is 683
°C, the zinc oxide nanowire can be synthesized on gold (Au) within a broad temperature range of 800-950 °C. But, the nanowire is hardly synthesized on aluminum (Al) or titanium (Ti) as the Al 2 O 3 and TiO 2 oxides are formed.
[58] In case of the silicon nanowire, the inside of the reactor is under strong reduction atmosphere because the hydrogen (H ) gas is injected, differently from the case of zinc oxide nanowire.
[59] Therefore, the formation of Al O or TiO oxides is prevented and the silicon
2 3 2 nanowire can be synthesized on aluminum (Al).
[60] As for titanium (Ti), the synthesis of the silicon nanowire is very difficult because the eutectic temperature of silicon (Si) and titanium (Ti) is very high at no less than 1300 °C.
[Table 1 ]
Figure imgf000008_0001
[61] Fig. 4 shows that the zinc oxide (ZnO) nanowire grows only on the gold catalyst, not on the aluminum conducting electrode (11). The zinc oxide nanowire shown in the figure was obtained by using an aluminum (Al, 5000 A) conducting electrode (11), a part of which is patterned with a gold catalyst layer (12) (Au, 100 A) under the synthesis condition C-(J) of Fig. 3.
[62] As seen in the figure, the zinc oxide nanowire selectively grew only on the region where the gold catalyst layer (12) was patterned.
[63] Fig. 5 shows that the silicon (Si) nanowire grows only on the gold catalyst, not on the titanium conducting electrode (11). The silicon nanowire shown in the figure was obtained by using a titanium (Ti, 5000 A) conducting electrode (11), a part of which is patterned with a gold catalyst layer (12) (Au, 100 A) under the synthesis condition C- (3) of Fig. 3.
[64] As seen in the figure, the silicon nanowire selectively grew only on the region where the gold catalyst layer (12) was patterned.
[65] Fig. 6 shows that the zinc oxide nanowire grows both on the platinum conducting electrode (11) and the gold catalyst. The zinc oxide nanowire shown in the figure was obtained by using a platinum (Pt, 5000 A) conducting electrode (11), a part of which is patterned with a gold catalyst layer (12) (Au, 100 A) under the synthesis condition C- (6) of Fig. 3.
[66] As seen in the figure, the zinc oxide nanowire grew not only on the region where the gold catalyst layer (12) was patterned but also on the platinum electrode (11).
[67] In accordance with the method for aligning semiconducting nanowires on a metal electrode of the present invention, a zinc oxide nanowire and a silicon nanowire are synthesized on a specific region of an electrode made of aluminum, titanium, platinum, etc. and the nanowires are aligned on the wafer scale instantly as they are synthesized. Accordingly, it is possible to manufacture multiple nanowire devices at once at low cost. Thus, the method in accordance with the present invention can be effectively utilized to produce various nano devices, including electronic devices, optoelectronic devices, laser devices, chemical sensors, etc., in large quantity.
[68]
Industrial Applicability
[69]
[70] As apparent from the above description, the method for aligning semiconducting nanowires on a metal electrode in accordance with the present invention makes it possible to manufacture multiple nanowire devices at once at low cost. Thus, the method in accordance with the present invention can be effectively utilized to produce various nano devices, including electronic devices, optoelectronic devices, laser devices, chemical sensors, etc., in large quantity.
[71] Those skilled in the art will appreciate that the concepts and specific embodiments disclosed in the foregoing description may be readily utilized as a basis for modifying or designing other embodiments for carrying out the same purposes of the present invention. Those skilled in the art will also appreciate that such equivalent embodiments do not depart from the spirit and scope of the present invention as set forth in the appended claims.

Claims

Claims
[1] A method for aligning semiconducting nano wires on a metal electrode comprising: a first step of patterning a gold catalyst layer on a conducting electrode made of aluminum (Al), titanium (Ti) and platinum (Pt); and a second step of synthesizing a zinc oxide nanowire and a silicon nanowire in the region where the gold catalyst layer is patterned instantly as the nanowires are aligned.
[2] The method for aligning semiconducting nanowires on a metal electrode as set forth in Claim 1, wherein the conducting electrode has a thickness of 3000-8000 A and a line width of 100 μm.
[3] The method for aligning semiconducting nanowires on a metal electrode as set forth in Claim 1, wherein the gold catalyst layer has a thickness of 20-100 A and can be patterned by ion sputtering.
[4] The method for aligning semiconducting nanowires on a metal electrode as set forth in Claim 1, wherein the zinc oxide nanowire is synthesized by the car- bothermal reduction method using zinc oxide and graphite powder (99.9 %; -325 mesh; 1:1 mixture) as a source material at 800-1000 °C for 1-120 minutes, while injecting argon (10-200 seem) as a carrier gas and oxygen (0.1-10 seem) as a reaction gas.
[5] The method for aligning semiconducting nanowires on a metal electrode as set forth in Claim 1, wherein the silicon nanowire is synthesized by the chemical vapor deposition under the reaction pressure of 1-100 Torr, while injecting a silane (SiH ) gas and a hydrogen (H ) gas diluted to 5 % are injected to a metal- organic gas helium (He) at a flow rate of about 10-100 seem and 10-200 seem, respectively.
[6] The method for aligning semiconducting nanowires on a metal electrode as set forth in Claim 1, wherein the zinc oxide nanowire grows on gold (Au) when the reaction gas has an oxygen/argon ratio of 0.5-12 and the reaction temperature is about 800-850 °C.
[7] The method for aligning semiconducting nanowires on a metal electrode as set forth in Claim 1, wherein the zinc oxide nanowire grows on platinum (Pt) and gold (Au) when the reaction gas has an oxygen/argon ratio of 1-10 and the reaction temperature is about 850-950 °C.
[8] The method for aligning semiconducting nanowires on a metal electrode as set forth in Claim 1, wherein the zinc oxide nanowire grows on platinum (Pt) when the reaction gas has an oxygen/argon ratio of 2-12 and the reaction temperature is about 950-1000 °C. [9] The method for aligning semiconducting nanowires on a metal electrode as set forth in Claim 1, wherein the silicon nanowire grows on gold (Au) when the reaction gas has a silane (SiH )/hydrogen (H ) ratio of 10-80 and the reaction temperature is about 500-600 °C. [10] The method for aligning semiconducting nanowires on a metal electrode as set forth in Claim 1, wherein the silicon nanowire grows on aluminum (Al) when the reaction gas has a silane (SiH )/hydrogen (H ) ratio of 70-120 and the reaction temperature is about 550-700 °C. [11] The method for aligning semiconducting nanowires on a metal electrode as set forth in Claim 1, wherein the silicon nanowire grows on platinum (Pt) and gold
(Au) when the reaction gas has a silane (SiH )/hydrogen (H ) ratio of 10-100 and the reaction temperature is about 600-750 °C. [12] The method for aligning semiconducting nanowires on a metal electrode as set forth in Claim 1, wherein the silicon nanowire grows on platinum (Pt) when the reaction gas has a silane (SiH )/hydrogen (H ) ratio of 20-120 and the reaction temperature is about 750-950 °C.
PCT/KR2006/005054 2006-07-27 2006-11-28 Alignment of semiconducting nanowires on metal electrodes Ceased WO2008013341A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE112006003964T DE112006003964T5 (en) 2006-07-27 2006-11-28 Arrangement of semiconducting nanowires on metal electrodes
US12/374,750 US20090317943A1 (en) 2006-07-27 2006-11-28 Alignment of Semiconducting Nanowires on Metal Electrodes

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2006-0070528 2006-07-27
KR1020060070528A KR100785347B1 (en) 2006-07-27 2006-07-27 Alignment method of semiconductor nanowire on metal electrode

Publications (1)

Publication Number Publication Date
WO2008013341A1 true WO2008013341A1 (en) 2008-01-31

Family

ID=38981638

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2006/005054 Ceased WO2008013341A1 (en) 2006-07-27 2006-11-28 Alignment of semiconducting nanowires on metal electrodes

Country Status (4)

Country Link
US (1) US20090317943A1 (en)
KR (1) KR100785347B1 (en)
DE (1) DE112006003964T5 (en)
WO (1) WO2008013341A1 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080264185A1 (en) * 2007-04-25 2008-10-30 Kobayashi Nobuhiko P Sensing device and methods for forming and using the same
EP2088430A1 (en) * 2008-01-30 2009-08-12 Korea Institute Of Science And Technology Biosensor having 3D metalic nanowire electrodes forming nanochannel, manufacturing method thereof, and bio disk system having same
CN101552203B (en) * 2008-04-02 2010-07-21 中国科学院微电子研究所 Method for realizing ZnO nanowire fixation in preparation of ZnO nanowire field effect tube
CN101886281A (en) * 2010-06-30 2010-11-17 长春理工大学 Si-ZnO one-dimensional nanomaterial and its preparation method
US8608849B2 (en) 2008-04-09 2013-12-17 Tsinghua University Method for making zinc oxide nano-structrure
CN103966662A (en) * 2014-04-01 2014-08-06 中国科学院重庆绿色智能技术研究院 Method for positioning transversely-growing zinc oxide nanowires on silicon electrode
CN105129840A (en) * 2015-07-17 2015-12-09 兰州思雪纳米科技有限公司 Method of preparing monocrystal zinc oxide nano wire at high yield

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7892610B2 (en) * 2007-05-07 2011-02-22 Nanosys, Inc. Method and system for printing aligned nanowires and other electrical devices
WO2011133144A1 (en) 2010-04-20 2011-10-27 Hewlett-Packard Development Company, L.P. A self-arranging, luminescence-enhancement device for surface-enhanced luminescence
US9274058B2 (en) 2010-10-20 2016-03-01 Hewlett-Packard Development Company, L.P. Metallic-nanofinger device for chemical sensing
WO2012054027A1 (en) 2010-10-20 2012-04-26 Hewlett-Packard Development Company, L.P. Chemical-analysis device integrated with metallic-nanofinger device for chemical sensing
JP2013219203A (en) * 2012-04-09 2013-10-24 Canon Inc Columnar structure manufacturing method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020172820A1 (en) * 2001-03-30 2002-11-21 The Regents Of The University Of California Methods of fabricating nanostructures and nanowires and devices fabricated therefrom

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6036774A (en) * 1996-02-26 2000-03-14 President And Fellows Of Harvard College Method of producing metal oxide nanorods
US7301199B2 (en) * 2000-08-22 2007-11-27 President And Fellows Of Harvard College Nanoscale wires and related devices
US6872645B2 (en) 2002-04-02 2005-03-29 Nanosys, Inc. Methods of positioning and/or orienting nanostructures
US6831017B1 (en) * 2002-04-05 2004-12-14 Integrated Nanosystems, Inc. Catalyst patterning for nanowire devices
US20030189202A1 (en) * 2002-04-05 2003-10-09 Jun Li Nanowire devices and methods of fabrication
JP2005534515A (en) 2002-08-01 2005-11-17 ステイト オブ オレゴン アクティング バイ アンド スルー ザ ステイト ボード オブ ハイヤー エデュケーション オン ビハーフ オブ ポートランド ステイト ユニバーシティー Method for synthesizing nanoscale structure in place
US20050112048A1 (en) 2003-11-25 2005-05-26 Loucas Tsakalakos Elongated nano-structures and related devices
US7158219B2 (en) 2004-09-16 2007-01-02 Hewlett-Packard Development Company, L.P. SERS-active structures including nanowires

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020172820A1 (en) * 2001-03-30 2002-11-21 The Regents Of The University Of California Methods of fabricating nanostructures and nanowires and devices fabricated therefrom

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PARK J.-H. ET AL.: "Alignment of ZnO nanowires on Al, Ti, Pt electrodes", MATERIALS LETTERS, vol. 60, no. 17-18, 31 January 2006 (2006-01-31), pages 2282 - 2287 *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080264185A1 (en) * 2007-04-25 2008-10-30 Kobayashi Nobuhiko P Sensing device and methods for forming and using the same
US8347726B2 (en) * 2007-04-25 2013-01-08 Hewlett-Packard Development Company, L.P. Free-standing nanowire sensor and methods for forming and using the same
EP2088430A1 (en) * 2008-01-30 2009-08-12 Korea Institute Of Science And Technology Biosensor having 3D metalic nanowire electrodes forming nanochannel, manufacturing method thereof, and bio disk system having same
CN101552203B (en) * 2008-04-02 2010-07-21 中国科学院微电子研究所 Method for realizing ZnO nanowire fixation in preparation of ZnO nanowire field effect tube
US8608849B2 (en) 2008-04-09 2013-12-17 Tsinghua University Method for making zinc oxide nano-structrure
CN101555034B (en) * 2008-04-09 2014-04-30 清华大学 Method for preparing zinc oxide nano structure
CN101886281A (en) * 2010-06-30 2010-11-17 长春理工大学 Si-ZnO one-dimensional nanomaterial and its preparation method
CN103966662A (en) * 2014-04-01 2014-08-06 中国科学院重庆绿色智能技术研究院 Method for positioning transversely-growing zinc oxide nanowires on silicon electrode
CN103966662B (en) * 2014-04-01 2016-06-15 中国科学院重庆绿色智能技术研究院 A kind of method positioning cross growth zinc oxide nanowire on silicon electrode
CN105129840A (en) * 2015-07-17 2015-12-09 兰州思雪纳米科技有限公司 Method of preparing monocrystal zinc oxide nano wire at high yield

Also Published As

Publication number Publication date
KR100785347B1 (en) 2007-12-18
US20090317943A1 (en) 2009-12-24
DE112006003964T5 (en) 2009-07-09

Similar Documents

Publication Publication Date Title
US6833558B2 (en) Parallel and selective growth method of carbon nanotube on the substrates for electronic-spintronic device applications
CN101550531B (en) Method for preparing silicon nano structures
US8207449B2 (en) Nano-wire electronic device
Yang et al. Influence of Temperature on Evolution of Coaxial ZnO/Al2O3 One-Dimensional Heterostructures: From Core− Shell Nanowires to Spinel Nanotubes and Porous Nanowires
Xu et al. Quasi-aligned ZnO nanotubes grown on Si substrates
Han et al. Controlled growth of gallium nitride single-crystal nanowires using a chemical vapor deposition method
US20090317943A1 (en) Alignment of Semiconducting Nanowires on Metal Electrodes
US20030126742A1 (en) Method of fabrication of ZnO nanowires
JP2008143771A (en) Method for producing oxide-based nanostructure
CN103531447B (en) A kind of method reducing defect density of gallium nitride nanowire array crystal
Wong et al. Gold nanowires from silicon nanowire templates
US20100291408A1 (en) Nanostructures including a metal
Tseng et al. Low-temperature growth of ZnO nanowires
KR100709112B1 (en) Alumina thin film coating method using atomic layer deposition on nanowire and nanotube surface
KR100581005B1 (en) Growth method of silicon carbide nanorods and nanowires using single precursor and thermochemical deposition
KR100455663B1 (en) Metal/nanomaterial heterostructure and method for the preparation thereof
KR100593835B1 (en) Lateral growth method of nanowires by patterning catalyst
KR100975126B1 (en) Copper-doped nitride lean magnetic semiconductor and its manufacturing method
Lee et al. The effect of nanoscale protrusions on field-emission properties for GaN nanowires
Ekielski et al. Implementation of the inductively coupled plasma etching processes for forming gallium nitride nanorods used in ultraviolet light-emitting diode technology
KR100807081B1 (en) Selective growth method of one-dimensional silicon carbide deposition
US9206532B2 (en) Nanostructure device and method for manufacturing nanostructures
JP2001135828A (en) Iii-v compound semiconductor and manufacturing method thereof
CN120081379B (en) In-situ preparation method of nickel silicide nanowires and obtained nickel silicide nanowires
KR100540511B1 (en) Zinc Oxide Nanowires with Multi-Wall Structure and Manufacturing Method Thereof

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 06823762

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 1120060039644

Country of ref document: DE

NENP Non-entry into the national phase

Ref country code: RU

WWE Wipo information: entry into national phase

Ref document number: 12374750

Country of ref document: US

RET De translation (de og part 6b)

Ref document number: 112006003964

Country of ref document: DE

Date of ref document: 20090709

Kind code of ref document: P

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PRSUANT TO RULE 112(1) EPC

122 Ep: pct application non-entry in european phase

Ref document number: 06823762

Country of ref document: EP

Kind code of ref document: A1

REG Reference to national code

Ref country code: DE

Ref legal event code: 8607