WO2008003032A1 - Mémoire non volatile à tension de drain variable - Google Patents

Mémoire non volatile à tension de drain variable Download PDF

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Publication number
WO2008003032A1
WO2008003032A1 PCT/US2007/072343 US2007072343W WO2008003032A1 WO 2008003032 A1 WO2008003032 A1 WO 2008003032A1 US 2007072343 W US2007072343 W US 2007072343W WO 2008003032 A1 WO2008003032 A1 WO 2008003032A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
floating gate
erase
memory device
blocks
Prior art date
Application number
PCT/US2007/072343
Other languages
English (en)
Inventor
Trismardawi Tanadi
Robert Melcher
Subramanyam Chandramouli
Johnny Javanifard
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Publication of WO2008003032A1 publication Critical patent/WO2008003032A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Definitions

  • the present invention relates generally to memory circuits, and more specifically to nonvolatile memory circuits.
  • Nonvolatile memories include FLASH memories that utilize hot electron injection for programming Gate and drain voltages on floating gate transistors are typically elevated during the programming process. Program times for conventional FLASH memories typically increase as the parts age and the number of program/erase cycles increases.
  • Figure 1 shows a floating gate transistor for use in a memory cell
  • Figure 2 shows a block diagram of a memory device
  • Figure 3 shows an erase cycle counter
  • FIGS. 4 and 5 show flowcharts in accordance with various embodiments of the present invention.
  • Figure 6 shows drain voltage during programming versus number of erase cycles
  • Figure 7 shows programming time versus number of erase cycles
  • FIG. 8 shows a diagram of an electronic system in accordance with various embodiments of the present invention.
  • Figure 1 shows a floating gate transistor for use in a memory cell.
  • Floating gate transistor 100 includes a channel region between drain node 102 and source node 1 12, and control gate 110 over the channel region.
  • floating gate transistor 100 has a floating gate (shown schematically at 108) between the control gate and the channel region.
  • Floating gate 108 is electrically isolated from the control gate and the channel region when nominal voltages are applied across the various terminals.
  • a nonvolatile memory device may have a large number of floating gate transistors arranged in arrays.
  • the control gate of each floating gate transistor is connected to a word line and the drain of each floating gate transistor is connected to a bit line.
  • nonvolatile memory refers to a memory device that maintains its state when power is removed.
  • Nonvolatile memories that incorporate floating gate transistors may be referred to as "FLASH" memories, although the various embodiments of the invention are not limited to those memories referred to as FLASH.
  • a memory cell that includes a floating gate transistor may be programmed by inducing hot electron injection from the channel region to the floating gate through the gate oxide by applying relatively high gate and drain voltages.
  • the voltage values applied to the gate and drain of floating gate transistor 100 during programming affect the amount of charge residing on the floating gate after programming.
  • the amount of time that the relatively high gate and drain voltages are applied also affect the amount of charge residing on the floating gate after programming.
  • the amount of stored charge affects current in the channel region by determining the voltage that must be applied to the gate in order to allow the floating gate transistor to conduct current between the source and the drain. This "threshold voltage" of the transistor is the physical form of the data stored in the memory cell. As the charge on the floating gate increases the threshold voltage also increases.
  • floating gate transistors may be programmed and erased many times.
  • the term "erase cycle” refers to the process of removing stored charge on the floating gate 108.
  • Programming time may be dependent on the number of erase cycles a floating gate transistor has undergone. For example, a memory device that has been programmed and erased only a few times may have a shorter program time than a memory device that has been programmed and erased many times.
  • the voltage applied to drain node 102 during programming is varied as a function of the number of previous erase cycles. For example, as the number of erase cycles increases, the drain node voltage used during programming may be increased. By increasing drain node voltage as the number of erase cycles increases, the programming time may be held more constant during the life of the memory device. Further, by providing for a lower drain voltage earlier in the life of the memory device, reliability may be increased.
  • Figure 2 shows a block diagram of a memory device.
  • Memory device 200 includes write/erase control engine 210, erase cycle counter 220, variable voltage source 230, and memory blocks 240, 242, and 244.
  • Memory blocks 240, 242, and 244 include arrays of floating gate transistors, such as floating gate transistor 100 ( Figure 1).
  • Write/erase control engine 210 provides control signals (not shown) to various circuits within memory device 200.
  • write/erase control engine 210 may provide timing control signals to erase cycle counter 220 and variable voltage source 230.
  • Write/erase control engine 210 may be any type of controller suitable to effect programming and erasing operations within memory device 200.
  • control engine 210 may be an embedded microprocessor, microcontroller, or the like. In operation, control engine 210 may receive and execute software instructions from a microcode store. Microcode may be held in a nonvolatile memory element. The manner in which write/erase control engine 210 is implemented is not a limitation of the present invention.
  • variable voltage source 230 provides a variable voltage on node 232 in response to information received on node 222 from erase cycle counter 220.
  • Variable voltage source 230 may be implemented in any manner suitable to provide a plurality of different voltage values on node 232.
  • variable voltage source 230 may include multiple precision voltage sources, and the output nodes of the voltage sources may be multiplexed onto node 232.
  • variable voltage source 230 generates a different output voltage using trimmable circuit elements. The manner in which variable voltage source 230 is implemented is not a limitation of the present invention.
  • Erase cycle counter 220 is an example of a mechanism to keep track of the number of erase cycles for each of the 2 N memory blocks.
  • erase cycle counter 220 may include at least one digital storage location corresponding to each of the 2 N memory blocks, and stored values in the digital storage locations may be incremented when the corresponding memory block is erased.
  • the information stored in erase cycle counter 220 may be provided to variable voltage source 230 during a programming cycle, and variable voltage source 230 may provide a different voltage on node 232 based on that information.
  • Node 232 is coupled to the drain nodes of floating gate transistors within the memory blocks.
  • drain node 102 ( Figure 1) may receive a voltage from variable voltage source 230 on node 232.
  • node 232 may include many different physical circuit nodes or traces, and variable voltage source 230 may provide voltages to the various memory blocks on different traces.
  • erase cycle counter 220 increments a digital word maintained for the block being erased. For example, if block 240 is erased, erase cycle counter 220 will increment a digital word corresponding to block 240. In this manner, erase cycles may be counted separately for each memory block in memory device 200.
  • erase cycle counter 220 provides the erase cycle count of the block being addressed to variable voltage source 230.
  • Variable voltage source 230 then provides a different voltage to be provided on a drain nodes of floating gate transistors based on the number of erase cycles that the addressed block has undergone.
  • the user address provided on node 202 is shown having components X, Y, and Z.
  • Z includes "N" signal lines used to decode one of 2 N blocks.
  • the X and Y components of the user address may be utilized to address rows and columns within a selected block.
  • Memory device 200 may include functional blocks and signal lines not shown in Figure 2.
  • memory device 200 may include a write interface circuit or a read interface circuit that couples various portions of memory device 200 to an external bus.
  • memory device 200 may include signal lines from one or more interface circuits to control engine 210, erase cycle counter 220, or any other block shown in Figure 2.
  • the blocks that are shown in Figure 1 were chosen to support an explanation of various embodiments relating to the programming of the memory blocks using variable drain voltages.
  • memory device 200 is a FLASH memory that includes arrays of multilevel cells (MLC).
  • MLC multilevel cells
  • each multilevel cell may support four different program states represented by different threshold voltages on a floating gate transistor. These four states may be represented as level zero (LO), level one (Ll), level two (L2), and level three (L3), where LO corresponds to an unprogrammed memory cell with a lowest threshold voltage, L3 corresponds to a programmed memory cell with a highest threshold voltage, and Ll and L2 correspond to programmed memory cells with intermediate threshold voltages.
  • L3, L2, Ll , and LO may also be represented as "00,” “01,” “10,” and “11,” respectively.
  • Figure 3 shows an erase cycle counter.
  • Erase cycle counter 220 includes incrementer 320 and nonvolatile array 310.
  • Nonvolatile array 310 is shown receiving the Z portion of the user address, read/write control information on node 312, and an incremented word on node 322.
  • the read/write control information may be provided by write/erase control engine 210 ( Figure 2).
  • nonvolatile array 310 receives the Z portion of the address and produces an erase cycle count on node 222 corresponding to the addressed block. Further, an incremented erase cycle count is written back to nonvolatile array 310.
  • nonvolatile array 310 receives the Z portion of the user address and provides the erase cycle count for the addressed block on node 222. An incremented erase cycle count is not written back to nonvolatile array 310 during a programming operation. As described above with reference to Figure 2, the erase cycle count on node 222 may be utilized to provide a different drain voltage for a particular memory block during a programming operation.
  • Nonvolatile array 310 may be any type of memory array capable of holding information relating to the erased cycle count of memory blocks within a memory device.
  • nonvolatile array 310 may include floating gate transistors such as floating gate transistor 100 ( Figure 1).
  • nonvolatile array 310 includes one addressable location for each block of memory within a memory device. In other embodiments, nonvolatile array 310 may include multiple storage locations for each addressable memory block.
  • Figures 4 and 5 show flowcharts in accordance with various embodiments of the present invention.
  • methods 400 and 500 may be used to erase and program a nonvolatile memory device.
  • methods 400 and 500, or portions thereof are performed by a controller in a nonvolatile memory device, embodiments of which are shown in the various figures.
  • methods 400 and 500, or portions thereof are performed by a combination of hardware and software in a nonvolatile memory device.
  • Methods 400 and 500 are not limited by the particular type of apparatus or software element performing the method.
  • the various actions in methods 400 and 500 may be performed in the order presented, or may be performed in a different order. Further, in some embodiments, some actions listed in Figures 4 and 5 are omitted from methods 400 and 500.
  • method 400 is shown beginning at block 410 in which the erase cycle count of a memory block is obtained.
  • this corresponds to an erase cycle counter providing an erase cycle count for an addressed block.
  • erase cycle counter 220 Figures 2, 3 may receive a portion of a user address, decode the block being addressed, and provide an erase cycle count for that block on node 222.
  • the erase cycle count is updated for the block.
  • incrementer 320 Figure 3) may increment the erase cycle count, and the incremented erase cycle count may be written to nonvolatile memory 310 in response to the read/write information provided on node 312.
  • the block is erased.
  • method 400 performs an erase of a block in a memory device and updates an erase cycle count for that block.
  • method 400 repeats the block erasure for multiple blocks, and erase cycle counts are updated for the multiple blocks.
  • method 500 is shown beginning at block 510 in which the erase cycle count of an addressed block is obtained.
  • the actions of block 510 may be performed when the "N" bits of an address are used to look up an erase count in a nonvolatile memory such as nonvolatile memory 310 ( Figure 3).
  • a drain voltage for the addressed memory block is set based on the erase cycle count for the addressed block. In some embodiments, this may correspond to variable voltage source 230 ( Figure 2) setting a drain voltage on node 232 in response to an erase cycle count provided by erase cycle counter 220.
  • the addressed block is programmed.
  • the drain voltage used during programming of a memory block is increased as the number erase cycles increases for that memory block.
  • Waveform 620 represents the drain voltage used for programming. As the number of erase cycles increases, the drain voltage also increases. Waveform 620 is shown with coarse granularity and appears as a stair-step pattern. This is not a limitation of the present invention. For example, in some embodiments, many more discrete drain voltages are available, and waveform 620 appears to have smaller steps. Further, in some embodiments, waveform 620 appears almost linear. Also for example, in some embodiments, fewer discrete drain voltages are available, and waveform 620 appears as having only one two "steps" between different possible drain voltages. Waveform 610 is shown to compare a nonvariable drain voltage with the variable drain voltage of waveform 620.
  • Figure 7 shows programming time versus number of erase cycles.
  • a programming time specification for a memory device is shown at 730.
  • Programming time specification 730 is generally a published specification that a manufacturer guarantees is a maximum programming time.
  • the actual programming time increases with erase cycle count for a nonvariable drain voltage.
  • the program time is held more constant by increasing the drain voltage as the erase cycle count increases.
  • Waveform 720 is shown as a constant programming time, but this is not a limitation of the present invention.
  • waveform 720 may take on a "sawtooth" pattern when waveform 620 ( Figure 6) has a very coarse stair-step pattern.
  • waveform 720 may gradually increase or decrease depending on the characteristics of the floating gate transistors, and the characteristics of waveform 620.
  • FIG. 8 shows a system diagram in accordance with various embodiments of the present invention.
  • Electronic system 800 includes processor 810, nonvolatile memory device 820, memory 825, digital circuit 830, radio frequency (RF) circuit 840, and antennas 850.
  • Processor 810 may be any type of processor adapted to access nonvolatile memory device 820 and memory 825.
  • processor 810 may be a microprocessor, a digital signal processor, a microcontroller, or the like.
  • Example systems represented by Figure 8 include cellular phones, personal digital assistants, wireless local area network interfaces, or any other suitable system.
  • Nonvolatile memory device 820 may be adapted to hold information for system 800.
  • nonvolatile memory device 820 may hold device configuration data, such as contact information with phone numbers, or settings for digital circuit 830 or RF circuit 840. Further, nonvolatile memory device 820 may hold multimedia files such as photographs or music files. Still further, nonvolatile memory device 820 may hold program code to be executed by processor 810.
  • Nonvolatile memory device 820 may be any of the nonvolatile memory embodiments described herein, including nonvolatile memory device 200 ( Figure 2). Many other systems uses for nonvolatile memory device 820 exist. For example, nonvolatile memory device 820 may be used in a desktop computer, a network bridge or router, or any other system without an antenna.
  • Radio frequency circuit 840 communicates with antennas 850 and digital circuit 830.
  • RF circuit 840 includes a physical interface (PHY) corresponding to a communications protocol.
  • PHY physical interface
  • RF circuit 840 may include modulators, demodulators, mixers, frequency synthesizers, low noise amplifiers, power amplifiers, and the like.
  • RF circuit 840 may include a heterodyne receiver, and in other embodiments, RF circuit 840 may include a direct conversion receiver.
  • RF circuit 840 may include multiple receivers. For example, in embodiments with multiple antennas 850, each antenna may be coupled to a corresponding receiver.
  • RF circuit 840 receives communications signals from antennas 850, and provides signals to digital circuit 830. Further, digital circuit 830 may provide signals to RF circuit 840, which operates on the signals and then transmits them to antennas 850. Digital circuit 830 is coupled to communicate with processor 810 and RF circuit 840. In some embodiments, digital circuit 830 includes circuitry to perform error detection/correction, interleaving, coding/decoding, or the like. Also in some embodiments, digital circuit 830 may implement all or a portion of a media access control (MAC) layer of a communications protocol. In some embodiments, a MAC layer implementation may be distributed between processor 810 and digital circuit 830.
  • MAC media access control
  • Radio frequency circuit 840 may be adapted to receive and demodulate signals of various formats and at various frequencies.
  • RF circuit 840 may be adapted to receive time domain multiple access (TDMA) signals, code domain multiple access (CDMA) signals, global system for mobile communications (GSM) signals, orthogonal frequency division multiplexing (OFDM) signals, multiple-input-multiple-output (MIMO) signals, spatial-division multiple access (SDMA) signals, or any other type of communications signals.
  • TDMA time domain multiple access
  • CDMA code domain multiple access
  • GSM global system for mobile communications
  • OFDM orthogonal frequency division multiplexing
  • MIMO multiple-input-multiple-output
  • SDMA spatial-division multiple access
  • antennas 850 may include a single directional antenna or an omni-directional antenna.
  • the term omni-directional antenna refers to any antenna having a substantially uniform pattern in at least one plane.
  • antennas 850 may include a single omni-directional antenna such as a dipole antenna, or a quarter wave antenna.
  • antennas 850 may include a single directional antenna such as a parabolic dish antenna or a Yagi antenna.
  • antennas 850 may include multiple physical antennas. For example, in some embodiments, multiple antennas are utilized to support multiple-input-multiple-output (MIMO) processing or spatial-division multiple access (SDMA) processing.
  • MIMO multiple-input-multiple-output
  • SDMA spatial-division multiple access
  • Memory 825 represents an article that includes a machine readable medium.
  • memory 825 represents a random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), read only memory (ROM), FLASH memory, or any other type of article that includes a medium readable by processor 810.
  • Memory 825 may store instructions for performing the execution of the various method embodiments of the present invention.
  • processor 810 reads instructions and data from either or both of nonvolatile memory device 820 and memory 825 and performs actions in response thereto.
  • nonvolatile memory device 820 and memory 825 are combined into a single memory device.
  • nonvolatile memory device 820 and memory 825 may both be include in a single nonvolatile memory device.
  • memory 825 or nonvolatile memory device 820 may be an internal memory within processor 810 or may be a microprogram control store within processor 810.
  • the various elements of system 800 may be separately packaged and mounted on a common circuit board.
  • the various elements are separate integrated circuit dice packaged together, such as in a multi-chip module, and in still further embodiments, various elements are on the same integrated circuit die.
  • bus 815 may be a serial interface, a test interface, a parallel interface, or any other type of interface capable of transferring command and status information between processor 810, nonvolatile memory device 820, and memory 825.
  • nonvolatile memory device 820 may include NOR- type FLASH memory cells, and in other embodiments, nonvolatile memory device 820 may include NAND-type FLASH memory cells.
  • Memory cells in nonvolatile memory device 820 may store one data bit per cell, or memory cells may be multilevel cells (MLC) capable of storing more than one bit per cell. Any memory arrangement may be utilized within nonvolatile memory device 820 without departing from the scope of the present invention.
  • Nonvolatile memory devices, controllers, erase cycle counters, and other embodiments of the present invention can be implemented in many ways. In some embodiments, they are implemented in integrated circuits.
  • design descriptions of the various embodiments of the present invention are included in libraries that enable designers to include them in custom or semi-custom designs.
  • any of the disclosed embodiments can be implemented in a synthesizable hardware design language, such as VHDL or Verilog, and distributed to designers for inclusion in standard cell designs, gate arrays, or the like.
  • any embodiment of the present invention can also be represented as a hard macro targeted to a specific manufacturing process.

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Abstract

L'invention concerne une mémoire non volatile qui augmente une tension de drain sur des transistors à gâchette flottante pendant la programmation en fonction du compteur de cycles d'effacement. Lorsqu'un bloc de mémoire est effacé, un compteur de cycles d'effacement pour ce bloc est effacé. Lorsqu'un bloc de mémoire est programmé, le compteur de cycles d'effacement pour ce bloc est utilisé pour déterminer une tension de drain à utiliser sur les transistors à gâchette flottante pendant la programmation.
PCT/US2007/072343 2006-06-29 2007-06-28 Mémoire non volatile à tension de drain variable WO2008003032A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US47853206A 2006-06-29 2006-06-29
US11/478,532 2006-06-29

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WO2008003032A1 true WO2008003032A1 (fr) 2008-01-03

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PCT/US2007/072343 WO2008003032A1 (fr) 2006-06-29 2007-06-28 Mémoire non volatile à tension de drain variable

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WO (1) WO2008003032A1 (fr)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115312103B (zh) * 2022-09-30 2022-12-13 芯天下技术股份有限公司 闪存芯片的擦除电压配置方法、装置、设备及存储介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5793677A (en) * 1996-06-18 1998-08-11 Hu; Chung-You Using floating gate devices as select gate devices for NAND flash memory and its bias scheme
US5867429A (en) * 1997-11-19 1999-02-02 Sandisk Corporation High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates
US6181601B1 (en) * 1999-12-02 2001-01-30 Taiwan Semiconductor Manufacturing Corporation Flash memory cell using p+/N-well diode with double poly floating gate
US7009244B2 (en) * 2003-07-02 2006-03-07 Integrated Memory Technologies, Inc. Scalable flash EEPROM memory cell with notched floating gate and graded source region

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5793677A (en) * 1996-06-18 1998-08-11 Hu; Chung-You Using floating gate devices as select gate devices for NAND flash memory and its bias scheme
US5867429A (en) * 1997-11-19 1999-02-02 Sandisk Corporation High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates
US6181601B1 (en) * 1999-12-02 2001-01-30 Taiwan Semiconductor Manufacturing Corporation Flash memory cell using p+/N-well diode with double poly floating gate
US7009244B2 (en) * 2003-07-02 2006-03-07 Integrated Memory Technologies, Inc. Scalable flash EEPROM memory cell with notched floating gate and graded source region

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