WO2008002581A2

WO2008002581A2 - Multi-port memory device and method

Info

Publication number: WO2008002581A2
Application number: PCT/US2007/014839
Authority: WO
Inventors: Gopal K. Garg; Eric Gross
Original assignee: Cypress Semiconductor Corporation
Priority date: 2006-06-26
Filing date: 2007-06-25
Publication date: 2008-01-03
Also published as: WO2008002581A3

Abstract

A memory device can include a plurality of memory cells arranged into entries that store data values accessible by an applied address. A plurality of read only ports can each applying a read address value corresponding to a different group of entries and receive read data values stored in the group of entries. The read only ports do not apply data values for storage in the group of entries. The memory device can also include at least one read/write port, different from the read only ports, that applies address values corresponding all storage entries and receiving data values stored in the storage entries as read data values, and applying data values for storage in the entries as write data values.

Description

MULTI-PORT MEMORY DEVICE AND METHOD

TECHNICAL FIELD

The present invention relates generally to integrated circuit devices, and more particularly to memory devices.

BACKGROUND OF THE INVENTION

Conventional memory devices can store data values at addressable locations for subsequent retrieval in a read operation. Memory devices can be both volatile and nonvolatile. Volatile memory devices can lose stored data in the absence of power. Nonvolatile memory devices can retain stored information in the absence of power.

While nonvolatile memory devices enjoy a wide variety of applications, one particular application can be that of a device configuration/identification memory. Such a memory can store data that indicates a particular device type, a device identification value, modes of operation, and data transfer/format information, as but a few examples. One very particular type of a device configuration/identification memory can be an extended data display identification (EDID) memory, promulgated by the Video Electronics Standard Organization (VESA). An EDID memory can store up to 32K bytes of information that includes the capabilities of a display device, such as display modes, display resolution, vendor specific information, or a device physical port address, to name but a few examples.

To better understand some features of the disclosed embodiments, a conventional system that includes a conventional EDID memory will now be described.

FIG. 12 shows a conventional multi-port video processor system 1200. The system 1200 includes a video processor 1202, a transmit (Rx) section 1204, one or more data buses 1206-0 and 1206-1, and EDID memories 1208-0 and 1208-1. Rx section 1204 and video processor 1202 can be considered a "sink" side of the system, while EDID memories (1208-0 and 1208-1) can be considered a "source" side of the system. Data buses (1206-0 and 1206-1) can be serial data buses, such as Display Data Channel (DDC) buses, for example,

Each EDID memory (1208-0 and 1208-1) can correspond to a different display port. Different display ports can be one port of a multi-port device, or may correspond to entirely different devices. Data stored in each EDID memory (1208-0 and 1208-1) can be read by a data transmission source to properly format data for the corresponding port prior to transmission. In such multi-port applications (e.g., a television or audio-visual (AV) decoder with multiple high- definition multimedia interface (HDMI) ports), each port can have its own EDID memory, as particular data for each port (e.g., port address) can be different and/or data transfer rates betweei such ports can be different.

Generally, data in EDID memory is fixed, being programmed during production of the device. FIG. 12 shows, by dotted lines, programming paths 1210 that can enable EDID memorie to be programmed in production. Ln addition, such paths can allow for dynamic writing after a system is in operation.

A drawback to an arrangement like that of FIG. 12 can be the size of the system. As mor ports are utilized, a corresponding number of EDED memories are included, resulting in the need for larger amounts of circuit board space. In addition, while programming paths 1210 can allow for programming (or re-programming) of EDID memories after production, such paths may compromise the security of the system. Typically, a conventional Rx section 1204 can include data that should be secured, such as de-encryption keys for data streams, as but one example. Inclusion of programming paths 1210 may provide undesirably easy access to secured data withi the Rx section 1204 or other sections of system 1200.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block schematic diagram of a memory device according to a first embodiment FIG. 2 is a block schematic diagram of a memory device according to a second embodiment.

FIG. 3 is a block schematic diagram of a memory device according to a third embodiment.

FIG. 4A-4C shows a memory device configurable address/control path according to a fourth embodiment.

FIG. 5 shows a memory device configurable data path according to a fourth embodiment FIG. 6 is a block schematic diagram of a memory device according to a fifth embodimen FIG. 7 is a block schematic diagram showing an arbitration circuit according to a sixth embodiment.

FIG. 8 is block schematic diagram of a memory device according to a seventh embodiment.

FIG. 9 is a block schematic diagram of a power supply coupling circuit according to an embodiment.

FIG. .10 is a block schematic diagram of a video processor system according to an embodiment.

FIG. 11 is a diagram showing a device package according to an embodiment.

FIG. 12 is a block schematic diagram of a conventional video processor system.

DETAILED DESCRIPTION

Various embodiments of the present invention will now be described in detail with reference to a number of drawings. The embodiments show memory devices and methods that can provide multiple read-only ports that can provide read data, and provide at least one read- write port that can receive write data and provide read data.

A memory device according to a first embodiment is shown in FIG. 1 and designated by the general reference character 100. A memory device 100 can include multiple read-only ports 102-0 to 102-M (PORT-OR to PORT-MR) and a read/write port 104 (PORT-RW) that is differer from the read-only ports (102-0 to 102-M). Preferably, each read-only port 102 can access a different, non-overlapping address space. Thus, each read-only port (102-0 to 102-M) can be accessed independently of any other read-only port. In addition, in a preferred embodiment, each read-only port (102-0 to 102-M) does not share any read access time with any other read-only port.

Read-only ports (102-0 to 102-M) can receive read addresses, and in response thereto, access a location corresponding to such an address, and output read data from the same port. In one particular arrangement, each read-only port (102-0 to 102-M) can be a serial port.

A read/write port 104 can access the entire address space accessible by all read-only portj (102-0 to 102-M). In this way, a read/write port 104 can be used to write to locations for read ou from read-only ports (102-0 to 102-M). It is understood that as used herein, a "write" operation can include the programming of nonvolatile memory cells. Such a programming can also includi the erasing of memory cells prior to such a programming step.

In one embodiment, the size of a memory space accessed by each read-only port (102-0 t< 102-M) can be configurable. That is, the number of storage locations accessible for each port (102-0 to 102-M) can be varied. Such an arrangement can advantageously accommodate the requirements of different electronic devices with a single memory device.

It is noted that a memory device 100 can include various types of memory cells for storin values accessible by the read-only ports and read/write port. Preferably, the memory cells are nonvolatile memory cells.

In this way, a memory device can provide read operations from read-only ports that acces non-overlapping address spaces, while at the same time including a read/write port that can write data all of the address spaces.

Referring now to FIG. 2, a memory device according to a second embodiment is shown ii a block schematic diagram, and designated by the general reference character 200. Memory device 200 can include some of the same general components as FIG. 1, thus, like reference characters are referred to by the same reference character, but with the first digit being a "2" instead of a "1".

Memory device 200 of FIG. 2 includes read-only ports (202-0 to 202-M), a read/write port 204, serial interfaces (I/Fs) 206-0 to 206-M and 208, and memory array sections 210-0 to 210-M. In the particular example of FIG. 2, read-only ports (202-0 to 202-M) and read/write poi 204 can be serial ports, each having a corresponding clock input (212-0 to 212-M, 214) and a data VO (216-0 to 216-M, 218).

Read-only ports (202-0 to 202-M) can be connected to memory sections (210-0 to 210-M by corresponding serial I/Fs (206-0 to 206-M). Each serial I/F (206-0 to 206-M) can capture serial data values received via its respective data I/Os according to timing established by a clock signal received at the clock input. Such data values can include read commands and read addresses for accessing a memory section (210-0 to 210-M). In addition, each serial I/F (206-0 t 206-M) can also receive read data received from the corresponding memory section (210-0 to 210-M) and output such data on the data I/O, also according to timing established at the accompanying clock input.

FlG. 2 shows an arrangement in which each read-only port (202-0 to 202-M) accesses a single memory section (210-0 to 210-M). That is-, the address space accessed by each read-only port (202-0 to 202-M) is not configurable in size. However, configurable embodiments will be shown below.

Read/write port 204 can be connected to all memory sections (210-0 to 210-M) by a read/write serial I/F 208. Read/write serial I/F 208 can operate in the same general fashion as serial I/Fs of the read-only port. However, read/write port 204 can also receive write commands and write data to enable data values to be written into any of the locations within memory sections (210-0 to 210-M).

It is noted that serial I/Fs (206-0 to 206-M, 208) can operate at different data rates, thus allowing data to be read from and written to different ports at different speeds.

In this way, a memory device can include multiple serial ports for read access from memory sections, and one or more serial read/write ports for writing data to such memory sections.

Referring now to FIG. 3, a memory device according to a third embodiment is shown in ; block schematic diagram, and designated by the general reference character 300. Memory devic 300 can include some of the same general components as FIG. 2, thus, like reference characters are referred to by the same reference character, but with the first digit being a "3" instead of a

The embodiment of FIG. 3 can differ from that of FIG. 2 in that it can include a configuration circuit 350 that can enable a read-only ports (202-0 to 202-M) to access more than one memory section (210-0 to 210-M). In such an arrangement, given M+l sections, a single port can be configured to have a memory space of 0 to M+l sections. In this way, an address space accessed by one read-only port can be larger or smaller than that accessed by another address. Preferably, such different sized addresses spaces do not overlap.

Referring now to FIGS. 4A and 4B, one example of an address portion of a configuratior circuit, like that shown as 350 in FIG. 3, is shown in a block schematic diagram and designated by the general reference character 400. FIG. 4A shows a configuration circuit 400 that provides configurable connection to four memory sections 410-0 to 410-3. Configuration circuit 400 can include four address/control inputs 452-0 to 452-3 and four address/control multiplexers (MUXi 454-0 to 454-3. Address/control inputs (452-0 to 452-3) can receive address values from a port (e.g., by way of a serial I/F), and provide soch values as an input to each address/control MUX (454-0 to 454-3). Address/control MUXs (454-0 to 454-3) can apply a selected address values tc corresponding memory sections 410-0 to 410-3.

Memory sections (410-0 to 410-3) can each include an address/control decoder (456-0 to 456-3). Each address/control decoder can determine access type (e.g., read or write), and provide access to locations within its respective memory section according to a received address value.

FIG. 4A also shows a read/write path 455 that can provide a read or write address and control signals from a read/write port to all memory sections (410-0 to 410-3). Read/write path 455 can include an address/control driver 457 that can drive a read or write address when a read/write port is active, and present a high impedance when the read/write port is not active. In such an arrangement, it is understood that no read-only port accesses are allowed to occur while the read/write port is active.

Referring now to FIG. 4B, one example of an address/control MUX, like those shown in FIG. 4A as 454-0 to 454-3, is shown in a schematic diagram and designated by the general reference character 460. In the particular arrangement shown, selection of each memory section (410-0 to 410-3) can be according to most significant address bits MSBN and MSBN-I, and selection of a given location within a memory section can be according to less significant bits LSBs. Thus, if a memory device 400 is configured for each port to access a different memory section, MSBN/MSBN-1 are not used, as LSBs can be used to access each memory section. If, however, one read-only port accesses two memory sections, address bit MSBN-I can be used to select between each section. Finally, if a read-only port accesses three or more memory sections both address bits MSBN/MSBN-1 can be used to select between different memory sections.

In the very particular example of FIG. 4B, address MUX 460 can include MSB MUX 46^ and LSB MUX 464. MSB MUX 462 includes MUX 462-0 and MUX 462-1. MUX 462-0 can selectively output a received address bit MSBN, or a predetermined value "1" or "0" based on configuration information CNFMSBN. In a similar fashion, MUX 462-1 can selectively output < received address bit MSBN-I, or a predetermined value "1" or "0" based on configuration information CNFMSBN-I.

LSB MUX 464 can selectively input the LSBs of a received address and corresponding control information from one of the read-only ports. FIGS. 4C and 4D are block schematic diagrams illustrating two configurations for a memory device like that o FIG. 4A. FIG. 4C shows an arrangement in which all ports are used, and each port accesses a given memory section (410-0 to 410-3). In the arrangement of FIG. 4C, bits MSBN/MSBN-1 can be forced to particular values to ensure that each memory section (410- 0 to 410-3) can be accessed via the LSBs received from the corresponding port.

FIG. 4D shows an arrangement in which a second read-only port can be configured to access two memory sections, while a first and fourth port access single memory sections. A thirc port is not used. In the arrangement of FIG. 4D, for address MUXs 454-0 and 454-3, bits MSBN/MSBN-1 can be forced to particular values to ensure that the corresponding memory section (410-0 and 410-3) are accessed via the LSBs received from the corresponding ports. However, address MUXs 454-1 and 454-2 only force MSBN to a particular value. This enables address bit MSBN-I from a port 2 to select between memory sections 410-1 and 410-2. LSBs from port 2 can select an entry from the memory section selected by address bit MSBN- 1.

Referring now to FIG. 5, one example of a data portion of a configuration circuit, like tha shown as 350 in FIG. 3, is shown in a block schematic diagram and designated by the general reference character 500. FIG. 5 shows a configuration circuit 500 that includes a read data path for four memory sections 410-0 to 410-3. Configuration circuit 500 provides and four read-only data outputs 502-0 to 502-3, as well as a read/write data input/output (I/O) 504. Memory section (410-0 to 410-3) can output read data in response to receiving read address and command information. Such read data can be provided as inputs to data de-multiplexers (deMUXs) (504-0 to 504-3). Data deMUXs (504-0 to 504-3) can apply accessed read data values to corresponding data outputs (502-0 to 502-3). According to such deMUXs (504-0 to 504-3), read data from a configurable number of memory sections (410-0 to 410-3) can be provided to any one of the read-only ports.

As shown in FIG. 5, each memory sections (410-0 to 410-3) can include a read data path 506-0 to 506-3 and a write data path 508-0 to 508-3. Read data paths (506-0 to 506-3) can provide read data in response to read control signals and address values received by the respective memory section. Similarly, write data paths (508-0 to 508-3) can apply write data values to the respective memory section in response to write control signals and address values received by the respective memory section. FIG. 5 also shows a read/write data' path 555 that can provide read data from, or write dat to, all memory sections (410-0 to 410-3). Read/write data path 555 can include write data driver: 510-0 to 510 -3 and read data drivers 512-0 to 512-3 corresponding to each memory section (410- 0 to 410-3). Such read and write data drivers can drive read or write data when a read/write port is active, and present a high impedance when the read/write port is not active. Again, in such an arrangement, it is understood that no read-only port accesses are allowed to occur while the read/write port is active.

In this way, memory device can have multiple read-only ports each of which can be configured to access different sized, non-overlapping address spaces. Of course, while FIGS. 4 A io 5 show arrangements utilizing MUXs and deMUXs, other embodiments can include crossbar switches and the like to provide selectable address paths between single ports and multiple memory sections.

Still further, while the embodiments of FIGS. 4A to 5 have shown an arrangement with only four memory sections, the addressing arrangement could be changed to accommodate various arrangements of with larger or smaller numbers of sections.

Referring now to FIG. 6, a memory device according to a fourth embodiment is shown in a block schematic diagram, and designated by the general reference character 600. Memory device 600 can include some of the same general components as FIG. 1, thus, like reference characters are referred to by the same reference character, but with the first digit being a "6" instead of a "1".

Memory device 600 of FIG. 6 can include some of the same sections as FIG. 3, including serial interfaces (I/Fs) 606-0 to 606-M and 608. However, unlike the arrangement of FIG. 3, in FIG. 6 a memory array section 610 can be accessed via a single address input. As in the case of FIG. 3, read-only ports (602-0 to 602-M) and read/write port 604 can be serial ports, each having a corresponding clock input (612-0 to 612-M, 614) and a data I/O (616-0 to 616-M, 618). Further, read-only ports (602-0 to 602-M) can be connected to memory array 610 by corresponding serial I/Fs (612-0 to 612-M), while read/write port 604 can be connected to memory array 610 by serial I/F 608.

The embodiment of FIG. 6 can differ from that of FIG. 3 in that it can include an arbitration circuit 650 that arbitrates between competing accesses via read-only ports (602-0 to 602-M) and read/write port 604. In addition, an arbitration circuit 650 can selectively introduce an address offset to enable accesses from each different port to start at a different base address. Thus, each single port can be configured to access different non-overlapping memory spaces that can vary in size.

Referring now to FIG. 7, one example of an arbitration circuit, like that shown as 650 in FIG. 6, is shown in a block schematic diagram and designated by the general reference character 700. An arbitration circuit 700 can include arbitration logic 702, an address/control MUX 704, a read data de-MUX 706, an address offset circuit 708, and a write data driver 710.

Arbitration logic 702 can receive request signals REQO to REQM from serial I/Fs (606-0 to 606-M), as well as request signal REQRW from serial VF 608. A request signal (REQO to REQM, REQRW) can be active when valid data is received at the corresponding serial VF. In response to such request signals, arbitration logic 702 can issue busy signals BUSYO to BUSYM BUSYRW, to serial LTs (606-0 to 606-M, 608). In the event more than one access is requested via serial I/Fs (606-0 to 606-M, 608), arbitration logic 702 can issue busy signals to all but one serial I/F. This can allow a single port to access memory array 610 at a given time, while that same time accommodating multi-port access.

In response to receiving request signals (REQO to REQM, REQRW), arbitration logic 70: can issue control signals MUX-CTRL for controlling address MUX 704 and read data de-MUX 706. More particularly, when one serial I/F has been granted access by arbitration logic 702, an address and control data path for the serial VF can be enabled through address MUX 704. Similarly, a data path from memory array 610 can be enabled through read data de-MUX 706 (assuming the access is a read operation). In the event read/write serial VF 608 has been granted access for a write operation, arbitration logic 702 can enable write driver 710 with enable signal WDEN.

In response to granting access to a serial I/F, arbitration logic 702 can also provide offset select signals OFF_SEL to address offset circuit 708. According to such signals, address offset circuit 708 can generate an address for memory array 610. In one embodiment, a different offset value can exist for each read-only port, thus creating non-overlapping address spaces for each port. In the case of the read/write port, however, no offset is generated to allow access to the entire address space of memory array 610. Addresses provided by address offset circuit 708 can be decoded by decoder 720 to accesi locations within memory array 610. Memory array 610 can also include read access circuit 722 and write access circuit 724. Read access circuit 722 can provide read data values to read data deMUX 706 in a read operation. Write access circuit 724 can write data received from serial JfF 608 to memory array 610.

In this way, a memory device can provide multiple read-only ports utilizing an arbitration arrangement that can receive multiple requests, but arbitrate to allow only one port request to access memory locations at a given time.

The above embodiments have shown arrangements that can provide multiple, separately accessible read-only ports, as well as one or more read/write ports. Other embodiments may advantageously provide a power supply input corresponding to each such port. In such an arrangement, a memory device can receive an operating power supply voltage via any such port. One particular example of such an arrangement is shown in FIGS. 8 and 9.

Referring now to P⁷IG. 8, a memory device according to another embodiment is shown in a block schematic diagram and designated by the general reference character 800.

A memory device 800 can include a number of read-only ports 802-0 to 802-M and a read/write port 804. In the particular example of FIG. 8, each read-only port 802-0 and 802-M can access a corresponding memory section 810-0 to 810-M within a memory array 810. However, it is understood that memory array 810 could be configurable or accessed via an arbitration arrangement as described in the embodiments above.

Unlike the previously described embodiments, memory device 810 can also include a power supply input 820-0 to 820-M corresponding to each read-only port (802-0 to 802-M), as well as a power supply input 824 corresponding to read-write port 804. Power supply inputs (820-0 to 820-M, 824) can be connected to a power supply coupling circuit 826, which can provide a power supply voltage to an internal common power supply node 828.

In response to a power supply voltage being provided at one or more of the power supply inputs (820-0 to 820-M, 824), power supply coupling circuit 826 can provide an operating powei supply voltage at common power supply node 828, to thereby provide a power supply for the memory device 800.

In this way, a memory device 800 can receive a power supply voltage from any of a number of power supply inputs corresponding to read-only and read/write ports.

Referring now to FIG. 9, one particular example of a power supply coupling circuit, like that shown as 826 in FIG. 8, is shown in a schematic diagram and designated by the general reference character 900. A power supply coupling circuit 900 can have a number of different power supply inputs (920-0 to 920-M), each connected to a first power supply node 922 by one c more diodes. The particular arrangement of FIG. 9, one diode (DO to DM+1) is connected between each power supply input and first power supply node 922. First power supply node 922 can be connected an internal power supply node 928 by one or more diodes. The example of FIG. 9 includes two such diodes (D20, D22).

The power supply coupling circuit 900 also includes one or more capacitors Cl and a voltage regulator circuit 930 in parallel between internal power supply node 928 and a low powe supply node 932.

When a power supply voltage received at any of power supply inputs (920-0 to 920-N) is sufficiently high enough in voltage, the corresponding diode(s) (DO to DN+1) between such a power supply input node and first power supply node 922 can be forward biased. In addition, diodes between nodes 922 and 928 can forward bias, resulting in a high power supply voltage being applied at internal node 928. Voltage regulator circuit 930 and capacitor Cl can regulate the voltage at node 928 and thus provide a constant voltage to a memory cell array section.

In this way, a memory device having multiple read-only ports can receive a power supply from any of a number of power supply inputs corresponding to such read-only ports.

Referring now to FIG. 10, a multi-port video processor system is shown in a block schematic diagram, and designated by the general reference character 1000. The system 1000 includes a video processor 1002, a transmit (Rx) section 1004, a number of data buses 1006-0 to 1006-M, and a multiport memory device 1008. Rx section 1004 and video processor 1002 can b considered a "sink" side of the system, while memory device 1008 can be considered a "source" side of the system. Data buses (1006-0 to 1006-M) can be serial data buses. As but one examph such buses can be Display Data Channel (DDC) buses. A memory device 1008 can be a memor; device 1008 according to any of the above described embodiments.

Unlike the conventional system 1300 of FIG. 13, in system 1000 of FIG. 10, a single memory device 1008 can provide multiple read-only ports, eliminating the need to provide a different EDID memory for each device/port of system 1000. This can considerably reduce overall circuit board size. Because each port is separately accessible, read access times for different sources are not shared, thus there is no loss in performance when accessing data. In addition, in particular embodiments, an address space corresponding to each port can be configurable, allowing memory device 1000 to accommodate different storage needs of different devices/ports.

In addition, a read/write port of memory device 1000 can be connected to a sink side of the system by a read/write bus 1010. Read/write bus 1010 can be secure with respect to the source side. Thus, a memory device 1000 can be programmed and subsequently, dynamically written to, while at the same time maintaining secure information in the sink side, such as decryption keys stored in Rx section 1004.

Still further, data buses (1006-0 to 1006-M) can also each include a power supply input. This can allow memory device 1008 to be operational from any active port.

In this way, a system can include a memory device like those described above to provide an advantageously compact and secure storage of device data, such as extended data display identification (EDID) data.

Referring now to FIG. 11, a memory device package according to an embodiment is shown in block schematic diagram and designated by the general reference character 1100. A device package configuration 1100 can include collection of inputs (e.g., pins) corresponding to different read-only ports and a read/write port. In the particular example shown, device package configuration 1100 can provide four port groups (1102-0 to 1102-3) and a read/write port group 1104. Each port group (1102-0 to 1102-3) can include a power supply input pin (VDDO to VDD3, VDDRW), a clock input (CLKO to CLK3, CLKRW), and a data I/O pin (DATAO to DATA3, DATARW). Pins for each port group (1102-0 to 1102-3) are preferably in close proximity with one another, even more preferably adjacent to one another. FIG. 11 also shows a low power supply input VSS.

Of course, FIG. 11 shows but one particular type of device package, and should not be construed as limited to any particular package. Other embodiments can include different packag types, including but not limited to pin grid arrays, and single in line type packages.

It is understood that the embodiments of the invention may be practiced in the absence o\ an element and or step not specifically disclosed. That is, an inventive feature of the invention can be elimination of an element.

Accordingly, while the various aspects of the particular embodiments set forth herein have been described in detail, the present invention could be subject to various changes, substitutions, and alterations without departing from the spirit and scope of the invention.

Claims

INTHE CLAIMSWhat is claimed is:

1. A memory device, comprising: a plurality of memory cells arranged into entries that store data values accessible by an applied address; a plurality of read only ports, each read only port applying a read address value corresponding to a different group of entries and receiving read data values stored in the group of entries, and not applying data values for storage in the group of entries; and at least one read/write port, different from the read only ports, the at least one read/write portion applying address values corresponding all storage entries and receiving data values stored in the storage entries as read data values, or applying data values for storage in the entries as write data values.

2. The memory device of claim 1, wherein: the memory cells comprise nonvolatile memory cells.

3. The memory device of claim 1, wherein: the at least one read/write port consists of a single read/write port.

4. The memory device of claim 1, wherein: each of the read only ports comprises a serial port that receives read address values in serial form, and outputs read data values in serial form; and the at least one read/write port comprises a serial port that receives read address values and write address values in serial form, and inputs write data values and outputs write data values in serial form.

5. The memory device of claim 4, wherein: each read only port includes a clock signal connection for receiving a periodic signal and a data connection for receiving read address values and providing read data values; and the at least one read/write serial port includes a clock signal connection for receiving a periodic signal and a data connection that receives read address values write address values and write data values, and that provides read data values.

6. The memory device of claim 5, wherein: the memory device is an integrated circuit formed in a circuit package having a plurality of external terminals arranged in to groups of adjacent terminals corresponding to each read-only port, each group of adjacent terminals including a clock terminal that receives the clock signal of the corresponding port, and a data terminal coupled to the data connection of the corresponding port.

7. The memory device of claim 1, wherein: the entries are organized into a plurality of sections that each include a different set of entries; and an address decoder, coupled between each port and a corresponding section, that accesses only the entries of the corresponding group in response to a received internal address.

8. The memory device of claim 7, further including: a configuration circuit that provides a signal path for at least a portion of an address received at a first read only port to the address decoder of at least two different sections in a first configuration, and provides a signal path to only one address decoder in a second configuration.

9. The memory device of claim 8, wherein: the configuration circuit provides a signal path for an address received at the at least one read/write port to all the address decoders in the first and second configurations.

10. The memory device of claim 7, further including: a data input/output circuit that provides one read only data path between different sections and a first read only port- in a first configuration, and provides read only data paths from different sections to corresponding different read only ports in a second configuration.

11. The memory device of claim 1 , further including: an arbitration circuit that arbitrates between simultaneous read accesses at multiple read only ports to allow only one read only port to access the entries at given time.

12. The memory device of claim 1, further including: at least one of the read-only ports being coupled to an electronic device; and the at least one read/write port is coupled to a processor that provides data to the electronic device.

13. A memory device, comprising: a storage area having a plurality of storage locations; a plurality of read only ports that provide read data from a storage circuit independently of one another; one read/write port that provides read data from the storage circuit and is coupled to the storage area by a write data path that writes data into the storage locations; and a power supply input corresponding to each read only port and the one read/write port, each power supply input being coupled to a common power supply node of the storage area by a separate power supply path.

14. The memory device of claim 12, further including: each read only port comprises a serial port that receives data signals in serial.

15. The memory device of claim 12, wherein: each serial port includes a clock input and a serial data input/output (I/O).

16. The memory device of claim 15, wherein: the memory device is an integrated circuit formed in a circuit package having a plurality of external terminals arranged in to groups of adjacent terminals corresponding to each read only port, each group of adjacent terminals including a clock terminal coupled to the clock input of the corresponding read only port, a data terminal coupled to the serial data I/O of the corresponding read only port, and a power supply terminal coupled to the power supply input of the corresponding port.

17. The memory device of claim 13, wherein: each power supply path comprises at least one diode.

18. The memory device of claim 17, wherein: each power supply path is coupled between its respective power supply input and a common intermediate node; and at least one diode coupled between the intermediate node and the common power supply node.

19. A method of providing data values in a memory device, comprising the steps of: providing data storage values in multiple sections; providing read only paths between each section and a corresponding read only port; and providing a read and write data path between all sections and a read/write port.

20. The method of claim 17, further including: providing a read only path between multiple sections and a single read only port according to a configuration setting.