WO2008002581A3 - Multi-port memory device and method - Google Patents

Multi-port memory device and method Download PDF

Info

Publication number
WO2008002581A3
WO2008002581A3 PCT/US2007/014839 US2007014839W WO2008002581A3 WO 2008002581 A3 WO2008002581 A3 WO 2008002581A3 US 2007014839 W US2007014839 W US 2007014839W WO 2008002581 A3 WO2008002581 A3 WO 2008002581A3
Authority
WO
WIPO (PCT)
Prior art keywords
entries
read
data values
storage
memory device
Prior art date
Application number
PCT/US2007/014839
Other languages
French (fr)
Other versions
WO2008002581A2 (en
Inventor
Gopal K Garg
Eric Gross
Original Assignee
Cypress Semiconductor Corp
Gopal K Garg
Eric Gross
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cypress Semiconductor Corp, Gopal K Garg, Eric Gross filed Critical Cypress Semiconductor Corp
Publication of WO2008002581A2 publication Critical patent/WO2008002581A2/en
Publication of WO2008002581A3 publication Critical patent/WO2008002581A3/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/10Decoders
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/16Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A memory device can include a plurality of memory cells arranged into entries that store data values accessible by an applied address. A plurality of read only ports can each applying a read address value corresponding to a different group of entries and receive read data values stored in the group of entries. The read only ports do not apply data values for storage in the group of entries. The memory device can also include at least one read/write port, different from the read only ports, that applies address values corresponding all storage entries and receiving data values stored in the storage entries as read data values, and applying data values for storage in the entries as write data values.
PCT/US2007/014839 2006-06-26 2007-06-25 Multi-port memory device and method WO2008002581A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US47462906A 2006-06-26 2006-06-26
US11/474,629 2006-06-26

Publications (2)

Publication Number Publication Date
WO2008002581A2 WO2008002581A2 (en) 2008-01-03
WO2008002581A3 true WO2008002581A3 (en) 2008-12-04

Family

ID=38846274

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/014839 WO2008002581A2 (en) 2006-06-26 2007-06-25 Multi-port memory device and method

Country Status (1)

Country Link
WO (1) WO2008002581A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11030128B2 (en) 2019-08-05 2021-06-08 Cypress Semiconductor Corporation Multi-ported nonvolatile memory device with bank allocation and related systems and methods

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3961324A (en) * 1974-03-13 1976-06-01 Compagnie Industrielle Des Telecommunications Cit-Alcatel Multiple receiver screen type picture displaying device
US4704697A (en) * 1985-06-17 1987-11-03 Counterpoint Computers Multiple station video memory
US6058039A (en) * 1995-01-11 2000-05-02 Hitachi, Ltd. Memory package and hot-line insertion/removal method using time constant based on-off switching
US6559826B1 (en) * 1998-11-06 2003-05-06 Silicon Graphics, Inc. Method for modeling and updating a colorimetric reference profile for a flat panel display
US20050219147A1 (en) * 2004-03-25 2005-10-06 Pioneer Plasma Display Corporation Display device, display support program and display support method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3961324A (en) * 1974-03-13 1976-06-01 Compagnie Industrielle Des Telecommunications Cit-Alcatel Multiple receiver screen type picture displaying device
US4704697A (en) * 1985-06-17 1987-11-03 Counterpoint Computers Multiple station video memory
US6058039A (en) * 1995-01-11 2000-05-02 Hitachi, Ltd. Memory package and hot-line insertion/removal method using time constant based on-off switching
US6559826B1 (en) * 1998-11-06 2003-05-06 Silicon Graphics, Inc. Method for modeling and updating a colorimetric reference profile for a flat panel display
US20050219147A1 (en) * 2004-03-25 2005-10-06 Pioneer Plasma Display Corporation Display device, display support program and display support method

Also Published As

Publication number Publication date
WO2008002581A2 (en) 2008-01-03

Similar Documents

Publication Publication Date Title
WO2011034673A3 (en) Memory device and method
EP1916665A3 (en) Combined read/write circuit for memory
WO2011130013A3 (en) Multi-port memory having a variable number of used write ports
WO2008098363A8 (en) Non-volatile memory with dynamic multi-mode operation
WO2012094481A3 (en) Memory address translation
WO2010045000A3 (en) Hot memory block table in a solid state storage device
WO2009097677A8 (en) Non-volatile memory device having configurable page size
WO2009044904A3 (en) Semiconductor memory device
WO2007076378A3 (en) Dual mode access for non-volatile storage devices
WO2013028434A3 (en) Memory device readout using multiple sense times
WO2008111058A3 (en) Adaptive estimation of memory cell read thresholds
TW200638425A (en) Nonvolatile memory devices that support virtual page storage using odd-state memory cells and methods of programming same
WO2009089612A8 (en) Nonvolatile semiconductor memory device
WO2009035505A3 (en) Storing operational information in an array of memory cells
WO2011048522A3 (en) Neighborhood operations for parallel processing
GB2472952A (en) Dynamic pass voltage
TW200615969A (en) Method and system for providing independent bank refresh for volatile memories
WO2006031551A3 (en) Selective replication of data structure
WO2005074613A3 (en) Method for testing and programming memory devices and system for same
WO2009052371A3 (en) Ground level precharge bit line scheme for read operation in spin transfer torque magnetoresistive random access memory
WO2007015773A3 (en) Memory device and method having multiple address, data and command buses
WO2007132452A3 (en) Reducing programming error in memory devices
TW200737182A (en) High-bandwidth magnetoresistive random access memory devices and methods of operation thereof
WO2010062655A3 (en) Error correction in multiple semiconductor memory units
WO2011062825A3 (en) Bit-replacement technique for dram error correction

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07796463

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

NENP Non-entry into the national phase

Ref country code: RU

122 Ep: pct application non-entry in european phase

Ref document number: 07796463

Country of ref document: EP

Kind code of ref document: A2