1287801 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種具有位址轉換功能之記憶體模 組及記憶體控制方法，尤指一種應用於具有缺損之記憶 體（Random Access Memory，DRAM)單元，存取並整合記 憶體位址之具有位址轉換功能之記憶體模組及記憶體 控制方法。 【先前技術】 請參照第1A圖所示，其為習知技術中一記憶單位 110之示意圖，一記憶體單元是由複數個此記憶單位 (cel 1)110所構成，每一記憶單位11〇結構包含：一資 料電容111、一啟動列線（Co 1 umn ) 112、一讀寫行線 (Row ) 113以及一電晶體114，其中該資料電容1 u係 用以儲存一位元（b i t )資料’該啟動列線112係用以 控制該資料電容111開關，該讀寫行線113係用以進行 資料讀寫，上述控制以及資料讀寫係利用該電晶體1丄4 之元件特性實現。因此，常見之記憶單位11〇具有上述 元件的結構’目前構成記憶單元1 1 〇中所用的電晶體， 大部分是η通道的金氧半導體場效電晶體（nM〇s)。 請參照第1B圖，其為一記憶矩陣（BANK )示意圖， 進一步地，一記憶體單元1 〇〇利用該等記憶單位丨丨〇形 成至少一記憶矩陣12 〇，指定一個行（R〇w )，再指定一 個列（Column)，即可準確地定位該等記憶單位11〇。 此種記憶矩陣即為該記憶體單元1〇()進行資料控制之 基本原理’該等§己憶矩陣120稱為一陣列（bank)。 基於技術、成本等原因，更重要地，由於記憶體的 工作原理限制，如一記憶體單元僅具有單一之記憶矩 陣，將會造成非常嚴重的定址冑突，使得記憶體單元工 作效率大幅降低，於是，習知之記憶體單元通常包含複 TP050242 5 1287801 數個記憶矩陣，請參見第1C圖，其為一雙倍數數據傳輸率 (double-data-rate，DDR )記憶體單元13 0，該記憶體單元 130包含四個該等記憶矩陣120，而在DDR-Π的標準 中，該等記憶矩陣120的數量甚至提高到了 8個。 因此，進行記憶體存取控制時，必須先確定系統所 欲存取之指定記憶矩陣120，其後再於指定之記憶矩陣 '中控制相應之讀寫行線113 ( Row )與啟動列線112 *( Column)進行定址。由此可知，系統每次透過一控制 通道（例如北橋通道）交換之資料即為記憶矩陣存儲陣 列中一個“存儲單元”的容量。 > 而市面上常見之標準記憶體模組通常包含複數個 記憶體，該記憶體模組總容量可依需要配置，但受限於 該記憶體模組和系統間所設定之通道寬度，以PC標準 為例，上述通道即為該記憶體模組以及北橋晶片之間用 來交換資料的通道，舉例來說，系統與記憶體之間（即 系統到DIMM槽）的通道位寬是6 4位元，這意味著系 統一次會向該記憶體模組傳送或從讀取64位元之資 料，此一 64位元之資料集合，通常稱之為一存取通道 寬度。記憶體一次傳輸率的資料量係為該記憶體單元之 • 通道寬度，亦即該記憶體模組所使用之記憶體個數，其 通道寬度總和需該存取通道之通道寬度相等，其中該等 -記憶體可分佈於記憶體模組之單一面或雙面，該存取通 道不限於特定個數與位元數。 總結來說’一記憶體模組包含複數個記憶體單元， 母一該兄憶體單元包含複數個記憶矩陣，每一該複數記 憶矩陣具有複數記憶單位（Ce丨丨），其中系統藉由至少 一存取通道存取該記憶體模組資料。上述之存取動作透 過存取指定之該等記憶矩陣實現。 如欲以上述方法進行記憶體模組存取控制，該記憶 TP050242 6 1287801 體單元之任一該等記憶矩陣均需能正常工作，只要該記 憶體單元之任一該等記憶矩陣出現損壞或不能正常運 作情形，該記憶體單元即視為廢品，無法被販賣和利 用，在今日記憶體以及$己憶體模組製造以及銷售利潤曰 - 趨減少的情形下，上述廢品的出現使得廠商必須承受相 . 當的額外成本。 職事之故，本案發明人為解決上述問題而提出一個 ^ 得以整合複數個具有缺損記憶矩陣之記憶體進行資料 存取並建構為一完整記憶體模組的方法。 【發明内容】 * 本發明之主要目的係提供一種記憶體控制方法， 利用轉換來自系統之記憶矩陣存取信號，實現習知無 法使用之記憶體單元之再利用。 … 、 本發明之另一目的係提供一種記憶體控制方法， 透過對來自系統之記憶矩陣存取位置之判斷與轉換， 整合至少兩習知無法使用之記憶體單元為一可工作記 憶體單元。 ° 本發明之另一目的係提供一種具有位址轉換功能 之記憶體模組，包含一系統存取信號轉換電路，接收 # 來自系統之記憶矩陣存取信號，判斷並轉換存取信號 之存取位址至所指定之該等記憶體單元以完成資料存 取。 為實現上述目的，本發明提供一種具有位址轉換 " 功能之記憶體模組，包含： 、 一記憶體模組基板； 一資料通道，設置於該基板上，與至少一系統介 面電連接’並可接收該系統之記憶體存取信號； 複數個第一類記憶體單元，設置於該基板之一面 上且各第一類記憶體單元包含複數個第一類記憶矩陣，其 TP050242 7 1287801 中至少一該等第一類記憶矩陣係正常工作； 複數個第二類記憶體單元，設置於該基板之另一 面上，且各第二類$己憶體早兀包含複數個第二類記憶矩 • 陣，其中至少一該等第二類資料矩陣係正常工作，該 等第二類記憶體單元與該等第一類記憶體單元係可整 合為一完整記憶單元； • 一系統存取信號轉換電路，分別與該資料通道、 、 該等第一類記憶體單元以及該等第二類記憶體單元電 連接，並接收該記憶體存取彳§號’用以決定該信號之 存取位址轉換至對應之該等第一類記憶體單元或該等 籲 第二類記憶體單元之一指定記憶矩陣並驅動該記憶矩 陣。 一具體例中，本發明之記憶體模組之該等第一類 以及第二類記憶矩陣包含下列位址狀態：ΒΑ1 = 〇、 ΒΑ1 = 1、ΒΑ0 = 0、BA0 = 1、BA1=BA0 以及 BA1 = !BA0 之一 者。 另一具體例中，本發明之記憶體模組之該等第一 類以及第二類記憶矩陣之位址狀態係為下列組合之一 者：BA1 = 0正常與BA1 = 1正常、BA1 = 1正常與ΒΑ1 = 〇正 0 常、BA0 = 0正常與BA0 = 1正常、BA0 = 1正常與BA0 = 1正 常、BA1=BA0正常與BA1 = !BA0正常、BA1 = !BA0正常與 . BA1=BA0 正常。 ’、 又另一具體例中，本發明之記憶體模組之該等第 一類及第二類記憶體單元各分別具有2n個記憶矩陣， 其中η為正整數。例如該等第一類及第二類記憶體單 70各分別具有4或8個記憶矩陣。 本發明又提供一種記憶體控制方法，包含下列步驟： (a)以刖述疋義之具有位址轉換功能之記憶體模 組讀取一系統存取信號； TP050242 1287801 (b) 判斷欲存取之該記憶單元； (c) 判斷該存取信號所欲存取之一記憶矩陣； (d) 使該存取信號之存取位址轉換至所決定之記 憶矩陣； (6 ) 驅動對應於該決定之記憶矩陣之至少—記憶 體單元以存取該指定記憶矩陣。 依據本發明之記憶體控制方法，該系統存取信號 係來自一個人電腦架構系統，並透過一介面例如北橋 介面傳送至該記憶體。 依據本發明之記憶體控制方法，其中該步驟（c ) 係基於記憶體單元位置加以判斷且該記憶體係位於一 記憶模組基板之任一面者。 本發明將藉由下述之實施方式更進一步加以閣 明。 【實施方式】 第2A圖所示為依據本發明較佳實施例之一具有 位址轉換功能之記憶體模組200，包含一記憶體模組 基板210、複數個第一類記憶體單元220、複數個第二 類記憶體單元230、一資料通道240以及一系統存^ 信號轉換電路250。其中該等第一類記憶體單元、 該等第一類記憶體早元230、該資料通道240以及兮 系統存取信號轉換電路250係設置於該記憶體模組^ 板210上，該系統存取信號轉換電路25〇之一端與二 資料通道240電連接，另一端分別與該等第一類ϋ 體模組220以及該等第二類記憶體模組230電連接。 每一該等第一類記憶體單元220以及每一該等第二J 記憶體單元230各至少包含4個記憶矩降。 該等記憶矩陣係透過ΒΑ0以及ΒΑ1兩位址線執Γ 定址工作，請參照第2Β圖，其為位址線及其對應之纪 9 ΤΡ050242 (s 1287801 憶矩陣示意圖，記憶矩陣可利用位址線之數值對應而 定義為：當ΒΑ0=0，BA1=0時，定義為ΒΑΝΚ0;當 BA0=0，BA1 = 1 時，定義為 BANK1;當 BA0=1，BA1=0 時，定義為 BANK2;當 BA0 = 1，BA1 = 1 時，定義為 BANK3。其中ΒΑΝΚ0以及BANK1被定義為第一類記 憶矩陣260，BANK2以及BANK3被定義為第二類記 憶矩陣270，該等第一類記憶體單元220中，該第一 類記憶矩陣260之工作狀況正常，而第二類記憶矩陣 270缺損。該等第二類記憶體單元230中，該第二類 記憶矩陣270之工作狀況正常，而第一類記憶矩陣260 缺損。 本實施例中，係於該記憶體模組之一面設置複數 個該等第一類記憶體單元220,於另一面設置相等數 量之第二類記憶體單元230,每一該等第一類記憶體 單元220以及第二類記憶體單元230係成對配置，該 第一類記憶體單元220具有一正常工作之第一類記憶 矩陣260，該第二類記憶體單元230具有與該第一類 記憶矩陣260互補之該第二類記憶矩陣270，以此， 該第一類記憶體單元220與該第二類記憶體單元230 之組合得以整合為一具有正常功能之整合式記憶體單 元，亦即一該第一類記憶體單元220與相對應之另一 該第二類記憶體單元230可視為一整合記憶體單元， 換言之，該整合式記憶體單元至少包含工作狀態正常 之記憶矩陣ΒΑΝΚ0、BANK1、BANK2以及BANK3，得以 執行一正常記憶體矩陣之功能，其中該等第一類記憶 體單元220與該第二類記憶體單元230可於該基板210 之兩面互換，亦即該等記憶單元可分別位於該記憶體 模組基板210之正面或是背面，均不影響該整合記憶 單元之功能。值得一提的是，該第一類記憶矩陣260 TP050242 10 1287801 以及該第二類記憶矩陣270係以位址線之操作定義， 不得視為本發明之限制，舉例而言，亦可定義ΒΑΝΚ0 以及BANK2為一類，BANK1以及BANK3為一類。 - 請參照第2C圖，該記憶體模組200之工作原理如 下：首先該系統存取信號轉換電路250經由該資料通 道240，接收來自系統之一存取信號，該系統存取信 • 號轉換電路250讀取存取信號中所包含之驅動位址資 、 料並進行位址轉換，舉例來說，當該存取信號欲操作 記憶矩陣ΒΑΝΚ0以及BANK1時，該系統存取信號轉換 電路250轉換存取位址至該第一類記憶矩陣260正常 • 之該等第一類記憶單元220並驅動之，當該存取信號 操作記憶矩陣BANK2以及BANK3時，該系統存取信號 轉換電路250轉換存取位址至該第二類記憶矩陣270 正常之該等第二類記憶體單元230並驅動之。另外， §系統要求對記憶體模組進行致動（Active)、讀取 (Read)、寫入（Write)等動作時，該系統存取信號 轉換電路250需判斷欲進行存取之該等記憶矩陣以驅 動位於該基板210上之該等記憶體單元22〇或230， 當系統要求對該記憶體模組2 0 0進行前置充能 • ( Precharge)時，如該等記憶矩陣内之一位址a1〇之 位準為低（Low) ’則該系統存取信號轉換電路250判 - 斷欲進行存取之該等記憶矩陣以驅動位於該基板210 上之該等記憶體單元220或230進行充能（charge)， 但亦不以此為限。值得注意的是，本實施例中所述， 來自系統的該存取信號實際上包含但不限於存取記憶 矩陣的la號’而為系統控制記憶體模組所需之所有相 關信號，亦即本發明對於存取信號的處理並不限於轉 址’亦應均等至對該存取信號的處理。 以此，本發明亦揭露一記憶體控制方法，請參照 TP050242 11 1287801 第3圖，係為本發明揭露之記憶體控制方法方塊圖， 首先本發明之記憶體模組自一系統存取信號’讀取該 系統存取信號，隨後判斷欲存取之記憶體單元位址， 例如係位於該記憶體模組基板之正面或反面’接著判 斷該存取信號所欲存取之記憶矩陣，最後，轉換該存 ' 取信號之存取位址以驅動對應該指定記憶矩陣之至少 ， 一記憶體單元（第一類記憶矩陣或第二類記憶矩陣）以 、 存取該指定記憶矩陣。 依據本發明之3己憶體控制方法’其中該系統存取 信號係來自一個人電腦架構系統，並透過一北橋介面 _ 傳送至該記憶體。 依據本發明之記憶體控制方法，其中該判斷該存 取信號所欲存取之記憶矩陣之步驟係基於記憶體單元 位置加以判斷且該記憶體係位於一記憶模組基板之任 一面者0 依據本發明之記憶體控制方法，其中該記憶體單 元為一雙倍數數據傳輸率記憶體。 本發明係利用記憶體模組之位址組合與判斷方 法，整合具有缺損之記憶體單元為可正常工作之記憶 φ 體模組，於此粉神下，本發明應存在但不限於具有下 述變化實施可能： - 首先’本發明不應侷限於一特定記憶矩陣數目之 記憶單元的應用，隨著技術演進，具有八個、十六個 5己憶矩陣之記憶早元亦可應用於本發明，僅需維持總 數之對等，例如在具有4個記憶矩陣之記憶單元的架 構下，一具有3個工作正常記憶矩陣之記憶單元可與 另一具有1個工作正常矩陣之記憶單元進行整合，或 者，在具有8個記憶矩陣之記憶單元的架構下，一具 有5個工作正常記憶矩陣之記憶單元可與另一具有3 ΤΡ050242 121287801 IX. Description of the Invention: [Technical Field] The present invention relates to a memory module and a memory control method having an address conversion function, and more particularly to a memory (Random Access Memory, DRAM) having a defect. a unit, a memory module having an address translation function and a memory control method for accessing and integrating a memory address. [Prior Art] Please refer to FIG. 1A, which is a schematic diagram of a memory unit 110 in the prior art. A memory unit is composed of a plurality of memory units (cel 1) 110, each memory unit 11 The structure comprises: a data capacitor 111, a start column line (Co 1 umn ) 112, a read and write line line (Row ) 113 and a transistor 114, wherein the data capacitor 1 u is used for storing a bit (bit) The data 'the start line 112 is used to control the data capacitor 111 switch, and the read and write line 113 is used for reading and writing data. The above control and data read and write are realized by the component characteristics of the transistor 1丄4. Therefore, the conventional memory unit 11 〇 has the structure of the above-mentioned elements 'currently constitutes the transistor used in the memory unit 1 1 ,, and most of them are η-channel MOS field-effect transistors (nM〇s). Please refer to FIG. 1B , which is a schematic diagram of a memory matrix (BANK ). Further, a memory unit 1 〇〇 forms at least one memory matrix 12 〇〇 by using the memory units 〇, and specifies a row (R〇w ). , then specify a column (Column), you can accurately locate these memory units 11 〇. Such a memory matrix is the basic principle of data control for the memory unit 1 〇 (). The § recall matrix 120 is called a bank. For reasons of technology, cost, etc., more importantly, due to the limitation of the working principle of the memory, such as a memory unit having only a single memory matrix, it will cause very severe addressing conflicts, which greatly reduces the efficiency of the memory unit. The conventional memory unit usually includes a plurality of memory matrices of TP050242 5 1287801. Please refer to FIG. 1C, which is a double-data-rate (DDR) memory unit 130, the memory. Unit 130 contains four such memory matrices 120, and in the DDR-Π standard, the number of such memory matrices 120 is even increased to eight. Therefore, when performing memory access control, it is necessary to first determine the specified memory matrix 120 to be accessed by the system, and then control the corresponding read and write row line 113 (row) and the enable column line 112 in the specified memory matrix ' * ( Column) for addressing. It can be seen that the data exchanged by the system through a control channel (for example, the north bridge channel) is the capacity of a "storage unit" in the memory matrix storage array. > The standard memory module commonly used in the market usually includes a plurality of memory, the total capacity of the memory module can be configured as needed, but limited by the channel width set between the memory module and the system, For example, in the PC standard, the channel is a channel for exchanging data between the memory module and the north bridge chip. For example, the channel width between the system and the memory (ie, the system to the DIMM slot) is 6 4 . Bit, which means that the system will transfer or read 64-bit data to the memory module at a time. This 64-bit data set is usually called an access channel width. The data volume of the primary transfer rate of the memory is the channel width of the memory cell, that is, the number of memory cells used by the memory module, and the sum of the channel widths is equal to the channel width of the access channel, where The equal-memory can be distributed on a single side or both sides of the memory module, and the access channel is not limited to a specific number and number of bits. In summary, a memory module includes a plurality of memory cells, and the parent memory unit includes a plurality of memory matrices, each of the complex memory matrices having a complex memory unit (Ce丨丨), wherein the system is at least An access channel accesses the memory module data. The above described access actions are implemented by accessing the specified memory matrices. If the memory module access control is to be performed by the above method, any of the memory matrices of the memory unit TP050242 6 1287801 need to be able to work normally, as long as any of the memory matrices of the memory unit are damaged or cannot be In normal operation, the memory unit is regarded as a waste product and cannot be sold and utilized. In the case of today's memory and the manufacturing and sales profit of the memory module, the occurrence of the above-mentioned waste products makes the manufacturer must bear Phase. When the extra cost. In order to solve the above problems, the inventor of the present invention proposed a method for integrating a plurality of memories with a memory matrix for data access and constructing a complete memory module. SUMMARY OF THE INVENTION The main object of the present invention is to provide a memory control method for realizing reuse of a memory unit that is conventionally unusable by converting a memory matrix access signal from a system. Another object of the present invention is to provide a memory control method for integrating at least two memory units that are not known to be usable as a workable memory unit by judging and converting the access position of the memory matrix from the system. Another object of the present invention is to provide a memory module having an address conversion function, comprising a system access signal conversion circuit, receiving a memory matrix access signal from the system, and determining and converting access signals. The address is addressed to the specified memory unit to complete the data access. To achieve the above object, the present invention provides a memory module having an address conversion function, comprising: a memory module substrate; a data channel disposed on the substrate and electrically connected to at least one system interface' And receiving a memory access signal of the system; a plurality of first type memory units disposed on one side of the substrate and each of the first type of memory units includes a plurality of first type memory matrices, in TP050242 7 1287801 At least one of the first types of memory matrices works normally; a plurality of second type of memory cells are disposed on the other side of the substrate, and each of the second type of memory has a plurality of second types of memory moments • array, wherein at least one of the second type of data matrices is functional, the second type of memory unit and the first type of memory unit can be integrated into a complete memory unit; • a system access signal conversion a circuit electrically connected to the data channel, the first type of memory unit, and the second type of memory unit, and receiving the memory access 彳§' for determining Access address signals corresponding to the transition to the plurality of first type memory unit or a second type of such Calls one memory cell array and driving the specified memory matrix memory. In a specific example, the first and second types of memory matrices of the memory module of the present invention include the following address states: ΒΑ1 = 〇, ΒΑ1 = 1, ΒΑ0 = 0, BA0 = 1, BA1=BA0, and One of BA1 = !BA0. In another specific example, the address states of the first and second types of memory matrices of the memory module of the present invention are one of the following combinations: BA1 = 0 normal and BA1 = 1 normal, BA1 = 1 Normal and ΒΑ1 = 〇 positive 0, BA0 = 0 normal and BA0 = 1 normal, BA0 = 1 normal and BA0 = 1 normal, BA1 = BA0 normal and BA1 = !BA0 normal, BA1 = !BA0 normal and . BA1=BA0 normal. In still another specific example, the first and second types of memory cells of the memory module of the present invention each have 2n memory matrices, wherein n is a positive integer. For example, the first and second types of memory cells 70 each have 4 or 8 memory matrices. The invention further provides a memory control method, comprising the following steps: (a) reading a system access signal by a memory module having an address conversion function; TP050242 1287801 (b) determining that the system is to be accessed a memory unit; (c) determining a memory matrix to which the access signal is to be accessed; (d) converting an access address of the access signal to the determined memory matrix; (6) driving corresponding to the decision At least a memory unit of the memory matrix to access the specified memory matrix. According to the memory control method of the present invention, the system access signal is from a personal computer architecture system and transmitted to the memory through an interface such as a north bridge interface. According to the memory control method of the present invention, the step (c) is judged based on the position of the memory unit and the memory system is located on either side of a memory module substrate. The invention will be further illustrated by the following embodiments. [Embodiment] FIG. 2A shows a memory module 200 having an address conversion function according to a preferred embodiment of the present invention, including a memory module substrate 210, a plurality of first type memory units 220, A plurality of second type memory cells 230, a data channel 240, and a system memory signal conversion circuit 250. The first type of memory unit, the first type of memory early 230, the data channel 240, and the system access signal conversion circuit 250 are disposed on the memory module board 210, and the system stores One end of the signal conversion circuit 25 is electrically connected to the two data channels 240, and the other end is electrically connected to the first type of body module 220 and the second type of memory module 230, respectively. Each of the first type of memory cells 220 and each of the second J memory cells 230 each include at least four memory moment drops. These memory matrices are assigned to address by ΒΑ0 and ΒΑ1 two-bit lines. Please refer to Figure 2, which is the address line and its corresponding period 9 ΤΡ 050242 (s 1287801 recall matrix diagram, memory matrix can use address line The corresponding value is defined as: when ΒΑ0=0, BA1=0, it is defined as ΒΑΝΚ0; when BA0=0, BA1=1, it is defined as BANK1; when BA0=1, BA1=0, it is defined as BANK2; BA0 = 1, BA1 = 1, defined as BANK3, where ΒΑΝΚ0 and BANK1 are defined as the first type of memory matrix 260, BANK2 and BANK3 are defined as the second type of memory matrix 270, the first type of memory unit 220 The working memory of the first type of memory matrix 260 is normal, and the second type of memory matrix 270 is defective. In the second type of memory unit 230, the working memory of the second type of memory matrix 270 is normal, and the first type of memory The matrix 260 is defective. In this embodiment, a plurality of the first type of memory units 220 are disposed on one side of the memory module, and an equal number of second type memory units 230 are disposed on the other side, each of the same The first type of memory unit 220 and the first The memory-like memory unit 230 is configured in pairs. The first-type memory unit 220 has a first-class memory matrix 260 that operates normally. The second-type memory unit 230 has a complementary memory to the first-type memory matrix 260. The second type of memory matrix 270, whereby the combination of the first type of memory unit 220 and the second type of memory unit 230 is integrated into a normal function integrated memory unit, that is, the first type The memory unit 220 and the corresponding other second type memory unit 230 can be regarded as an integrated memory unit. In other words, the integrated memory unit includes at least a memory matrix ΒΑΝΚ0, BANK1, BANK2, and BANK3 with normal working states. The function of a normal memory matrix is performed, wherein the first type of memory unit 220 and the second type of memory unit 230 are interchangeable on both sides of the substrate 210, that is, the memory units can be respectively located in the memory The front or back of the module substrate 210 does not affect the function of the integrated memory unit. It is worth mentioning that the first type of memory matrix 260 TP050242 10 1287801 And the second type of memory matrix 270 is defined by the operation of the address line, and should not be regarded as a limitation of the present invention. For example, ΒΑΝΚ0 and BANK2 may be defined as one type, and BANK1 and BANK3 are one type. - Please refer to FIG. 2C The working principle of the memory module 200 is as follows: First, the system access signal conversion circuit 250 receives an access signal from one of the systems via the data channel 240, and the system accesses the signal conversion circuit 250 to read and access. The drive address information and the address conversion included in the signal, for example, when the access signal is to operate the memory matrix ΒΑΝΚ0 and BANK1, the system access signal conversion circuit 250 converts the access address to the The first type of memory matrix 260 is normally driven by the first type of memory cells 220. When the access signal operates the memory matrix BANK2 and BANK3, the system access signal conversion circuit 250 converts the access address to the first The second type of memory matrix 270 is normally driven by the second type of memory cells 230. In addition, when the system requires an action (Active), read (Read), write (Write) or the like on the memory module, the system access signal conversion circuit 250 needs to determine the memory to be accessed. The matrix drives the memory cells 22 or 230 on the substrate 210. When the system requires precharge of the memory module 200, such as one of the memory matrices The address of the address a1 is low (Low), and the system access signal conversion circuit 250 determines that the memory matrix to be accessed is driven to drive the memory cells 220 or 230 located on the substrate 210. Charge, but not limited to this. It should be noted that, in the embodiment, the access signal from the system actually includes, but is not limited to, the access number of the memory matrix, and all the related signals required by the system to control the memory module, that is, The process of the present invention for accessing signals is not limited to addressing 'and should be equal to the processing of the access signal. Therefore, the present invention also discloses a memory control method. Please refer to FIG. TP050242 11 1287801. FIG. 3 is a block diagram of a memory control method according to the present invention. First, the memory module of the present invention accesses a signal from a system. Reading the system access signal, and then determining the memory unit address to be accessed, for example, on the front or back side of the memory module substrate, and then determining the memory matrix to be accessed by the access signal. Finally, Converting the access address of the stored signal to drive at least one memory unit (the first type of memory matrix or the second type of memory matrix) corresponding to the specified memory matrix to access the specified memory matrix. According to the present invention, the system of access control signals is derived from a personal computer architecture system and transmitted to the memory through a north bridge interface. According to the memory control method of the present invention, the step of determining the memory matrix to be accessed by the access signal is determined based on the location of the memory unit and the memory system is located on either side of a memory module substrate. The memory control method of the invention, wherein the memory unit is a double data transmission rate memory. The invention utilizes the address combination and judgment method of the memory module, and integrates the memory unit with the defect into a memory φ body module which can work normally. Under the powder, the present invention should exist but not limited to the following The implementation of the change may be: - Firstly, the invention should not be limited to the application of a memory unit of a specific number of memory matrices, and as the technology evolves, memory early elements with eight, sixteen, five recall matrices can also be applied to the present invention. It is only necessary to maintain the total number of peers. For example, in the architecture of a memory unit having four memory matrices, a memory unit having three working memory matrices can be integrated with another memory unit having a working normal matrix. Alternatively, in the architecture of a memory unit having 8 memory matrices, a memory unit having 5 working normal memory matrices may be associated with another having 3 ΤΡ050242 12
1287801 個工作正常矩陣之記憶單元進行整合，換言之，記憶 矩陣數目的變化不應成為本發明之限制。 另外，整合式記憶單元應以記憶單元間之互補為 原則，舉例來說，一 BANK0以及BANK1記憶矩陣正常 工作之記憶單元應與另一 BANK2以及BNAK3記憶矩陣 正常工作之記憶單元整合，或者一 BANK0以及BANK2 記憶矩陣正常工作之記憶單元則應與另一 BANK1以及 BANK3記憶矩陣正常工作之記憶單元整合，而其反 (Not )組合，亦應被視為已為本發明所揭露。 再者，一個包含一整合記憶體單元以及一系統存 取、號轉換電路之板組’即可視為一具有完整功能之 記憶體模組。 進而，本發明又有關一種電腦系統，其包含：一 電源’供應該電腦系統工作所需；一處理器，處理該 電腦系統之輸出以及輸入之資料運算；至少一本發明 W述定義之具有位址轉換功能之記憶體模組；複數個 輸入裝置’用以接收外界指令並傳送至該處理器處 理；以及複數個輸出裝置，用以轉換由處理器輸出之 信號為指定形式。 熟知此項技術人士應瞭解上述圖式及說明中所示 之本發明具體實施例只是範例性且非限制。 本發明較佳具體實施例的前述說明係用於示範及 說明目的，其非限制本發明於該等具體實施例。具體 實施例之選擇及描述是為了更佳解釋本發明的原理及 其實際應用之最㈣式，#而允冑熟習此項技術人士 理解用於各種具體實_之本發明，且具有適合於特 定使用或所涵蓋實作之各種修改。 【圖式簡單說明】 第1A圖為習知技術之一記憶單位之示意圖。 TP050242 13 1287801 第1B圖為一記憶矩陣（BANK)示意圖。 第1C圖為一雙倍數數據傳輸率（double-data-rate，DDR )記 憶體單元。 第2A圖為依據本發明較佳實施例之一具有位址轉換 功能之記憶體模組。 第2B圖為位址線及其對應之記憶矩陣示意圖。 第2C圖為第2A圖所示之記憶體模組之工作原理方塊 圖01287801 memory cells working in a normal matrix are integrated, in other words, variations in the number of memory matrices should not be a limitation of the present invention. In addition, the integrated memory unit should be based on the complementarity between memory cells. For example, a memory cell in which BANK0 and BANK1 memory matrices work normally should be integrated with another BANK2 and BNAK3 memory matrix working memory unit, or a BANK0. And the memory unit in which the BANK2 memory matrix works normally should be integrated with the memory unit of another BANK1 and BANK3 memory matrix, and the reverse (Not) combination should also be regarded as having been disclosed. Furthermore, a board group comprising an integrated memory unit and a system access and number conversion circuit can be regarded as a fully functional memory module. Furthermore, the present invention relates to a computer system comprising: a power source for supplying the computer system for operation; a processor for processing the output of the computer system and inputting data operations; at least one of the inventions has a bit defined a memory module of the address translation function; a plurality of input devices 'for receiving external commands and transmitting to the processor for processing; and a plurality of output devices for converting signals output by the processor into a specified form. It will be apparent to those skilled in the art that the specific embodiments of the present invention shown in the drawings and description are only illustrative and not limiting. The foregoing description of the preferred embodiments of the invention are intended to The selection and description of the specific embodiments are intended to better explain the principles of the present invention and the practical application of the invention, and the skilled artisan understands that the present invention is applicable to various specific embodiments and is suitable for a particular Various modifications to use or cover the implementation. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a schematic diagram of one of the memory units of the prior art. TP050242 13 1287801 Figure 1B is a schematic diagram of a memory matrix (BANK). Figure 1C shows a double-data-rate (DDR) memory unit. Figure 2A is a diagram of a memory module having an address translation function in accordance with a preferred embodiment of the present invention. Figure 2B is a schematic diagram of the address line and its corresponding memory matrix. Figure 2C shows the working principle of the memory module shown in Figure 2A. Figure 0
第3圖為本發明之記憶體控制方法方塊圖。 【主要元件符號說明】 100 記憶體單元 110 記憶單位 111 資料電容 112 啟動列線（Column) 113 讀寫行線（Row) 114 電晶體 120 記憶矩陣 130 記憶體單元 200 記憶體模組 210 基板 220 第一類記憶體單元 230 第二類記憶體單元 240 資料通道 250 系 260 第 270 第 統存取信號轉換電路 一類記憶矩陣 二類記憶矩陣 TP050242Figure 3 is a block diagram of a memory control method of the present invention. [Main component symbol description] 100 Memory unit 110 Memory unit 111 Data capacitor 112 Start column line (Column) 113 Read and write line line (Row) 114 Transistor 120 Memory matrix 130 Memory unit 200 Memory module 210 Substrate 220 A type of memory unit 230, a second type of memory unit 240, a data channel, a 250 system, a 260th system, an access signal conversion circuit, a memory matrix, a class II memory matrix, TP050242