WO2007148778A1

WO2007148778A1 - Memory controller, nonvolatile memory device, nonvolatile memory system, and memory control method

Info

Publication number: WO2007148778A1
Application number: PCT/JP2007/062569
Authority: WO
Inventors: Takashi Ogasawara; Daisuke Kunimune; Masahiro Nakanishi
Original assignee: Panasonic Corporation
Priority date: 2006-06-23
Filing date: 2007-06-22
Publication date: 2007-12-27
Also published as: JP2009205187A

Abstract

A program download unit (108) downloads, in accordance with a selecting instruction of a program selecting unit (105), a program to be executed by a memory interface unit (103), selectively from a nonvolatile memory (140). The download of the program is performed in parallel with the operation in a control unit (102), so that a time overhead can be made unnecessary for the download. In accordance with a command from a host (160), the necessary program is selected so that the unnecessary program need not be downloaded every time, thereby to realize a power economy. As a result, the operations of the interface unit on the nonvolatile memory can be made programmable thereby to correspond to a plurality of kinds of nonvolatile memories, to reduce the capacity of a program storing RAM and to realize a high-speed access and the power economy.

Description

Specification

MEMORY CONTROLLER, NONVOLATILE STORAGE DEVICE, NONVOLATILE STORAGE SYSTEM, AND MEMORY CONTROL METHOD

Technical field

The present invention relates to a nonvolatile memory device such as a semiconductor memory card including a nonvolatile memory such as a flash memory as a main memory, and a memory controller built in the nonvolatile memory device. Furthermore, a nonvolatile storage system in which an access device is added to the nonvolatile storage device as a constituent element, and a memory control method are also included.

Background

BACKGROUND [0003] Nonvolatile memory devices including a rewritable nonvolatile memory are in increasing demand mainly for semiconductor memory cards. Semiconductor memory cards are very expensive compared to optical discs and tape media, but due to their merits such as small size, light weight, earthquake resistance, and ease of handling, digital still cameras, video recording devices, etc. The demand is growing mainly for communication equipment such as AV equipment and mobile phones.

[0003] This nonvolatile storage device includes a flash memory as a nonvolatile main storage memory, and has a memory controller that controls the flash memory. The memory controller performs read / write control on the flash memory in response to read / write instructions from an access device such as a digital still camera body.

[0004] Accompanying the need for higher quality AV content recorded in such a nonvolatile storage device, flash memory capacity and cost have been rapidly increasing in recent years. Specifically, in order to reduce the area occupied by the peripheral circuit of the memory cell array with respect to the memory cell array built in the flash memory, the size of the physical block that is the erasing unit, for example, 256 kbytes or 512 kbytes is increasing year by year. It is coming.

[0005] Further, there is a method for increasing the amount of information that can be stored in one memory cell from 1 bit to multiple bits. As a non-volatile memory of a 1-bit memory cell, for example, there is a binary NAND flash memory, and as a typical multi-bit memory, there is a multi-value NAND flash memory. Multi-level NAND flash memory is less expensive than binary NAND flash memory On the other hand, it has disadvantages such as slow access speed or low reliability. For this reason, binary NAND flash memory is still used in applications that require high speed and high reliability, for example.

[0006] As a related technique, a function expansion method of a microcontroller as in Patent Document 1 is known.

Patent Document 1: Japanese Patent Application Laid-Open No. 2003-58377

Disclosure of the invention

Problems to be solved by the invention

In view of such a situation, there is a demand for a versatile memory controller that can handle various types of flash memories. However, because the control differs depending on the type of flash memory mounted on the semiconductor memory card, there was a problem that it was not possible to easily adapt to flash memory changes.

[0008] In view of the above problems, the present invention provides a memory controller, a nonvolatile storage device, and a nonvolatile storage system that can cope with a change in flash memory by selectively downloading a processing program of the memory interface unit. And a memory control method.

Means for solving the problem

[0009] In order to solve this problem, the memory controller of the present invention writes data to and reads data from a nonvolatile memory holding a plurality of programs in addition to user data. A non-volatile memory comprising a host interface unit that communicates with the outside and a program download unit that selectively downloads the program from the non-volatile memory in response to a program selection instruction; A memory interface unit that performs read / write control on the memory, and a program selection unit that instructs the memory interface unit to select a program necessary for read / write control of the memory interface unit, and controls the operation of each unit of the memory controller Controller section and the program Those comprising a RAM which holds a program downloaded, the by download unit.

[0010] In order to solve this problem, the nonvolatile memory device of the present invention is provided in addition to user data. A nonvolatile memory that holds a plurality of programs, and a memory controller that writes data to the nonvolatile memory and reads data from the nonvolatile memory, the memory The controller has a host interface unit that communicates with the outside, and a program download unit that selectively downloads the program from the nonvolatile memory in response to a program selection instruction, and performs read / write control to the nonvolatile memory A memory interface unit for controlling the memory interface unit, and a program selection unit for instructing the memory interface unit to select a program necessary for read / write control of the memory interface unit. The controller controls the operation of each unit of the memory controller. Nore part and the program Those comprising a RAM which holds a program downloaded, the by download unit.

Here, the program selection unit may select the program according to an operation mode.

[0012] In order to solve this problem, a nonvolatile storage system of the present invention is a nonvolatile storage system having a host device and a nonvolatile storage device connected to the host device, the nonvolatile storage system The storage device includes a nonvolatile memory that holds a plurality of programs in addition to user data, and a memory controller that writes data to the nonvolatile memory and reads data from the nonvolatile memory, and The memory controller includes a host interface unit that communicates with the host device, and a program download unit that selectively downloads the program from the nonvolatile memory in response to a program selection instruction, and the nonvolatile memory A memory interface unit for performing read / write control on the memory, and the memory interface A program selection unit for selecting and instructing the memory interface unit a program necessary for read / write control of the memory unit, which is downloaded by the control unit for controlling the operation of each unit of the memory controller and the program download unit. RAM for holding the program

[0013] Here, the program selection unit may select the program according to the type of instruction designated by the host device or the operation mode.

[0014] In order to solve this problem, the memory control method of the present invention provides a method for a non-volatile memory. A memory control method that selectively reads a program that reads and writes data from the nonvolatile memory in accordance with a data read and write instruction, and downloads the read program to the RAM The download process is performed at the same time as the process other than the download process.

Here, the program of the nonvolatile memory may be selected by a data read / write instruction or an operation of the memory controller.

The invention's effect

[0016] According to the present invention, the program download unit selectively downloads a program in response to a selection instruction from the program selection unit. As a result, the processing of the interface unit for the non-volatile memory can be made programmable, and it is possible to deal with a plurality of types of non-volatile memories, and the RAM capacity can be reduced.

Furthermore, since the program download is executed in parallel with the control unit force S and the operation control of each unit, the time overhead required for the download can be reduced.

[0018] Furthermore, since the necessary programs are selected and downloaded according to either the type of instruction or the operation mode specified from the outside, it is not necessary to download all the programs every time. Power saving can be realized.

Brief Description of Drawings

FIG. 1 is a block diagram showing a configuration of a nonvolatile storage system in an embodiment of the present invention.

FIG. 2A is a flowchart showing processing contents of the nonvolatile memory system.

FIG. 2B is a flowchart showing the processing contents of the nonvolatile memory system.

FIG. 3 is a time chart showing processing contents of the nonvolatile memory system.

[FIG. 4] FIG. 4 is a flowchart showing the contents of read processing in the memory interface unit.

[FIG. 5] FIG. 5 is a flowchart showing the contents of write processing in the memory interface section.

FIG. 6 is a flowchart showing the contents of erasure processing in the memory interface unit.

[FIG. 7A] FIG. 7A is a diagram showing register specifications. FIG. 7B is a diagram showing the contents of each bit of the register.

Explanation of symbols

[0020] 100 memory controller

101 Host interface B

102 Control section

103 Memory interface

104 RAM

105 Program selector

106 Logical physical conversion table

107 registers

108 Program Download Department

110 Nonvolatile memory

120 program area

121 First processing program

122 Second processing program

123 Third processing program

130 Table area

140 Normal area

150 Nonvolatile storage

160 hosts

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the main configuration of the nonvolatile memory system according to the embodiment of the present invention. The nonvolatile storage system according to the present embodiment includes a host device (hereinafter referred to as a host) 160 and a nonvolatile storage device 150. The host 160 and the nonvolatile storage device 150 are connected by a bus 1.

The non-volatile storage device 150 includes a memory controller 100 and a non-volatile memory 110. The memory controller 100 includes a host interface (IF) unit 101, a controller unit 102, a memory A re-interface (IF) unit 103 and a RAM 104 are included. The host interface unit 101 communicates with the host 160 via the bus 1. The control unit 102 includes a program selection unit 105, a logical physical conversion table 106, and a register 107. The memory interface unit 103 is an interface unit that communicates with the nonvolatile memory 110 via the bus 2, and includes a program download unit 108.

The non-volatile memory 110 includes a program area 120 and a normal area 140. The normal area 140 includes the table area 130. The table area 130 is an area for holding a table such as a logical physical conversion table.

[0024] In the program area 120, a program describing the processing contents of the memory interface unit 103 is written in advance before product shipment. This program is, for example, a first processing program 121, a second processing program 122, and a third processing program 123. These processing programs are written in the program area 120 with a unique number assigned to the first byte.

The logical-physical conversion table 106 is read from the table area 130 of the nonvolatile memory 110 and temporarily stored in the RAM in the control unit 102. It is updated after data is written or erased by the host 160 write or erase command, and is written back to the tape area 130.

The operation of the nonvolatile storage system configured as described above will be described. 2A and 2B are flowcharts showing the processing contents of the nonvolatile storage system in the embodiment of the present invention, and FIG. ₃ is a time chart showing the processing contents of the nonvolatile storage system in the embodiment of the present invention. It is a chart. 7A and 7B show the contents of the register 107. FIG. First, the control unit 102 that senses a change in voltage when the power is turned on sets 0, 1, 0, 0 to BITO, BIT1, BIT2, and BIT3 of the register 107, respectively. This is because initialization is always performed after power-on. During initialization, the program selection unit 105 continues to monitor the value of the register 107 to select an operation mode and a processing program, and performs the same processing as S230 in FIG. 2 described later. After initialization is completed, the control unit 102 sets BIT0 of the register 107 to 1, and sets BIT1 to BIT3 to 0 to return to normal operation. The register 107 during normal operation sets the value of the command force, the BIT0 force, and the BIT3 received by the control unit 102. In addition, Two or more of bits BIT1 to BIT3 in register 107 cannot be 1.

[0027] Now, processing after receiving a command from the host 160 will be described with reference to FIGS. 2A and 2B. The host 160 transmits a command to the host interface unit 101 (S200), and the host interface unit 101 receives the command (S201). The program selection unit 105 continues to monitor the register 107 to determine the operation mode and the processing program to be selected. (S202).

[0028] Here, the processing of S202 will be described in detail using Table 1. The operation mode is classified into two types: initialization and normal operation depending on the type of command sent from the host 160. The value of the first byte in program area 120 is 0x01 for read, 0x02 for write, and 0x03 for erase.

[table 1]

[0029] Here, the initialization means that the memory interface unit 103 starts from the table area 130 to the RAM in the control unit 102 in response to an initialization command received from the host 160 immediately after the nonvolatile storage device 150 is powered on. The operation of reading the logical-physical conversion table 106 is described below. On the other hand, the normal operation refers to an operation in which the memory interface unit 103 writes, reads, or erases the normal area 140 in accordance with a command from the host 160 after initialization.

Next, reading processing of the memory interface unit 103 in normal operation will be described with reference to the flowchart of FIG. Reading is an operation of reading data recorded at a physical address in the normal area 140 corresponding to a logical address designated by the host 160. The memory interface unit 103 sends an address input command to the nonvolatile memory 110. Transmit (S400), output a physical address (S401), and finally execute a read by transmitting a read start command (S402).

Next, the writing process of the memory interface unit 103 in the normal operation will be described with reference to the flowchart of FIG. The writing is an operation of writing data designated at a physical address in the normal area 140 corresponding to a logical address designated by the host 160. The memory interface unit 103 transmits a data address input command to the nonvolatile memory 110 (S500), outputs a physical address (S501), outputs further data (S502), and finally transmits a write start command (S503). By doing so, the writing is executed.

Next, erase processing of the memory interface unit 103 in normal operation will be described with reference to the flowchart of FIG. The erasing is an operation of erasing data of the physical address in the normal area 140 corresponding to the logical address designated by the host 160 from the normal area 140. The memory interface unit 103 transmits an address input command to the nonvolatile memory 110 (S600), outputs a physical address (S601), and finally transmits an erase start command (S602) to execute erasure.

[0033] Now, in FIG. 2, after the operation mode is determined in S202, the processing after S203 and the processing after S208 are performed in parallel. The host interface unit 101 determines whether or not the operation mode is normal operation (S203). If it is a normal operation, the host interface unit 101 retrieves the logical address of the command argument (S204), and the host interface unit 101 transmits the command and logical address to the control unit 102 (S205). The control unit 102 converts the logical address into a physical address using the logical / physical conversion table 106 (S206), and the control unit 102 transmits the physical address to the memory interface unit 103 (S207). Next, the memory interface unit 103 accesses the normal area 140 based on the program on the RAM 104 (S213).

Note that the logical-physical conversion process described above refers to a logical block and a physical block while performing so-called wear leveling to cope with the limit (lifetime) of the number of writes in the nonvolatile memory 110. Since this process can be realized using a known technique, the explanation is omitted.

Next, the operation from S208 will be described. In S208, the program selection unit 105 executes Select a program. When selecting the program, for example, if the operation mode is initialized from the value in register 107 and the processing program required for the RAM is read, select the “read” program whose first byte in the program area 120 is 0x01. To do. If the operation mode is normal operation and the processing program necessary for the RAM 104 is erasure, the “erase” program in which the first byte of the program area 120 is 0x03 is selected. Here, the program selection unit 105 holds the data of the first byte (hereinafter referred to as a new first byte).

[0036] After that, it is determined whether the program has not been downloaded (S209). If the download has not been completed, the program download unit 108 downloads the program in the program area 120 from the first byte of each program to the RAM 104. (S210).

[0037] Here, the processing of S209 and S210 will be described in detail. First, the program download unit 108 acquires the first 1 byte (hereinafter referred to as the old first byte) of the program already downloaded from the RAM 104 and holds it. Then, the program download unit 108 compares the data of the new first byte and the old first byte. If they are different, it is determined that the download has not yet been made, and the program is downloaded (S210). If these are the same, it is determined that the download has been performed and the processing of S210 is not executed. In S209, for example, if the host 160 command is executed twice in succession and the operation mode is normal operation and the program is erased, the program is judged to have already been downloaded the second time and the processing of S210 is skipped. Do not download.

Note that the processing from S205 force to S207 is S220, and the processing from S208 force to S210 is S230.

[0039] Next, processing in the case where the operation mode is initialization based on the determination in S203 will be described. In the case of initialization processing, it is determined in S211 whether the read program has already been downloaded. Since the program required for initialization is “read” as shown in Table 1, the first byte of the RAM 104 is acquired to check whether it is 0x01. If it is 0x01, the process proceeds to S212. If it is not 0x01, it is not already downloaded, so the first byte of the RAM 104 is obtained again and a determination is made. At this time, the process of S230 is simultaneously operating. S230 downloads the reading program because the operation mode is initialization. For this reason When downloading of the program is completed, it is already downloaded in S211. When the download is completed or the download is completed, the control unit 102 reads the data in the table area 130 into the logical-physical conversion table 106 in the control unit 102 (S212).

With reference to FIG. 3, the time relationship between the control unit 102 and its program selection unit 105, the memory interface unit 103 and its program download unit 108 will be described.

First, the memory interface unit 103 accesses the nonvolatile memory 110 based on the physical address. In normal operation, the host 160 accesses the nonvolatile storage device 150 based on the logical address. Therefore, the control unit 102 must convert the logical address to a physical address and output the physical address to the memory interface unit 103. Nanare ,. In other words, in order for the memory interface unit 103 to access the nonvolatile memory 110, the physical address must be determined by the logical-physical conversion process of the control unit 102.

Therefore, as shown in FIG. 3, the program selection unit 105 selects a program using the period during which the control unit 102 performs logical-physical conversion processing, and the program download unit 108 downloads the program. Then, access to the normal area based on the program.

[0043] As described above, in the nonvolatile storage system according to the embodiment of the present invention, the program download unit 108 selectively downloads a program in accordance with a selection instruction from the program selection unit 105. Can be reduced.

[0044] Also, in the normal operation, the download process of the program download unit 108 is performed in parallel with the process such as the logical-physical conversion of the control unit 102, so the download process is performed within the time required for the process of the control unit 102. It can be performed. In other words, the time overhead required for downloading becomes unnecessary.

[0045] In addition, a program for operating the memory interface unit 130 prior to product shipment is given a number in the first byte and written in the program area 120 in advance, so that the program selected by the program selection unit 105 is programmed. Before the download unit 108 downloads, the programs on the RAM 104 can be compared. Result of comparison Downloading to RAM can be done only when is different. In this way, power saving can be realized by minimizing the download from the program area 120 to the RAM 104.

Industrial applicability

The non-volatile storage memory which is useful in the present invention proposes a cost reduction of a memory controller and a non-volatile storage device or a non-volatile storage system on which the memory controller is mounted, and a non-volatile storage device such as a semiconductor memory card. This is useful in still image recording / playback devices, moving image recording / playback devices, and mobile phones.

Claims

The scope of the claims

[1] A memory controller that writes data to and reads data from a nonvolatile memory that holds a plurality of programs in addition to user data.

A host interface that communicates with the outside;

A memory interface unit that has a program download unit that selectively downloads the program from the non-volatile memory according to a program selection instruction, and that performs read / write control on the non-volatile memory;

A control unit for controlling the operation of each part of the memory controller, including a program selection unit for selecting and instructing the memory interface unit a program necessary for read / write control of the memory interface unit;

A memory controller comprising: a RAM that holds a program downloaded by the program download unit.

2. The memory controller according to claim 1, wherein the program selection unit selects the program according to an operation mode.

[3] In addition to user data, non-volatile memory that holds multiple programs,

A non-volatile storage device comprising a memory controller that writes data to the non-volatile memory and reads data from the non-volatile memory, the memory controller comprising:

A host interface that communicates with the outside;

A non-volatile storage device comprising: a RAM that holds the program downloaded by the program download unit;

4. The nonvolatile memory device according to claim 3, wherein the program selection unit selects the program according to an operation mode.

[5] A nonvolatile storage system having a host device and a nonvolatile storage device connected to the host device,

The nonvolatile memory device is

A nonvolatile memory that holds a plurality of programs in addition to user data; and a memory controller that writes data to the nonvolatile memory and reads data from the nonvolatile memory;

The memory controller is

A host interface unit for communicating with the host device;

A non-volatile storage system comprising: a RAM that holds the program downloaded by the program download unit;

6. The nonvolatile storage system according to claim 5, wherein the program selection unit selects the program in accordance with either the type of instruction or the operation mode specified from the host device.

[7] A memory control method for nonvolatile memory,

In response to a data read / write command, a program for performing data read / write from the nonvolatile memory is selectively read from the nonvolatile memory,

A memory control method for executing a download process for downloading the read program into a RAM simultaneously with a process other than the download process.

8. The memory control method according to claim 7, wherein a program of the nonvolatile memory is selected by a data read / write instruction or a memory controller operation.