WO2007143972A3 - Prozessor mit internem raster von ausführungseinheiten - Google Patents
Prozessor mit internem raster von ausführungseinheiten Download PDFInfo
- Publication number
- WO2007143972A3 WO2007143972A3 PCT/DE2007/001022 DE2007001022W WO2007143972A3 WO 2007143972 A3 WO2007143972 A3 WO 2007143972A3 DE 2007001022 W DE2007001022 W DE 2007001022W WO 2007143972 A3 WO2007143972 A3 WO 2007143972A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- grid
- processor
- alus
- alu
- connections
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
- G06F9/3895—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
- G06F9/3897—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Advance Control (AREA)
- Devices For Executing Special Programs (AREA)
- Executing Machine-Instructions (AREA)
Abstract
Die vorliegende Erfindung betrifft einen Prozessor, der als Hauptmerkmal ein internes Raster von ALUs aufweist, mit dessen Hilfe sequentielle Programme abgearbeitet werden. Die Verbindungen zwischen den ALUs werden automatisch dynamisch zur Laufzeit über Multiplexer hergestellt. Verantwortlich für das Herstellen der Verbindungen ist eine zentrale Dekodier- und Konfigurationseinheit, die aus einem Strom herkömmlicher Assembler-Befehle Konfigurationsdaten für das ALU-Grid zur Laufzeit erzeugt. Neben dem ALU-Grid ist eine spezielle Einheit für die Ausführung von Speicherzugriffen und eine weitere Einheit für die Behandlung von Sprungbefehlen vorhanden. Die dem Prozessor zugrunde liegende neuartige Architektur ermöglicht die effiziente Durchführung sowohl von Kontrollfluss- als auch von Datenfluss-orientieren Aufgaben.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/304,655 US20090249028A1 (en) | 2006-06-12 | 2007-06-12 | Processor with internal raster of execution units |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102006027181.5 | 2006-06-12 | ||
DE102006027181A DE102006027181B4 (de) | 2006-06-12 | 2006-06-12 | Prozessor mit internem Raster von Ausführungseinheiten |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2007143972A2 WO2007143972A2 (de) | 2007-12-21 |
WO2007143972A3 true WO2007143972A3 (de) | 2008-03-27 |
Family
ID=38663830
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2007/001022 WO2007143972A2 (de) | 2006-06-12 | 2007-06-12 | Prozessor mit internem raster von ausführungseinheiten |
Country Status (3)
Country | Link |
---|---|
US (1) | US20090249028A1 (de) |
DE (1) | DE102006027181B4 (de) |
WO (1) | WO2007143972A2 (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008072179A1 (en) * | 2006-12-11 | 2008-06-19 | Nxp B.V. | Virtual functional units for vliw processors |
US20150052330A1 (en) * | 2013-08-14 | 2015-02-19 | Qualcomm Incorporated | Vector arithmetic reduction |
JP6553694B2 (ja) * | 2017-09-25 | 2019-07-31 | Necスペーステクノロジー株式会社 | プロセッサエレメント、プログラマブルデバイス及びプロセッサエレメントの制御方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1577789A2 (de) * | 2003-12-22 | 2005-09-21 | Sanyo Electric Co., Ltd. | Rekonfigurierbare Schaltung mit Verbindungseinrichtung |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6023753A (en) * | 1997-06-30 | 2000-02-08 | Billion Of Operations Per Second, Inc. | Manifold array processor |
US6681341B1 (en) * | 1999-11-03 | 2004-01-20 | Cisco Technology, Inc. | Processor isolation method for integrated multi-processor systems |
JP2004334429A (ja) * | 2003-05-06 | 2004-11-25 | Hitachi Ltd | 論理回路及びその論理回路上で実行するプログラム |
JP4728581B2 (ja) * | 2004-02-03 | 2011-07-20 | 日本電気株式会社 | アレイ型プロセッサ |
JP4275013B2 (ja) * | 2004-06-21 | 2009-06-10 | 三洋電機株式会社 | データフローグラフ処理装置、処理装置、リコンフィギュラブル回路。 |
-
2006
- 2006-06-12 DE DE102006027181A patent/DE102006027181B4/de not_active Expired - Fee Related
-
2007
- 2007-06-12 WO PCT/DE2007/001022 patent/WO2007143972A2/de active Application Filing
- 2007-06-12 US US12/304,655 patent/US20090249028A1/en not_active Abandoned
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1577789A2 (de) * | 2003-12-22 | 2005-09-21 | Sanyo Electric Co., Ltd. | Rekonfigurierbare Schaltung mit Verbindungseinrichtung |
Non-Patent Citations (7)
Title |
---|
BRACY A ET AL: "Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth", MICROARCHITECTURE, 2004. MICRO-37 2004. 37TH INTERNATIONAL SYMPOSIUM ON PORTLAND, OR, USA 04-08 DEC. 2004, PISCATAWAY, NJ, USA,IEEE, 4 December 2004 (2004-12-04), pages 18 - 29, XP010859309, ISBN: 0-7695-2126-6 * |
BURGER D ET AL: "Scaling to the End of Silicon with EDGE Architectures", COMPUTER, IEEE SERVICE CENTER, LOS ALAMITOS, CA, US, vol. 37, no. 7, July 2004 (2004-07-01), pages 44 - 55, XP011115169, ISSN: 0018-9162 * |
CLARK N ET AL: "Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization", MICROARCHITECTURE, 2004. MICRO-37 2004. 37TH INTERNATIONAL SYMPOSIUM ON PORTLAND, OR, USA 04-08 DEC. 2004, PISCATAWAY, NJ, USA,IEEE, 4 December 2004 (2004-12-04), pages 30 - 40, XP010859310, ISBN: 0-7695-2126-6 * |
JONG-EUN LEE ET AL: "Evaluating memory architectures for media applications on coarse-grained reconfigurable architectures", APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES, AND PROCESSORS, 2003. PROCEEDINGS. IEEE INTERNATIONAL CONFERENCE ON 24-26 JUNE 2003, PISCATAWAY, NJ, USA,IEEE, 24 June 2003 (2003-06-24), pages 166 - 176, XP010645218, ISBN: 0-7695-1992-X * |
JONG-EUN LEE ET AL: "Reconfigurable ALU Array Architecture with Conditional Execution", INTERNATIONAL SOC DESIGN CONFERENCE, XX, XX, 25 October 2004 (2004-10-25), XP002376739 * |
OZAWA M ET AL: "A CASCADE ALU ARCHITECTURE FOR ASYNCHRONOUS SUPER-SCALAR PROCESSORS", IEICE TRANSACTIONS ON ELECTRONICS, ELECTRONICS SOCIETY, TOKYO, JP, vol. E84-C, no. 2, February 2001 (2001-02-01), pages 229 - 237, XP001044150, ISSN: 0916-8524 * |
YEHIA S ET AL: "From sequences of dependent instructions to functions : an approach for improving performance without ilp or speculation", COMPUTER ARCHITECTURE, 2004. PROCEEDINGS. 31ST ANNUAL INTERNATIONAL SYMPOSIUM ON MUNCHEN, GERMANY JUNE 19-23, 2004, PISCATAWAY, NJ, USA,IEEE, 19 June 2004 (2004-06-19), pages 238 - 249, XP010769379, ISBN: 0-7695-2143-6 * |
Also Published As
Publication number | Publication date |
---|---|
US20090249028A1 (en) | 2009-10-01 |
DE102006027181B4 (de) | 2010-10-14 |
WO2007143972A2 (de) | 2007-12-21 |
DE102006027181A1 (de) | 2007-12-13 |
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