WO2007138786A1 - Method for reducing thickness of substrate, lamination system, and substrate thickness reduction system - Google Patents

Method for reducing thickness of substrate, lamination system, and substrate thickness reduction system Download PDF

Info

Publication number
WO2007138786A1
WO2007138786A1 PCT/JP2007/057538 JP2007057538W WO2007138786A1 WO 2007138786 A1 WO2007138786 A1 WO 2007138786A1 JP 2007057538 W JP2007057538 W JP 2007057538W WO 2007138786 A1 WO2007138786 A1 WO 2007138786A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
support plate
solvent
bump
protective film
Prior art date
Application number
PCT/JP2007/057538
Other languages
French (fr)
Japanese (ja)
Inventor
Yoshihiro Inao
Yasumasa Iwata
Koichi Misumi
Takahiro Asai
Original Assignee
Tokyo Ohka Kogyo Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Ohka Kogyo Co., Ltd. filed Critical Tokyo Ohka Kogyo Co., Ltd.
Publication of WO2007138786A1 publication Critical patent/WO2007138786A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector

Definitions

  • the present invention relates to a method and system for thinning a substrate (wafer) having bumps (projection electrodes) formed on a circuit forming surface.
  • Patent Document 3 and Patent Document 4 disclose a protective tape on the surface (circuit forming surface) as means for grinding and thinning the back surface of a semiconductor wafer having the bump (projection electrode) formed on the surface.
  • the back surface of the semiconductor wafer is ground with a grinder, and finally the IC chip is peeled off using a collet.
  • Patent Document 1 Japanese Patent Laid-Open No. 8-148452
  • Patent Document 2 JP 2005-136187 A
  • Patent Document 3 Japanese Patent Application Laid-Open No. 2004-14843
  • Patent Document 4 Japanese Patent Laid-Open No. 2005-116610
  • a circuit forming surface (bump forming surface) was provided with a protective tape.
  • the protective tape is dissolved and removed, and in Patent Document 3 and Patent Document 4, the protective tape is peeled off. ing.
  • the protective tape does not adhere to the circuit forming surface where the embedding property to the bump of the protective tape is bad, and serves as a protective layer. This function may not fully function, and the wafer may slip during grinding, or the stress during grinding may not be absorbed and the wafer may be damaged. Also, when the protective tape is peeled off, the bump may interfere with the peeling, causing the wafer to break or the bump to peel off from the wafer together with the protective tape.
  • the substrate thinning method according to the present invention applies a liquid resin thicker than the height of the bumps to a circuit forming surface provided with the bumps of the substrate, and dries the liquid resin.
  • the substrate is attached to the support plate through this protective layer, and the back side of the substrate is ground to form a thin plate, and then the solvent supply hole formed on the support plate is supported.
  • a solvent was supplied between the plate and the protective layer to dissolve and remove the protective layer.
  • a system for carrying out the above-described thin plate coating method includes a coating apparatus that applies a liquid resin thicker than the bump height to a circuit forming surface of a substrate provided with bumps, and the applied liquid state.
  • a beta device for drying the resin to form a protective layer and a laminating device for laminating a support plate on the protective layer are provided.
  • a method using a squeegee is preferable as a means for uniformly applying the liquid resin thicker than the bump height.
  • the support plate for example, made of glass in which a large number of through-holes are formed in the thickness direction, or a large number of grooves capable of moving the solvent are formed on the surface bonded to the protective layer, A glass plate having a solvent supply hole and a recovery hole connected to the groove formed in the thickness direction can be used.
  • the protective layer adheres to the circuit forming surface provided with the bumps without gaps, the stress during grinding that absorbs no shift between the protective layer and the substrate during grinding is absorbed. This prevents cracking of the wafer. Furthermore, since the means for removing the protective layer is not peeling as in the conventional tape, there is no disadvantage that the bumps are peeled off with the tape.
  • FIG. 1 is a plan view showing the overall configuration of a substrate thinning system according to the present invention.
  • FIG. 2] (a) to (g) are diagrams illustrating a method of thinning a substrate according to the present invention in the order of steps.
  • FIG. 3 (a) and (b) are diagrams showing another embodiment.
  • FIG. 4 (a) and (b) are diagrams illustrating an example of a procedure for stacking substrates obtained by the method of the present invention to form a multilayer wiring structure.
  • FIG. 1 is a plan view showing the overall configuration of a substrate thin plate system (bonding system) according to the present invention.
  • the thin plate system encloses wafer cassette B and squeegee so as to surround transfer robot A.
  • Coating device C equipped, beta device D equipped with hot plate and cool plate, support plate supply device E, laminating device F for bonding the support plate on the protective layer F and grinding device for grinding the back side of the wafer G force is composed.
  • FIG. 2 is a diagram for explaining the method of thinning a substrate according to the present invention in the order of steps.
  • the surface W1 of a wafer (substrate) W to be ground is a circuit. 1 is formed, and a bump (projection electrode) 2 is formed on a part of the circuit 1.
  • a liquid resin 4 used as a resist for example, is applied to the surface W 1 of the wafer (substrate) W to be thicker than the height of the bump 2 using a squeegee 3.
  • a protective film 5 having a uniform thickness is formed as shown in FIG. 2 (c).
  • the coating thickness of the liquid resin 4 is determined by the height of the bump 2. That is, since the liquid resin 4 is thinned and thinned by drying (beta), it is necessary to be higher than the bump 2 even if this thinning is anticipated. For example, for a 200 ⁇ m bump, liquid resin 4 with a thickness of 200 to 400 ⁇ m What is necessary is just to apply.
  • the support plate 6 is overlaid on the protective film 5, and the support plate 6 is pressed by the head 7 to bond the support plate 6 and the protective film 5. .
  • a large number of solvent supply holes 8 are formed in the thickness direction of the support plate 6, and a solvent supply pipe 9 and a solvent recovery pipe 10 are connected to the head 7, and the lower surface of the head 7 and the upper surface of the support plate 6 are connected.
  • a solvent reservoir 12 defined by an O-ring 11 is formed between the two.
  • the support plate 6 is brought close to the surface W1 of the wafer (substrate) W up to a predetermined interval, and in this state, the resin is supplied from the liquid resin supply hole and the support plate 6 is supplied. Fill the space between the rate 6 and the surface W1 of wafer W, and then cure it by beta or ultraviolet irradiation to form a protective film.
  • a spin method or a slit nozzle method may be applied.
  • coating twice is preferable.
  • the solvent is supplied from the solvent supply pipe 9 of the head 7, and the protective film 5 and the support plate 6 are passed through the solvent supply holes 8 of the support plate 6.
  • the protective film 5 is dissolved by allowing the solvent to spread over the adhesive interface, and the solvent in which the protective film 5 is dissolved is recovered from the solvent recovery pipe 10 of the head 7.
  • a thinned wafer W shown in FIG. 2 (g) is obtained. That is, a circuit 1 is formed on the surface W1 of the wafer W, a through electrode 11 is formed as a part of the circuit 1, and a bump 2 is formed on the through electrode 11.
  • FIGS. 3 (a) and 3 (b) are diagrams showing another embodiment.
  • a groove 14 is formed as a support plate 6 on a surface in contact with the protective layer 5.
  • FIG. The solvent is supplied to the groove 14 through the through hole 15 in the thickness direction, and the solvent in which the protective layer is dissolved is recovered through the through hole 16 in the thickness direction.
  • FIG. 4 (a) In order to obtain a multilayer wiring structure using the above-described thinned wafer W, as shown in Fig. 4 (a), two thinned wafers W are prepared, and these back surfaces are provided.
  • a multi-layer wiring structure shown in FIG. 4 (b) is obtained by joining the through electrodes 21 so as to be moved through the facing wirings 22. Furthermore, by overlapping these in the same way, a multilayered wiring structure can be obtained. It should be noted that it is arbitrary how the thinned wafer W is formed into a multilayer wiring structure.

Abstract

[PROBLEMS] To provide a method for reducing the thickness of a substrate, which can reduce the thickness of a wafer (a substrate) with a bump provided on a circuit forming face without the separation of the bump. [MEANS FOR SOLVING PROBLEMS] A liquid resin (4) is coated to a larger thickness than the height of a bump (2) by a squeegee (3) onto a wafer (substrate) (W) in its surface (W1), and the coating is baked to form a protective film (5) having an even thickness. Thereafter, a support plate (6) is superimposed on the protective film (5), and the support plate (6) is pressed by a head (7) to conduct adhesion of the support plate (6) to the protective film (5). Next, the assembly is turned upside-down, and the backside (W2) of the wafer (W) is ground by a grinder (13) to reduce the thickness. Thereafter, a solvent is supplied through a solvent supply pipe (9) in the head (7), and the solvent is spread to the bonding interface of the protective film (5) and the support plate (6) through a number of solvent supply holes (8) in the support plate (6) to dissolve the protective film (5). Further, the solvent containing the protective film (5) dissolved therein is recovered from a solvent recovery pipe (10) in the head (7).

Description

明 細 書  Specification
基板の薄板化方法、貼り合わせシステムおよび薄板化システム 技術分野  Substrate thinning method, bonding system, and thinning system
[0001] 本発明は、回路形成面にバンプ (突起電極)を形成した基板 (ゥエーハ）を薄板ィ匕 する方法とそのシステムに関する。  [0001] The present invention relates to a method and system for thinning a substrate (wafer) having bumps (projection electrodes) formed on a circuit forming surface.
背景技術  Background art
[0002] 回路素子 (ICチップ)を薄くすることで、この回路素子を組み込む各種装置のコンパ クトイ匕を達成することができる。そのため特許文献 1に示すように、半導体ゥエーハの 回路形成面に保護テープを貼り付け、この保護テープを介して半導体ゥエーハを吸 着ヘッドなどに固定し、この状態で半導体ゥエーハの裏面側をグラインダーで検索し て薄板ィ匕し、薄板ィ匕した後に保護テープをイソプロピルアルコールで溶カゝして除去 するようにしている。  [0002] By thinning the circuit element (IC chip), it is possible to achieve a compact toy for various devices incorporating the circuit element. Therefore, as shown in Patent Document 1, a protective tape is attached to the circuit forming surface of the semiconductor wafer, and the semiconductor wafer is fixed to the suction head or the like through this protective tape. In this state, the back side of the semiconductor wafer is ground with a grinder. After searching and thinning, the protective tape is melted with isopropyl alcohol and removed.
[0003] また、回路の集積率を高めるため、特許文献 2に示すように、バンプ (突起電極)を 用いて上下の回路を電気的に接続して多層配線構造にすることが従来力 行われ ている。  [0003] In addition, in order to increase the integration rate of circuits, as shown in Patent Document 2, conventionally, upper and lower circuits are electrically connected using bumps (projection electrodes) to form a multilayer wiring structure. ing.
[0004] 更に、特許文献 3及び特許文献 4には上記のバンプ (突起電極)を表面に形成した 半導体ゥヱーハの裏面を研削して薄板ィヒする手段として、表面（回路形成面）に保護 テープを介してサポート板に取り付け、この状態でグラインダーによって半導体ゥエー ハの裏面を研削し、最終的にはコレットなどを用いて保護テープ力も ICチップを剥が すようにしている。  [0004] Further, Patent Document 3 and Patent Document 4 disclose a protective tape on the surface (circuit forming surface) as means for grinding and thinning the back surface of a semiconductor wafer having the bump (projection electrode) formed on the surface. In this state, the back surface of the semiconductor wafer is ground with a grinder, and finally the IC chip is peeled off using a collet.
[0005] 特許文献 1 :特開平 8— 148452号公報  Patent Document 1: Japanese Patent Laid-Open No. 8-148452
特許文献 2 :特開 2005— 136187号公報  Patent Document 2: JP 2005-136187 A
特許文献 3 :特開 2004— 14843号公報  Patent Document 3: Japanese Patent Application Laid-Open No. 2004-14843
特許文献 4：特開 2005 - 116610号公報  Patent Document 4: Japanese Patent Laid-Open No. 2005-116610
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0006] 上述したように、従来にあっては回路形成面 (バンプ形成面）に保護テープを介し てサポートプレートに貼り付け研削して薄板ィ匕した後、特許文献 1にあっては保護テ ープを溶解して除去し、特許文献 3及び特許文献 4にあっては保護テープを剥がす ようにしている。 [0006] As described above, in the past, a circuit forming surface (bump forming surface) was provided with a protective tape. In Patent Document 1, the protective tape is dissolved and removed, and in Patent Document 3 and Patent Document 4, the protective tape is peeled off. ing.
[0007] バンプが形成されているゥエーハの回路形成面を、保護テープを介してサポートプ レートに取り付けても、保護テープのバンプに対する埋め込み性が悪ぐ回路形成面 に密着せずに保護層としての機能を十分に発揮できず研削中にゥ ーハがずれたり 、研削時のストレスを吸収できずゥエーハを傷つけることがある。また保護テープを剥 離する場合にはバンプが剥離の邪魔になってゥエーハが割れたり、バンプが保護テ ープとともにゥエーノ、から剥がれてしまうことが生じる。  [0007] Even if the circuit forming surface of the wafer on which the bump is formed is attached to the support plate via a protective tape, the protective tape does not adhere to the circuit forming surface where the embedding property to the bump of the protective tape is bad, and serves as a protective layer. This function may not fully function, and the wafer may slip during grinding, or the stress during grinding may not be absorbed and the wafer may be damaged. Also, when the protective tape is peeled off, the bump may interfere with the peeling, causing the wafer to break or the bump to peel off from the wafer together with the protective tape.
課題を解決するための手段  Means for solving the problem
[0008] 上記課題を解決するため本発明に係る基板の薄板化方法は、基板のバンプを設 けた回路形成面に前記バンプの高さよりも厚く液状榭脂を塗布し、この液状榭脂を乾 燥せしめて保護層とし、この保護層を介して基板をサポートプレートに取り付けて基 板の裏面側を研削して薄板ィ匕し、この後、前記サポートプレートに形成した溶剤供給 孔カゝらサポートプレートと保護層との間に溶剤を供給して前記保護層を溶解除去す るよつにした。 [0008] In order to solve the above problems, the substrate thinning method according to the present invention applies a liquid resin thicker than the height of the bumps to a circuit forming surface provided with the bumps of the substrate, and dries the liquid resin. The substrate is attached to the support plate through this protective layer, and the back side of the substrate is ground to form a thin plate, and then the solvent supply hole formed on the support plate is supported. A solvent was supplied between the plate and the protective layer to dissolve and remove the protective layer.
[0009] また、上記の薄板ィ匕方法を実施するシステムは、バンプを設けた基板の回路形成 面に前記バンプの高さよりも厚く液状榭脂を塗布する塗布装置と、前記塗布された液 状榭脂を乾燥せしめて保護層とするベータ装置と、前記保護層の上にサポートプレ ートを貼り合わせる貼り合せ装置を備えて ヽる。  [0009] In addition, a system for carrying out the above-described thin plate coating method includes a coating apparatus that applies a liquid resin thicker than the bump height to a circuit forming surface of a substrate provided with bumps, and the applied liquid state. A beta device for drying the resin to form a protective layer and a laminating device for laminating a support plate on the protective layer are provided.
[0010] バンプの高さよりも厚く且つ均一に液状榭脂を塗布する手段としては、スキージを用 いる方法が好ましい。また保護層となる液状榭脂としては、例えばアクリル系榭脂 (溶 剤等により粘度が調整されていてよい）を用い、溶剤としてはアルコール等の極性溶 剤を用いるのが好ましい。  [0010] A method using a squeegee is preferable as a means for uniformly applying the liquid resin thicker than the bump height. In addition, it is preferable to use, for example, an acrylic resin (the viscosity may be adjusted by a solvent or the like) as the liquid resin serving as the protective layer, and a polar solvent such as an alcohol as the solvent.
[0011] また、サポートプレートとしては、例えば厚み方向に多数の貫通孔が形成されたガ ラス製、或いは保護層と接着される面に溶剤の移動を可能とする多数の溝が形成さ れ、この溝につながる溶剤の供給孔と回収孔を厚み方向に形成したガラス製のプレ ートなどを使用することができる。 発明の効果 [0011] Further, as the support plate, for example, made of glass in which a large number of through-holes are formed in the thickness direction, or a large number of grooves capable of moving the solvent are formed on the surface bonded to the protective layer, A glass plate having a solvent supply hole and a recovery hole connected to the groove formed in the thickness direction can be used. The invention's effect
[0012] 本発明によれば、保護層がバンプを設けた回路形成面に隙間なく接着するため、 研削中に保護層と基板との間にずれが生じることがなぐ研削中のストレスを吸収して ゥエーハの割れなどを防ぐことができる。更に保護層を除去する手段が従来のテープ のように引き剥がしではないので、バンプがテープとともに剥離してしまう不利もない 図面の簡単な説明  [0012] According to the present invention, since the protective layer adheres to the circuit forming surface provided with the bumps without gaps, the stress during grinding that absorbs no shift between the protective layer and the substrate during grinding is absorbed. This prevents cracking of the wafer. Furthermore, since the means for removing the protective layer is not peeling as in the conventional tape, there is no disadvantage that the bumps are peeled off with the tape.
[0013] [図 1]本発明に係る基板の薄板化システムの全体構成を示す平面図 FIG. 1 is a plan view showing the overall configuration of a substrate thinning system according to the present invention.
[図 2] (a)〜 (g)は本発明に係る基板の薄板化方法を工程順に説明した図  [FIG. 2] (a) to (g) are diagrams illustrating a method of thinning a substrate according to the present invention in the order of steps.
[図 3] (a)及び (b)は別実施例を示す図  FIG. 3 (a) and (b) are diagrams showing another embodiment.
[図 4] (a)及び (b)は本発明方法にて得られた基板を積層して多層配線構造とする手 順の一例を説明した図  [FIG. 4] (a) and (b) are diagrams illustrating an example of a procedure for stacking substrates obtained by the method of the present invention to form a multilayer wiring structure.
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0014] 以下に本発明を実施するための最良の形態を図面に基づいて詳細に説明する。  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.
図 1は本発明に係る基板の薄板ィ匕システム (貼り合せシステム)の全体構成を示す平 面図であり、薄板化システムは搬送ロボット Aを囲むように、ゥエーハカセット B、スキ ージを備えた塗布装置 C、ホットプレート及びクールプレートを備えたベータ装置 D、 サポートプレート供給装置 E、保護層の上にサポートプレートを貼り合わせる貼り合せ 装置 F及びゥ ーハの裏面側を研削する研削装置 G力 構成される。  FIG. 1 is a plan view showing the overall configuration of a substrate thin plate system (bonding system) according to the present invention. The thin plate system encloses wafer cassette B and squeegee so as to surround transfer robot A. Coating device C equipped, beta device D equipped with hot plate and cool plate, support plate supply device E, laminating device F for bonding the support plate on the protective layer F and grinding device for grinding the back side of the wafer G force is composed.
[0015] 図 2は本発明に係る基板の薄板ィ匕方法を工程順に説明した図であり、図 2 (a)に示 すように、研削対象となるゥエーハ（基板) Wの表面 W1は回路 1が形成され、この回 路 1の一部にはバンプ (突起電極） 2が形成されて 、る。  [0015] FIG. 2 is a diagram for explaining the method of thinning a substrate according to the present invention in the order of steps. As shown in FIG. 2 (a), the surface W1 of a wafer (substrate) W to be ground is a circuit. 1 is formed, and a bump (projection electrode) 2 is formed on a part of the circuit 1.
[0016] 次いで、図 2 (b)〖こ示すように、上記のゥエーハ（基板) Wの表面 W1にスキージ 3を 用いて例えばレジストとして用いる液状榭脂 4をバンプ 2の高さよりも厚く塗布し、ベー クすることで図 2 (c)に示すように均一な厚みの保護膜 5を形成する。ここで、液状榭 脂 4の塗布厚はバンプ 2の高さによって決定する。即ち、乾燥 (ベータ）によって液状 榭脂 4は膜減りして薄くなるので、この膜減りを見込んでもバンプ 2より高いことが必要 である。例えば、 200 μ mのバンプに対しては 200〜400 μ mの厚さで液状榭脂 4を 塗布すればよい。 Next, as shown in FIG. 2 (b), a liquid resin 4 used as a resist, for example, is applied to the surface W 1 of the wafer (substrate) W to be thicker than the height of the bump 2 using a squeegee 3. By baking, a protective film 5 having a uniform thickness is formed as shown in FIG. 2 (c). Here, the coating thickness of the liquid resin 4 is determined by the height of the bump 2. That is, since the liquid resin 4 is thinned and thinned by drying (beta), it is necessary to be higher than the bump 2 even if this thinning is anticipated. For example, for a 200 μm bump, liquid resin 4 with a thickness of 200 to 400 μm What is necessary is just to apply.
[0017] この後、図 2 (d)に示すように、保護膜 5の上にサポートプレート 6を重ね、更にへッ ド 7によってサポートプレート 6を押し付けてサポートプレート 6と保護膜 5を接着する。  [0017] After that, as shown in FIG. 2 (d), the support plate 6 is overlaid on the protective film 5, and the support plate 6 is pressed by the head 7 to bond the support plate 6 and the protective film 5. .
[0018] サポートプレート 6には厚み方向に多数の溶剤供給孔 8が形成され、またヘッド 7に は溶剤供給用配管 9と溶剤回収用配管 10が接続され、ヘッド 7下面とサポートプレー ト 6上面との間には Oリング 11で画成される溶剤溜り 12が形成される。  [0018] A large number of solvent supply holes 8 are formed in the thickness direction of the support plate 6, and a solvent supply pipe 9 and a solvent recovery pipe 10 are connected to the head 7, and the lower surface of the head 7 and the upper surface of the support plate 6 are connected. A solvent reservoir 12 defined by an O-ring 11 is formed between the two.
[0019] 尚、スキージを用いずに、サポートプレート 6を所定間隔までゥエーハ（基板) Wの表 面 W1に接近せしめ、この状態で液状樹脂の供給孔カゝら榭脂を供給してサポートプ レート 6とゥエーハ Wの表面 W1との間の空間に充填し、この後ベータ若しくは紫外線 の照射などによって硬化せしめて保護膜を形成するようにしてもょ 、。またスピン法や スリットノズル法を適用してもよい。但し、本発明の場合には 200〜400 /ζ πι程度の厚 さに塗布することが必要なため、スピン法やスリットノズル法の場合には二度塗りが好 ましい。  [0019] It should be noted that without using a squeegee, the support plate 6 is brought close to the surface W1 of the wafer (substrate) W up to a predetermined interval, and in this state, the resin is supplied from the liquid resin supply hole and the support plate 6 is supplied. Fill the space between the rate 6 and the surface W1 of wafer W, and then cure it by beta or ultraviolet irradiation to form a protective film. Also, a spin method or a slit nozzle method may be applied. However, in the case of the present invention, since it is necessary to apply to a thickness of about 200 to 400 / ζ πι, in the case of the spin method or the slit nozzle method, coating twice is preferable.
[0020] 以上の如くして、保護膜 5を介してゥエーノ、 Wをサポートプレート 6に取り付けたなら ば、図 2 (e)〖こ示すように、上下反転せしめてゥエーハ Wの裏面 W2をグラインダー 13 にて研削し薄板ィ匕する。  [0020] As described above, if the ueno and W are attached to the support plate 6 through the protective film 5, as shown in Fig. 2 (e), it is turned upside down and the back surface W2 of the woofer W is attached to the grinder. Grind at 13 and thin plate.
[0021] この後、図 2 (f)に示すように、ヘッド 7の溶剤供給用配管 9から溶剤を供給し、サボ ートプレート 6の多数の溶剤供給孔 8を介して保護膜 5とサポートプレート 6の接着界 面に溶剤を行き渡らせて保護膜 5を溶解せしめ、更に保護膜 5が溶けた溶剤をヘッド 7の溶剤回収用配管 10から回収する。  Thereafter, as shown in FIG. 2 (f), the solvent is supplied from the solvent supply pipe 9 of the head 7, and the protective film 5 and the support plate 6 are passed through the solvent supply holes 8 of the support plate 6. The protective film 5 is dissolved by allowing the solvent to spread over the adhesive interface, and the solvent in which the protective film 5 is dissolved is recovered from the solvent recovery pipe 10 of the head 7.
[0022] 保護膜 5を溶解除去することで、図 2 (g)に示す薄板化されたゥエーハ Wが得られる 。即ち、ゥエーハ Wの表面 W1には回路 1が形成され、この回路 1の一部として貫通電 極 11が形成され、この貫通電極 11の上にバンプ 2が形成されて!、る。  [0022] By dissolving and removing the protective film 5, a thinned wafer W shown in FIG. 2 (g) is obtained. That is, a circuit 1 is formed on the surface W1 of the wafer W, a through electrode 11 is formed as a part of the circuit 1, and a bump 2 is formed on the through electrode 11.
[0023] 保護膜 5を溶解除去に関しては、完全に保護膜 5を溶解させず、サポートプレート が容易に剥がれるまで保護膜 5を溶解したらここで溶解を停止し、サポートプレートを 剥離した後に洗浄液にて残りの保護膜 5を溶解除去するのが好ましい。即ち、保護 膜 5を完全に溶解除去するとサポートプレート 6とバンプ 2とがぶつ力ることがあり、バ ンプを潰してしまうことが考えられるので、上記の方法が好ま 、。 [0024] 図 3 (a)及び (b)は別実施例を示す図であり、 (a)に示す実施例では、サポートプレ ート 6として保護層 5と接触する面に溝 14を形成し、この溝 14に厚み方向の貫通孔 1 5を介して溶剤を供給するとともに、厚み方向の貫通孔 16を介して保護層が溶けた 溶剤を回収するようにして 、る。 [0023] Regarding the dissolution removal of the protective film 5, the protective film 5 is not completely dissolved, and the protective film 5 is dissolved until the support plate is easily peeled off. The remaining protective film 5 is preferably dissolved and removed. That is, if the protective film 5 is completely dissolved and removed, the support plate 6 and the bump 2 may collide with each other and the bump may be crushed. Therefore, the above method is preferred. FIGS. 3 (a) and 3 (b) are diagrams showing another embodiment. In the embodiment shown in FIG. 3 (a), a groove 14 is formed as a support plate 6 on a surface in contact with the protective layer 5. FIG. The solvent is supplied to the groove 14 through the through hole 15 in the thickness direction, and the solvent in which the protective layer is dissolved is recovered through the through hole 16 in the thickness direction.
[0025] (b)に示す実施例にあっては、保護層 5を溶解せしめる工程において、ゥエーノ、 W を上方に、サポートプレート 6を下方に配置して行うようにしている。斯カる構成とする と溶剤の回収が容易になる。  [0025] In the embodiment shown in (b), in the step of dissolving the protective layer 5, Ueno and W are arranged upward and the support plate 6 is arranged downward. Such a configuration makes it easier to recover the solvent.
[0026] 上記の薄板ィ匕されたゥエーハ Wを用いて多層配線構造とするには、図 4 (a)に示す ように、薄板ィ匕されたゥエーハ Wを 2枚用意し、これらの裏面を対向せしめ配線 22を 介して夫々の貫通電極 21を動通せしめるように接合することで、図 4 (b)に示す多層 配線構造が得られる。更にこれらを同様の手法で重ねることで更に重畳された多層 配線構造が得られる。尚、薄板ィ匕されたゥエーハ Wをどのようにして多層配線構造に するかは任意である。  [0026] In order to obtain a multilayer wiring structure using the above-described thinned wafer W, as shown in Fig. 4 (a), two thinned wafers W are prepared, and these back surfaces are provided. A multi-layer wiring structure shown in FIG. 4 (b) is obtained by joining the through electrodes 21 so as to be moved through the facing wirings 22. Furthermore, by overlapping these in the same way, a multilayered wiring structure can be obtained. It should be noted that it is arbitrary how the thinned wafer W is formed into a multilayer wiring structure.

Claims

請求の範囲 The scope of the claims
[1] バンプを設けた基板の回路形成面に前記バンプの高さよりも厚く液状榭脂を塗布し [1] Apply a liquid resin thicker than the bump height to the circuit formation surface of the board on which the bumps are provided.
、この液状榭脂を乾燥せしめて保護層とし、この保護層を介して基板をサポートプレ ートに取り付けて基板の裏面側を研削して薄板ィ匕し、この後、前記サポートプレート に形成した溶剤供給孔からサポートプレートと保護との間に溶剤を供給して前記保 護層を溶解除去することを特徴とする基板の薄板化方法。 The liquid resin is dried to form a protective layer, the substrate is attached to the support plate via the protective layer, the back side of the substrate is ground and thinned, and then formed on the support plate. A method of thinning a substrate, comprising: supplying a solvent from a solvent supply hole between a support plate and a protective member to dissolve and remove the protective layer.
[2] 請求項 1に記載の基板の薄板化方法にお!、て、前記液状樹脂の塗布はスキージを 用いて行うことを特徴とする基板の薄板化方法。  [2] The method for thinning a substrate according to claim 1, wherein the application of the liquid resin is performed using a squeegee.
[3] バンプを設けた基板の回路形成面に前記バンプの高さよりも厚く液状榭脂を塗布す る塗布装置と、前記塗布された液状榭脂を乾燥せしめて保護層とするベータ装置と、 前記保護層の上にサポートプレートを貼り合わせる貼り合せ装置とを備えた貼り合わ せシステム。 [3] A coating device that applies a liquid resin thicker than the bump height to a circuit forming surface of a substrate provided with a bump, a beta device that dries the applied liquid resin to form a protective layer, A laminating system comprising a laminating apparatus for laminating a support plate on the protective layer.
[4] バンプを設けた基板の回路形成面に前記バンプの高さよりも厚く液状榭脂を塗布す る塗布装置と、前記塗布された液状榭脂を乾燥せしめて保護層とするベータ装置と、 前記保護層の上にサポートプレートを貼り合わせる貼り合せ装置と、前記サポートプ レートが貼り合わされた基板の裏面側を研削する研削装置とを備えた基板の薄板ィ匕 システム。  [4] A coating device that applies a liquid resin thicker than the bump height to a circuit forming surface of a substrate provided with a bump, a beta device that dries the applied liquid resin to form a protective layer, A substrate thin plate system comprising: a bonding device for bonding a support plate on the protective layer; and a grinding device for grinding the back side of the substrate on which the support plate is bonded.
PCT/JP2007/057538 2006-06-01 2007-04-04 Method for reducing thickness of substrate, lamination system, and substrate thickness reduction system WO2007138786A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006152987A JP5008340B2 (en) 2006-06-01 2006-06-01 Substrate thinning method, bonding system, and thinning system
JP2006-152987 2006-06-01

Publications (1)

Publication Number Publication Date
WO2007138786A1 true WO2007138786A1 (en) 2007-12-06

Family

ID=38778311

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/057538 WO2007138786A1 (en) 2006-06-01 2007-04-04 Method for reducing thickness of substrate, lamination system, and substrate thickness reduction system

Country Status (4)

Country Link
JP (1) JP5008340B2 (en)
KR (1) KR20090018139A (en)
TW (1) TW200806395A (en)
WO (1) WO2007138786A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103042449A (en) * 2011-10-11 2013-04-17 株式会社迪思科 Method of grinding a wafer

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7470411B2 (en) 2020-09-30 2024-04-18 フジコピアン株式会社 Laminate for wafer processing, method for manufacturing thin wafer using same, and method for dividing thin wafer

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10270398A (en) * 1997-03-27 1998-10-09 Fujikoshi Mach Corp Wafer polishing device
JP2004153193A (en) * 2002-11-01 2004-05-27 Disco Abrasive Syst Ltd Processing method for semiconductor wafer
JP2005191550A (en) * 2003-12-01 2005-07-14 Tokyo Ohka Kogyo Co Ltd Method for sticking substrates
JP2005303214A (en) * 2004-04-16 2005-10-27 Matsushita Electric Ind Co Ltd Grinding method for semiconductor wafer
JP2005347382A (en) * 2004-06-01 2005-12-15 Mitsui Chemicals Inc Adhesive film for protecting semiconductor wafer surface, and semiconductor wafer protecting method using adhesive film
JP2006135272A (en) * 2003-12-01 2006-05-25 Tokyo Ohka Kogyo Co Ltd Substrate support plate and peeling method of support plate

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10270398A (en) * 1997-03-27 1998-10-09 Fujikoshi Mach Corp Wafer polishing device
JP2004153193A (en) * 2002-11-01 2004-05-27 Disco Abrasive Syst Ltd Processing method for semiconductor wafer
JP2005191550A (en) * 2003-12-01 2005-07-14 Tokyo Ohka Kogyo Co Ltd Method for sticking substrates
JP2006135272A (en) * 2003-12-01 2006-05-25 Tokyo Ohka Kogyo Co Ltd Substrate support plate and peeling method of support plate
JP2005303214A (en) * 2004-04-16 2005-10-27 Matsushita Electric Ind Co Ltd Grinding method for semiconductor wafer
JP2005347382A (en) * 2004-06-01 2005-12-15 Mitsui Chemicals Inc Adhesive film for protecting semiconductor wafer surface, and semiconductor wafer protecting method using adhesive film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103042449A (en) * 2011-10-11 2013-04-17 株式会社迪思科 Method of grinding a wafer

Also Published As

Publication number Publication date
JP2007324370A (en) 2007-12-13
TW200806395A (en) 2008-02-01
JP5008340B2 (en) 2012-08-22
KR20090018139A (en) 2009-02-19

Similar Documents

Publication Publication Date Title
JP6759343B2 (en) Arrangement of ultra-small or ultra-thin discrete parts
US7494845B2 (en) Method of forming a thin wafer stack for a wafer level package
KR100780123B1 (en) Dicing sheet, manufacturing method thereof, and manufacturing method of semiconductor apparatus
JP7321760B2 (en) Display device manufacturing method and source substrate structure
KR100759687B1 (en) Method for thinning substrate and method for manufacturing circuit device
US7723213B2 (en) Manufacturing method of semiconductor chips and semiconductor device having the semiconductor chips
CN101512742B (en) Method for manufacturing semiconductor device
WO2008012937A1 (en) Wafer bonding method, thinning method and detaching method
JP4179312B2 (en) Semiconductor device mounting method, semiconductor device
KR101530528B1 (en) Production method for solder transfer base matrerial, solder precoating method, and solder transfer base material
JP3917484B2 (en) Semiconductor device manufacturing method and semiconductor device
JP5647335B2 (en) Solder transfer substrate, method for manufacturing solder transfer substrate, and solder transfer method
US9613932B2 (en) Integrated circuit package and method of making same
WO2007138786A1 (en) Method for reducing thickness of substrate, lamination system, and substrate thickness reduction system
JP4515129B2 (en) Manufacturing method of semiconductor device
JP2007294575A (en) Method for manufacturing semiconductor device
JP2012004603A (en) Mounting structure for semiconductor device, method for mounting semiconductor device and substrate
JP6698337B2 (en) Semiconductor wafer holding method and semiconductor device manufacturing method
JP4173681B2 (en) Device connection method
JP5087967B2 (en) Electronic chip component and manufacturing method thereof
TW202321040A (en) Method for manufacturing connection structure
CN113053760A (en) Packaging method
JP2010199187A (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07740974

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 1020087030791

Country of ref document: KR

NENP Non-entry into the national phase

Ref country code: RU

122 Ep: pct application non-entry in european phase

Ref document number: 07740974

Country of ref document: EP

Kind code of ref document: A1