WO2007138693A1

WO2007138693A1 - Semiconductor device and method for manufacturing same

Info

Publication number: WO2007138693A1
Application number: PCT/JP2006/310881
Authority: WO
Inventors: Masaomi Yamaguchi; Yasuyoshi Mishima
Original assignee: Fujitsu Limited
Priority date: 2006-05-31
Filing date: 2006-05-31
Publication date: 2007-12-06
Also published as: JPWO2007138693A1

Abstract

A semiconductor device is provided with a semiconductor substrate (11); a single layer gate electrode (15), which is positioned on the semiconductor substrate and is formed of a material including silicon (Si); and a gate insulating film (14) inserted between the gate electrode and the semiconductor substrate. The gate insulating film is an oxide or an oxynitride of three or more kinds of metal elements including a first metal, a second metal and a third metal.

Description

Specification

Semiconductor device and manufacturing method thereof

Technical field

The present invention relates to a semiconductor device in which a threshold voltage (Vth) shift caused by Fermi level pinning, fixed charge, or the like is suppressed, and a manufacturing method thereof. Background art

[0002] High-speed LSI integration has been advanced by miniaturization of MOS field-effect transistors (MO SFETs) based on a scaling rule. Regarding miniaturization, by simultaneously reducing the height and lateral dimensions of each part of the MOSFET, such as the film thickness of the Si02 insulating film and the gate length, to maintain normal device characteristics and improve performance Has made it possible.

[0003] MOS field-effect transistors are still being miniaturized, and according to this scaling rule, next-generation MOS field-effect transistors require a thickness of less than In m for the Si02 gate insulating film. It has been.

[0004] However, since this film thickness region is also the thickness at which the tunnel current starts to flow directly, the leakage current cannot be suppressed, and problems such as an increase in power consumption cannot be avoided. Therefore, by using a material having a high Si02 by remote permittivity, silicon Sani匕膜terms effective thickness _{_{_{(EOT: Equi Va l en t}}} 0 xide Thickness) a while kept below lnm, earns physical thickness It is necessary to suppress the leakage current.

[0005] For example, oxynitride containing nofnium (Hf) as a main component is a material having a dielectric constant several times to 10 times higher than that of Si02. Hf oxynitride is expected to be applied as a next-generation gate insulating film because of its high dielectric constant (High k).

[0006] On the other hand, the use of metal for the gate is also being studied. Metal gates have the advantage that depletion does not occur and gate resistance can be reduced. It is expected that the gate electrode will be polysilicon (Poly-Si) because it is difficult to control the work function due to its strength and heat resistance. In other words, for the near future, there is an urgent need to research and develop MOSFETs that combine HfSiON films with poly-Si gates.

[0007] When a high-dielectric-constant insulating material as described above is formed by a CVD method, it is usually a pre-deposition process. Then, an SiO (N) film having a thickness of 0.8 nm or less is formed on the Si substrate, and a high-k insulating film is formed thereon. After deposition, post-deposition (PDA) is performed, and then a polysilicon gate electrode film is deposited.

[0008] As a method of controlling the EOT of the high-k insulating film to a desired value, a method of controlling the dielectric constant by injecting impurities into a predetermined depth region of the high-k insulating film has been proposed. (For example, see Patent Document 1).

In this method, as shown in FIG. 1A, a first insulating film 102 is formed on a silicon substrate 101 using a high-k material having a first dielectric constant, for example, Hf02. Next, as shown in FIG. 1B, impurities such as aluminum (A1), silicon i), and germanium (Ge) are implanted into a predetermined depth region of the Hf02 insulating film. Next, as shown in FIG. 1 (c), the activation of the implanted ions is performed by annealing, and a second dielectric film 103 having a second dielectric constant such as Hf AlxOy is generated. Finally, as shown in FIG. 1 (d), a polysilicon film is deposited over the entire surface, and a poly-Si gate electrode 105 and a double gate insulating film 104 are formed by ordinary lithography and etching processes. Using the gate electrode 105 and the double gate insulating film 104 as a mask, ion implantation is performed to form an extension region 106, a sidewall 107, and then a source and drain region 108 to form a double gate insulating film transistor. To complete.

[0010] Further, in a structure using an Hf-based high-k film as the gate insulating film, in order to prevent an interface reaction (diffusion of impurities) between the polysilicon gate electrode and the Hf-based high-k gate insulating film, There has also been proposed a method of making a double (see, for example, Patent Document 2).

[0011] In this method, as shown in FIG. 2, the dielectric constant is higher than that of the silicon oxide film, and the element contains elements other than silicon (Si), oxygen (0), and nitrogen (N). — Use a gate insulating film 204 having a k film such as HfAlO or HfSiO force. A gate electrode 205 composed of a first polysilicon film 205a having a large grain size and a second polysilicon film 205b having a small grain size is positioned on the gate insulating film 204. Side surfaces of the gate electrode 205 and the gate insulating film 204 are covered with a sidewall 207, and a source / drain 208 is formed in the silicon substrate 201.

Patent Document 1: Japanese Unexamined Patent Application Publication No. 2004-134753 Patent Document 2: JP 2005-251801 A

Disclosure of the invention

Problems to be solved by the invention

[0012] When HfSiO (N) is combined with polysilicon (Poly-Si), which is the gate electrode, the interaction causes n-type Poly-Si and p-type Poly as shown in Fig. 3 (a). — Fermi level of Si Force Phenomenon appears to be pulled to almost the same position as if pinned. Fermi

It is a phenomenon called 'level pyung.

[0013] When the peaking occurs, for example, in the case of a PMOS diode, the flat band voltage (Vl) shifts to the minus side by about 0.55 V. In the NMOS diode, it shifts to the plus side by about 0.2V.

[0014] Originally, the Vlb of the MOS structure is determined by the difference in work function between the Poly-Si and the Si substrate. In general, PMOS Vlb is around 0.9V, NMOS is around -0.9V, and the difference is about 1.8V. This is the ideal value.

However, due to the pinning, Vfb becomes 0.35V in the PMOS, and around 0.7V in the NMOS. In other words, the difference in Vl between the PMOS diode and NMOS diode should be about 1.8V, but it will be reduced to about 1.05V due to force piping.

[0016] As shown in FIGS. 3 (b) and 3 (c), the threshold voltage (Vth) shifts between PMOS and NMOS due to the peaking. This increase in threshold voltage is particularly noticeable in PMOS.

[0017] Such a phenomenon occurs only when an Hf-based insulating film is used for the gate electrode mainly composed of silicon (Si), so that it occurs at the interface between Poly-Si and HfSiO (N). It is thought that there is a cause. Recently, oxygen atoms are released from HfSiO (N) and oxygen vacancies are formed, which is considered to cause pinning. Electrons generated by the generation of oxygen vacancies move into Pily-Si. The theory that the distribution of electrons at the interface is biased is becoming more prominent. There is also the theory that the Hf-Si bond causes the pieng. The idea is that Hf-Si bond levels are generated in the band gap, causing pieng. Neither of these theories is definitive proof, but agrees that the cause is thought to be caused by the interface between Poly-Si and HfSiO (N)! Means for solving the problem

[0018] Piing is a phenomenon that occurs in association with elements such as Si, 0, and Hf. On the other hand, aluminum (A1) is known to bind strongly to oxygen and to react with Si.

Therefore, in one embodiment of the present invention, silicon is contained on a silicon substrate via a gate insulating film (for example, Hf SiAlO (N)) in which A1 is introduced into an Hf-based insulating film such as HfSiO (N). The pinning phenomenon is suppressed by adopting a structure in which the gate electrode is arranged.

[0020] Also provided is a method for producing an interface between the gate electrode film Z and the gate insulating film so that the effect of A1 can be further exerted.

[0021] Specifically, in the first aspect, the semiconductor device comprises:

(a) a semiconductor substrate;

(b) a single-layer gate electrode formed on a material containing silicon (Si), located on the semiconductor substrate;

(c) a gate insulating film inserted between the gate electrode and the semiconductor substrate;

The gate insulating film is an oxide or oxynitride of three or more metal elements including the first metal, the second metal, and the third metal.

It is characterized by that.

In good practice, the first metal and the second metal are each selected from Hf, Si, Zr, Ta, Ti, Y, and La.

Alternatively, the first metal is Si and the second metal is selected from Hf, Zr, Ta, Ti, Y, and La.

[0022] In a second aspect, a method for manufacturing a semiconductor device includes:

(a) forming an insulating film made of an oxide or oxynitride of two or more metal elements including a first metal and a second metal on a semiconductor substrate;

(b) forming a thin film made of a third metal on the insulating film;

(c) including a step of depositing a gate electrode film on the third metal film with a material containing silicon.

[0023] Preferably, in the example, in the step of depositing the gate electrode film, the third metal is separated from the insulating film. Diffusing into the film.

[0024] The film thickness of the third metal is, for example, in the range of 0.1 nm to 1 Onm.

Effect

[0025] With the configuration and method as described above, a transistor structure is realized in which the threshold voltage shift (rise) due to Fermi 'level' peaking or the like is suppressed.

[0026] At the interface between the Hf-based gate insulating film and the poly-Si gate electrode film, it is possible to form an interface with a high Fermi 'level' pinning suppression effect.

Brief Description of Drawings

[0027] FIG. 1 is a diagram showing a known transistor configuration having a double gate insulating film made of a high-k material.

FIG. 2 is a diagram showing a known transistor configuration having an Hf-based gate insulating film and a double Poly-Si gate electrode.

FIG. 3 is a diagram for explaining a Fermi level 'piung and a threshold voltage shift caused by this.

FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a diagram for explaining the A1 adhesion treatment according to the embodiment. FIG. 6 (a) is a graph of the AES analysis result of the Al-treated HfSiO (N) film surface, and FIG. 6 (b) is a diagram. 3 is a graph showing processing time dependency of Al film thickness.

[Fig. 7] Comparison of the characteristics of the transistor with the A1 treatment with different film thickness compared to the transistor made by the conventional method without the A1 treatment. Fig. 7 (a) shows the CV power of NMOS Fig. 7 (b) shows the PMOS CV curve.

FIG. 8 is a graph showing the Al deposition time dependence of the flat band voltage (Vl).

[Figure 9] Poly-Si and HfSiON interface attached to the interface between the A1 force MOS structure and Hf

It is a figure which shows the XPS analysis result which investigated the process which diffuses and spreads in a SiON film.

Explanation of symbols

[0028] 1 MISFET (semiconductor device)

11 Si substrate (semiconductor substrate) 12 HfSiON film (High-k film)

13 Al

14 HfSiAlO (N) film (gate insulation film)

15 Gate electrode

16 Extension area

18 Source and drain regions

19 Silicon oxide film (interface layer)

20 channel region

BEST MODE FOR CARRYING OUT THE INVENTION

[0029] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 4 is a schematic cross-sectional view of a MOSFET as an example of a semiconductor device according to an embodiment of the present invention. The semiconductor device (MOSFET) 1 is formed in a predetermined region defined by element isolation (not shown) of the silicon substrate 11 whose main surface is the (100) plane. The MOS FET 1 includes a gate electrode 15, a source / drain impurity diffusion region (hereinafter simply referred to as “source / drain”) 18 formed on the surface of the silicon substrate 11 with the gate electrode 15 interposed therebetween, and a gate electrode 15. And a gate insulating film 14 located between the silicon substrate 11 and the silicon substrate 11.

[0031] The gate insulating film 14 is a thin film that includes three or more kinds of metal elements including the first metal, the second metal, and the third metal, and these three or more kinds of metals are oxidized or oxynitrided. is there. The first metal and the second metal are Hf, Si (metal silicon), Zr, Ta, Ti, Y, or La, and the third metal is A1. In the example of FIG. 4, the first metal is Hf, the second metal is Si, and the gate insulating film 14 is HfSiAlO or HfSiAlON. Side surfaces of the gate insulating film 14 and the gate electrode 15 are covered with sidewalls 17. Note that FIG. 4 is a schematic diagram for explaining the basic configuration of the MOS FET to the last, and a more detailed configuration of the MOSFET 1 will be described later.

FIG. 5 is a manufacturing process diagram of MOSFET 1 shown in FIG. In the example of Figure 5, p-type MOSFET

(PMOS) will be described as an example.

As shown in FIG. 5A, an n-type well region 11a is formed in a predetermined region of the silicon (Si) substrate 11 whose main surface is the (100) plane. Then, as a pretreatment, the natural acid on the surface of the Si substrate 1 After removing the oxidized film with dilute hydrofluoric acid and washing with water, an oxide silicon (chemical oxide) film 19 having a thickness of about 1 nm is formed on the surface of the Si substrate 11. This silicon oxide film 19 has a function of stabilizing the interface between the Si substrate 11 and the upper layer, and is called an interface layer.

An HfSiON film 12 is formed as a high-k film on the oxide silicon film 19. Deposition conditions are, for example, Hf (N (CH)), SiH (N (CH)), NO gas, and carrier gas

3 2 4 3 2 3

(Hf Si) (0 N) film with N2 gas as source gas, substrate temperature of 600 ° C and thickness of about 4 nm

0.6 0.4 0.9 0.1

12 is deposited by chemical vapor deposition (CVD) in a fully oxidized state. Note that oxygen gas is supplied instead of ON gas to form an HfSiO film.

Next, as shown in FIG. 5B, an aluminum (A1) film 13 having a thickness of 0.1 nm to Lnm is formed on the surface of the HfSiON film 12. The thickness of the A1 film 13 is more preferably 0.2 nm to 0.4 nm. Deposition conditions include, for example, a gas obtained by publishing a liquid source of A1 (C4H9) 3 with 3 OOsccm of N2 gas at 20 ° C and 50 Pa on the surface of the HfSiON film 12 with a substrate temperature of 600 ° C. Spray. Then, post-deposition annealing (PDA) is performed at 800 ° C for 30 seconds. Next, as shown in FIG. 5 (c), a polysilicon (Poly-Si) layer 15a is deposited on the surface of the A1 film 13 on the HfSiON film 12 at a substrate temperature of 600 ° C. (CVD ) To a thickness of about lOOnm. Due to the heat during deposition of this Poly-Si film 15a, A1 atoms constituting the A1 film 13 diffuse into the HfSiON film 12, and Hf (first metal), Si (second metal), A1 (third metal) An HfSiAlON film that is an oxynitride of 14 force is formed on the interface layer 19.

Next, as shown in FIG. 5 (d), the Poly-Si film 15a, the HfSiAlON film 14, and the oxide silicon film 19 are patterned by an arbitrary method to obtain an 80 m × 80 m gate electrode 15, A gate structure composed of the HfSiAlON gate insulating film 14 and the oxide silicon interface film 19 is fabricated. Using the gate electrode 15 as a mask, a p-type impurity such as boron (B) is implanted to form a source / drain / extension region (simply called “extension”) 16. The surface region force channel region 20 immediately below the gate electrode 15 extending between the extensions 16 is formed. In the example of Fig. 5, it is a p-type channel region.

An insulating film such as silicon oxide or silicon nitride is deposited on the entire surface and etched back to leave the sidewalls 17. Using the third wall 17 and the gate electrode 15 as a mask, high-concentration p-type impurities are implanted, activation annealing is performed, and source / drain impurity diffusion regions (simply “ 18) (referred to as source 'drain'). Thereafter, the surface is cleaned and a metal film of nickel (Ni), platinum (Pt) or the like is deposited on the entire surface, and silicided by heat treatment to form silicide 21 on the surfaces of the gate electrode 15 and the source / drain 18. Thereafter, although not shown in the drawing, an interlayer insulating film is deposited, a contact plug for energizing the upper layer wiring is formed, and the upper layer wiring is formed to complete the semiconductor device. Silicide 21 is in contact with the bottom of a contact plug (not shown) and serves to lower the electrical resistance of the region.

Fig. 6 (a) is a graph of the AES (Auger electron spectroscopy) analysis results on the surface of the HfSiNO film 12 subjected to the A1 adhesion treatment, and Fig. 6 (b) is a dull showing the treatment time dependence of the film thickness of the A1 film 13. It is fu. The film thickness was measured by spectroscopic ellipso. In the graph of FIG. 6 (a), the leftmost peak is the peak of A1, and the presence of the A1 film 13 is confirmed. Also, from Fig. 6 (b), it can be seen that the film value of A1 increases as the A1 treatment time is increased. Therefore, by controlling the A1 processing time, the A1 film 13 can be formed to a desired film thickness. ~ 1. A1 film thickness of Onm can be formed.

FIG. 7 is a graph comparing the CV measurement results of the MOSFET fabricated according to the embodiment with a conventional HfSiON gate insulating film that does not form the A1 film 13. Figure 7 (a) shows the NMOS CV curve, and Figure 7 (b) shows the PMOS CV curve. In the graph, the solid line is the HfSiNO film that does not form A1 (A1 treatment time Osec), the alternate long and short dash line is the CV characteristic when the A1 treatment time is 5 seconds, the broken line is the CV characteristic when the A1 treatment time is lOsec, and the dotted line is This is the CV characteristic when the A1 processing time is 15 seconds. A sample was manufactured under the same conditions as the manufacturing method shown in FIG. 5 except that the A1 treatment time was changed.

In the case of NMOS, the sample with A1 for 15 seconds shifts the flat band voltage (Vlb) to the positive side by about 0.1 IV compared to the sample without A1. In the same comparison, in the case of PMOS, it is shifted to the positive side by about 1.0V.

Fig. 8 shows a plot of the results plotted in Fig. 7, with the horizontal axis representing A1 adhesion time and the vertical axis representing Vlb. The “ideal values” for PMOS and NMOS in the figure indicate the position of Vl when the Si02 film is used as the gate insulating film. In other words, this is an ideal Vl in the case where no pining occurs in the gate insulating film and there is also a fixed charge.

In NMOS, A1 is attached to the surface of the HfSiO (N) film before depositing the Poly-Si gate. Even if it is placed, Vl hardly changes, but in PMOS, as A1 deposition increases from 0 to 0.3 nm, it linearly changes from 0.35 V to 1. IV.

In the ideal value, the difference in Fermi level between NMOS and PMOS Poly-Si is about 1.0 V, and when converted to Vl, the difference is equivalent to about 1.8 V. In the experimental results, as shown in Fig. 3, in the case of NMOS, when A1 is not attached, the shift amount (AVl) of Vl from the ideal value is about + 0.2V, while in the case of PMOS, It was about 0.5V. It is in a state of being puned!

On the other hand, in the sample in which A1 was deposited for 15 seconds, in the case of NMOS, AVlb = + 0.2V, and in PMOS, AVlb = + 0.2V. Therefore, the Vl difference between NMOS and PMOS is about 1.8V, which is close to the ideal Vlb of 1.8V.

In the embodiment, by setting the A1 adhesion amount to 0.22 nm, the Vl of the PMOS is controlled to an ideal value of 0.9V. On the other hand, Vl of NMOS remains at around -0.7V, and if the force shift amount that remains shifted by about 0.2V is about 0.2V, by changing the channel dose during MOSFET fabrication, Vl Can be controlled to 0.9V, so there is no effect.

Fig. 9 shows the XPS analysis results of examining the state of diffusion into the Hf SiON film 12 during the A1 film 13 force MOS structure fabrication process inserted at the interface between the Poly-Si film 15a and the HfSiON film 12. . As shown in FIG. 9 (a) and FIG. 9 (c), the progress of the process in the sample starts after the pretreatment (HF treatment + SC2 cleaning) and proceeds in the following order.

Process 0: Deposition of Hf SiON film 12 and adhesion of A1 film 13

Process 1: 800 ° C, 30sec post-depot annealing (PDA)

Process 2: Deposition of Poly—Si film 15

Process 3: Activation annealing at 1050 ° C for 1 second

Process 4: Formation of MOS cap

The deposition conditions for the HfSiON film 12 in step 0 were a substrate temperature of 600 ° C, the deposition time was about 7 minutes + α, and the deposition of the Poly-Si film 15a in step 3 was 30 after the PDA and before deposition. Minutes, and the deposition time of Poly—Si was about 11 minutes, and about 20 minutes after the deposition. To do.

[0033] As shown in Fig. 9 (b), XPS analysis was performed on the thus prepared sample at incident angles of 45 ° and 15 °. Figure 9 (C) shows how the ratio of the amount of A1 in the surface area to the amount of A1 at the deeper position decreases as the process progresses, that is, the diffusion of A1 proceeds. From the graph of FIG. 9 (C), it can be seen that the diffusion of A1 diffuses into the HfSiON film 12 during the deposition of the Poly-Si film 15a, which does not proceed by post-deposition annealing. After PDA at 800 ° C, it takes 30 minutes before Poly—Si deposition, so the diffusion of A1 is not due to the effects of PDA! / ヽ.

[0034] In addition, the ratio of the amount of A1 at the 15 ° position to the 45 ° position is approximately 1.0 within one second after the deposition of Poly-Si. This means that A1 diffuses almost uniformly into the HfSiON film 12 and the HfSiAlON film 14 is generated.

As shown in the graph of FIG. 8, it is possible to effectively suppress the MOSFET force Fermi “level” peaking having the HfSiAlON gate insulating film 14 thus fabricated.

[0036] The HfSiAlON gate insulating film 14 is a force that can be formed by CVD itself. By attaching a very thin A1 thin film only to the surface of the HfSi ON film 12, Si atoms are deposited during the deposition of Poly-Si. The influence of diffusing into the lower insulating film can also be prevented.

[0037] As described above, the power of the present invention described based on specific embodiments The present invention is not limited to the above-described embodiments. For example, in the embodiment, the interface film 19 that is the base of the HfSiON film 12 is made of Si02, but the same effect can be obtained even if a SiNO film is used. In addition, the insulating film to which A1 is attached is not limited to the HfSiON film 12, but instead of Hf, it is made of a material containing one or more elements selected from Hf, Zr, Ta, Ti, and Υ. Also good. Further, the metal constituting the oxide or oxynitride may be two or more elements selected from the medium forces of Hf, Zr, Si, Ta, Ti, and Y.

[0038] The gas used when depositing A1 on the HfSiO (N) film 12 is not limited to A1 (C4H9) 3, and AL (CH3) 3 and Al (C2H5) 3 may be supplied! /.

Claims

The scope of the claims

[1] a semiconductor substrate;

A single-layer gate electrode formed on a material including silicon (Si), located on the semiconductor substrate;

A gate insulating film inserted between the gate electrode and the semiconductor substrate;

And the gate insulating film is an oxide or oxynitride of three or more metal elements including the first metal, the second metal, and the third metal

A semiconductor device characterized by that.

[2] The semiconductor device according to [1], wherein the first metal and the second metal are each selected from Hf, Si, Zr, Ta, Ti, Y, and La.

[3] The first metal is Si,

The second metal is selected from Hf, Zr, Ta, Ti, Y, and La

The semiconductor device according to claim 1, wherein:

[4] The semiconductor device according to any one of [1] to [3], wherein the third metal is A1.

[5] An interface layer located between the semiconductor substrate and the gate insulating film

The semiconductor device according to claim 1, further comprising:

[6] The gate insulating film is HfSiAlO or HfSiAlON

The semiconductor device according to claim 1, wherein:

[7] An insulating film made of an oxide or oxynitride of two or more kinds of metal elements including the first metal and the second metal is formed on the semiconductor substrate,

Forming a thin film made of a third metal on the insulating film;

A method for manufacturing a semiconductor device, comprising: depositing a gate electrode film with a material containing silicon on the third metal film.

8. The method for manufacturing a semiconductor device according to claim 7, wherein the step of depositing the gate electrode film includes a step of diffusing the third metal into the insulating film.

[9] The film thickness of the third metal is in the range of 0.1 nm to L Onm.

The method for manufacturing a semiconductor device according to claim 7.

[10] The method for manufacturing a semiconductor device according to [7], wherein the third metal is A1.

[11] The gate electrode film deposition step generates a gate insulating film made of an oxynitride or oxynitride of three or more metals including the first metal, the second metal, and the third metal. The method for manufacturing a semiconductor device according to claim 7, wherein:

[12] The step of forming the third metal film uses at least one of A1 (C4H9) 3, A1 (C2H5) 3, and A1 (CH) 3 as a source gas. 8. A method for manufacturing a semiconductor device according to 7.