WO2007117869A3 - Self-boosting system with suppression of high lateral electric fields - Google Patents

Self-boosting system with suppression of high lateral electric fields Download PDF

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Publication number
WO2007117869A3
WO2007117869A3 PCT/US2007/064215 US2007064215W WO2007117869A3 WO 2007117869 A3 WO2007117869 A3 WO 2007117869A3 US 2007064215 W US2007064215 W US 2007064215W WO 2007117869 A3 WO2007117869 A3 WO 2007117869A3
Authority
WO
WIPO (PCT)
Prior art keywords
isolation
word lines
electric fields
lateral electric
suppression
Prior art date
Application number
PCT/US2007/064215
Other languages
French (fr)
Other versions
WO2007117869A2 (en
Inventor
Ken Oowada
Original Assignee
Sandisk Corp
Ken Oowada
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/394,460 external-priority patent/US7428165B2/en
Priority claimed from US11/394,803 external-priority patent/US7511995B2/en
Application filed by Sandisk Corp, Ken Oowada filed Critical Sandisk Corp
Publication of WO2007117869A2 publication Critical patent/WO2007117869A2/en
Publication of WO2007117869A3 publication Critical patent/WO2007117869A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data

Landscapes

  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

In an improved EASB programming scheme for a flash device (e.g. a NAND flash device), the number of word lines separating a selected word line (to which a program voltage is applied) and an isolation word line (to which an isolation voltage is applied) is adjusted as a function (e.g. inverse function) of distance of the selected word line from the drain side select gate to reduce program disturb due to high vertical and lateral electric fields at or near the isolation transistor when programming word lines closer to the drain side select gate. The selected and isolation word lines are preferably separated by two or more word lines to which intermediate voltage(s) are applied.
PCT/US2007/064215 2006-03-30 2007-03-16 Self-boosting system with suppression of high lateral electric fields WO2007117869A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/394,460 US7428165B2 (en) 2006-03-30 2006-03-30 Self-boosting method with suppression of high lateral electric fields
US11/394,803 US7511995B2 (en) 2006-03-30 2006-03-30 Self-boosting system with suppression of high lateral electric fields
US11/394,803 2006-03-30
US11/394,460 2006-03-30

Publications (2)

Publication Number Publication Date
WO2007117869A2 WO2007117869A2 (en) 2007-10-18
WO2007117869A3 true WO2007117869A3 (en) 2007-12-06

Family

ID=38283334

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/064215 WO2007117869A2 (en) 2006-03-30 2007-03-16 Self-boosting system with suppression of high lateral electric fields

Country Status (2)

Country Link
TW (1) TW200807422A (en)
WO (1) WO2007117869A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7466590B2 (en) 2004-02-06 2008-12-16 Sandisk Corporation Self-boosting method for flash memory cells
US7161833B2 (en) 2004-02-06 2007-01-09 Sandisk Corporation Self-boosting system for flash memory cells
US7511995B2 (en) 2006-03-30 2009-03-31 Sandisk Corporation Self-boosting system with suppression of high lateral electric fields
US7428165B2 (en) 2006-03-30 2008-09-23 Sandisk Corporation Self-boosting method with suppression of high lateral electric fields
CN103106922B (en) * 2012-12-26 2017-05-10 上海华虹宏力半导体制造有限公司 Programming method for separating grid memory array

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997049089A1 (en) * 1996-06-18 1997-12-24 Advanced Micro Devices, Inc. Nand flash memory using floating gate transistors as select gate devices and its bias scheme
US6191975B1 (en) * 1998-12-22 2001-02-20 Kabushiki Kaisha Toshiba Non-volatile NAND type semiconductor memory device with stacked gate memory cells and a stacked gate select transistor
US20050056869A1 (en) * 2003-08-04 2005-03-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory cell matrix, a mehtod for operating the same, monolithic integrated circuits and systems
US20050174852A1 (en) * 2004-02-06 2005-08-11 Hemink Gerrit J. Self-boosting system for flash memory cells
WO2006124525A1 (en) * 2005-05-12 2006-11-23 Sandisk Corporation Selective application of program inhibit schemes in non-volatile memory

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997049089A1 (en) * 1996-06-18 1997-12-24 Advanced Micro Devices, Inc. Nand flash memory using floating gate transistors as select gate devices and its bias scheme
US6191975B1 (en) * 1998-12-22 2001-02-20 Kabushiki Kaisha Toshiba Non-volatile NAND type semiconductor memory device with stacked gate memory cells and a stacked gate select transistor
US20050056869A1 (en) * 2003-08-04 2005-03-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory cell matrix, a mehtod for operating the same, monolithic integrated circuits and systems
US20050174852A1 (en) * 2004-02-06 2005-08-11 Hemink Gerrit J. Self-boosting system for flash memory cells
WO2006124525A1 (en) * 2005-05-12 2006-11-23 Sandisk Corporation Selective application of program inhibit schemes in non-volatile memory

Also Published As

Publication number Publication date
TW200807422A (en) 2008-02-01
WO2007117869A2 (en) 2007-10-18

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