TW200807422A - Self-boosting system with suppression of high lateral electric fields - Google Patents

Abstract

In an improved EASB programming scheme for a flash device (e.g. a NAND flash device), the number of word lines separating a selected word line (to which a program voltage is applied) and an isolation word line (to which an isolation voltage is applied) is adjusted as a function (e.g. inverse function) of distance of the selected word line from the drain side select gate to reduce program disturb due to high vertical and lateral electric fields at or near the isolation transistor when programming word lines closer to the drain side select gate. The selected and isolation word lines are preferably separated by two or more word lines to which intermediate voltage(s) are applied.

Description

200807422 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention generally relates to a non-volatile semiconductor memory of the type of flash EEPROM (Electrically Erasable Programmable Read Only Memory), specifically for The structure and method for operating a NAND type memory cell array. [Prior Art] There are many commercially available non-volatile memory products available today, especially non-volatile memory in the form of small form factor cards that use a flash eppR〇M cell array. product. One popular flash EEPROM architecture uses a NAND array in which a large number of memory cell strings are connected by one or more selective transistors between individual bit lines and a reference potential. Figure 2A shows a portion of this array in plan view. BLO-BL4 (where BL1-BL3 is for a transistor string, for example, NAND strings 11, 13, 15 in Figure 3A are also labeled 12, 14, 16) means a vertical metal bit line to the royal office (not shown) The diffusion bit line is connected. Although four floating gate memory cells are shown in each string, individual strings typically contain 16, 32 or more memory cells or charge storage components, such as floating gates, in a row. The terms "memory unit" and "charge storage element" are used interchangeably herein. The control gate (word) line labeled wl〇-wL3 in Figure 2 (labeled P2 in Figure 2B, Figure 2B is a cross-section along line AA of Figure 2A) and the string selection lines SGD and SGS extend A plurality of strings across the floating gate column, the floating gates are typically polycrystalline (labeled as "·,", 丨 in Figure 2B, for the non-polar side selection transistor 40 and the source side selection transistor 50, Electrically connectable control gate and floating gate (not shown), 119599.doc 200807422

The control gate and floating gate are hereinafter referred to as the drain side select gate (for transistor 40) and the source side select gate (for transistor 5 〇). As shown in Figure 2b, the control gate lines (CG) are typically formed on the floating gates in a self-aligned stack and are capacitively coupled to one another by an intermediate dielectric layer 19. The top and bottom of the string are connected to the bit line and a common source line by means of a transistor, and the floating gate uses a floating gate material (ρι) as its active closed electrode. The periphery is electrically driven. This capacitive coupling between the mother-transistor floating gate (FG) and the control gate ((3)) of the four transistors in each string allows floating by increasing the voltage on the control gate coupled to it. The voltage of the gate rises. During stylization, # is read and verified - in a row or string - individual cells: by setting a relatively high voltage on their respective word lines and by setting a relatively low voltage on a selected word line The remaining cells in the string are turned on so that the current flowing through each string is substantially only dependent on the electrical headroom stored in the address cells below the selected word line. This current is typically detected in parallel for a large number of strings, thereby reading the charge level state in parallel along a galvanic gate column. Examples of nand-type flash memories and their operation are provided in the following U.S. patents/patent applications, each of which is incorporated by reference.

The manner of this is incorporated herein by reference: U.S. Patent No. 5,570,315, 5,774,397, 6, 〇46, 935, 6, 456, 528, and 6, 522, 580. The most common charge storage element of the current flash (tetra) R〇M array is the conductive galvanic gate, which is typically formed of a doped polycrystalline material. However, other (4) having a charge storage capacity may be used, and the (4) is not necessarily and electrically conductive. An example of such an alternative material is nitrite. This unit is described in one 119599.doc 200807422

Takaaki Nozaki et al. "A"_Mb EEPR〇M whh m〇n〇s

Memory Cell f0r Semiconductor Disk Application" IEEE

Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, PP· 497-501. A memory cell of a typical non-volatile flash array is divided into discrete cell blocks that can be erased together. That is, the block contains the minimum number of cells that can be erased together as a single erase unit, although more than one block can be erased in a single erase job. Each block typically stores one or more data page pages defined as the minimum number of units that are subjected to a stylized and read unit as a basic stylized and read unit, although can be programmed or read in a single job. Take more than __ pages. Each page usually stores one: multiple data sectors, and the size of the 4 areas is defined by the host system. An instance is used. The data is a sector of 512 bytes (follow--established with the disk drive) The overhead information of a certain number of bytes on the user data and/or the block (where the HI sector is stored). As in most integrated circuit applications, the flash-emer 〇m array also has the pressure to reduce the area of the substrate in which some of the integrated circuit functions are built. People = want to increase the number of data that can be stored in a given area of the m board. Six denier, θ force, size, memory card and other types of package storage = = increase capacity and reduce size. Another type of data storage data/system memory unit charge storage element stores more than one bit storage window. The allowable (four) or charge of the charge-discharging element is carried out every H. Using four such states can store two bits of data, using eight states to store three bits per H9599.doc 200807422 unit, and so on. A multi-state flash EEPROM structure and operation is described in U.S. Patent Nos. 5,043,940, 5,172,338, 5,570,315, and 6,046,935. A typical architecture of a flash memory system using a NAND structure will include a plurality of NAND arrays, wherein Each array contains several NAND strings. For example, Figure 3A shows only three NAND strings 11, 13, and 15 of the memory array of Figure 2A, but the array can include more than three NAND strings. Each of the NAND strings of Figure 3A includes two select transistors and four memory cells. By way of example, NAND string 11 includes select transistors 20 and 30, and memory cells 22, 24, 26 and 28. NAND string 13 includes select transistors 40 and 50, and memory cells 42, 44, 46 and 48. Each string is connected to the source line by its selection transistor (e.g., select transistor 30 and select transistor 50). A select line SGS is used to control the source side select gate. The various NAND strings are connected to the corresponding bit lines by the select transistors 20, 40 controlled by the select line SGD. In other embodiments, the selection lines do not necessarily need to be shared. The word line WL3 is connected to the control gates of the memory unit 22 and the memory unit 42. Word line WL2 is coupled to the control gates of memory unit 24 and memory unit 44. Word line WL1 is coupled to the control gates of memory unit 26 and memory unit 46. Word line WL0 is coupled to the control gates of memory unit 28 and memory unit 48. Thus, each bit line and corresponding NAND string includes a plurality of rows of the memory cell array. The word lines (WL3, WL2, WL1, and WL0) include a plurality of columns of the array. Each word line is connected to the control gate of each memory cell in the column. For example, word line WL2 is coupled to the control gates of memory cells 24, 44, and 64. 119599.doc 200807422 Figure 3B is a circuit diagram of a number of NAND arrays, each of which is controlled by a common set of word lines. The array of Figures 8 and 3 appears as the top array in Figure (9). As shown in FIG. 3B, each NAND string (eg, 11, 13) in the same array is connected to one of a plurality of bit lines 12, 14, and a common source line, and is shared by a common word. Line set (Wl〇_WL3) control. Each memory unit can store data (analog or digital). When a bit of digital data (in-one memory unit) is stored, the range of possible threshold voltages of the memory unit is divided into two ranges of assigned logical data "1" and "〇". In an example of a NAND flash memory, the voltage threshold is negative after the memory cell is erased and is defined as a logic "丨". The threshold voltage after a stylized operation is positive and defined as logic 0 j α. When the threshold voltage is negative and a read is attempted by applying volts to the control gate, the memory cell will conduct current to indicate Storing logic '. When the threshold voltage is positive and a read operation is attempted, the memory unit will not be V-passed, and this indication stores a logic zero. A memory unit can also store information of a plurality of levels, for example, storing digital data of a plurality of bits. In the case of storing the data at the same level, the range of possible threshold voltages is divided into the number of data levels. For example, if four levels of information are stored, it is expected to be within the four (four) voltage limit range, and each range is assigned to a data value by a difference between multiple (ie, 'more than two) threshold voltage ranges. The memory of the remaining data is called multi-state memory. In the -NAND type: In the case of the L body, the threshold voltage is negative and ::11 after the erase operation. The positive threshold voltage is used for "..., "... and ".." 2 119599.doc 200807422 When stylizing the NAND flash memory cell, the program voltage is applied to the control gate and the NAND string is passed through. Select the grounding (0 volts) for the stylized channel area. Electrons are injected into the floating gate from the channel region below the NAND string. When t electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the cell rises. To ground the channel region of the selected string, ground the corresponding bit line (0 volts) and connect the SGD to a sufficiently high voltage (for example, usually 3 3 volts, this voltage is high: select electricity The threshold voltage of the crystal. To apply the program voltage to the control gate of the program cell, the program voltage is applied to the appropriate word line as described above, and the sub-line is also connected to other NANDs using the same word line. A unit in each of the strings. For example, when the unit 24 of Figure 3A is programmed, the program voltage is also applied to the control idle of the unit ~ because the two units share the same-word line. It is desirable to program a unit on a word line but not to connect to other units (4) of the same word line (for example, β, when the stylized unit 24 is expected but not programmed), a problem arises. The program power (4) is applied to all units connected to the word line: therefore the unselected unit on the word line ("the program unit is not intended to be programmed" can be stylized by the month. For example, she Adjacent to unit 24, unit 44. In the case of a modular unit, there is a concern that the unit 44 may be unintentionally programmed. The unintentional stylization of unselected units on the selected word line is called "program disturb". More usually, "program disturb" is used for Any unfavourable threshold in the positive or negative direction (4)#,&

Shifts can occur during a stylized job and are not necessarily limited to the selected word line. Several techniques can be used to prevent program interruptions. K. D. (4) et al., "A 119599.doc -10- 200807422 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme," Journal of Solid-State

Circuits, Vol 30, No. 11, Nov. 1995, pp. 1 149-55 proposed η \ / a method called "self-improvement" ("SB"). During the run-length using the SB scheme, the channel region of the unselected NAND string is electrically isolated from its corresponding bit line. Next, an intermediate pass voltage (e.g., volts) is applied to the unselected word lines while a high program voltage (e.g., 丨 8 volts) is applied to the selected word line. In this application, the terms "isolation" and "electrical isolation" are used interchangeably and the terms "write voltage", "program voltage" and "programmed voltage" are used interchangeably. The channel region of the unselected NAND string is capacitively coupled to the unselected word line such that there is a voltage present in the channel region of the unselected NAND string (e.g., assuming a coupling ratio of 〇·6, the voltage is six volts). This so-called "self-raising" reduces the potential difference between the channel region of the unselected NAND string and the program voltage applied to the selected word line. Thus, for memory cells in unselected NAND strings and particularly for memory banks 70 in such strings on the selected word line, the voltage across the tunnel oxide is significantly reduced and thus the program is disturbed. Referring to FIG. 3A, when a self-lifting program technique is applied to the memory array of FIG. 38 to program one of the cells on bit line 12, for example, zero volts is applied to bit line 12. A voltage Vdd is applied to the bit line 14 (eg, 3.3 volts p applies a voltage Vdd to the drain select line s (}D to conduct the transistors 20 and 4G and zero volts to the source select s (js to turn off) Transistors 3G and 5G. Assuming that all memory cells 42-48 in the array are in a normal state (eg, 'erased or negative threshold voltage state'), Vdd and selection applied to SGD by 119599.doc 11 200807422 The difference between the threshold voltages of the transistors 40 recognizes the channel potential of all cells in the NAND string between the transistors 40 and 50. For example, if Vdd is 3.3 volts and the threshold voltage of the transistor 4 is volts , the channel potential of all cells 42_48 is charged to 2 volts. The above operation can be called A "precharge" 'This is because the channel potential is precharged to a predetermined potential of about 2 volts in this case. Because of the transistor 5〇 Shutdown and the channel potential of the NAND string reaches - sufficient high value (in The second transistor is (2 volts). The transistor 40 will be automatically turned off, so the channel potential of the memory cell 42_48 becomes floating. Therefore, when the high program voltage Vpgm (for example, 18 volts) is applied to the word line WL2 and will be - intermediate When voltage ¥_ (for example, 1 volt volt) is applied to the remaining word lines, the channel potential of the memory cell 42_48 will be from 2 volts due to capacitive coupling (assuming a coupling ratio of approximately 〇·6) (initial precharge level) Booting or boosting to a value such as 8 volts. Therefore, even if a high voltage (e.g., 18 volts) is applied to the control gate of the memory unit 44, the potential difference between the high voltage and the channel potential is not sufficient. Causes electron tunneling through the oxide to the floating gate of the memory cell 44, thereby preventing program disturb. In a stylized cycle, usually (but not always) from the source side to the drain side, for example A NAND string is programmed from the memory unit 28 to the memory unit 22. When the stylization process is ready to program the last (or near the last) memory unit in the nand string, if the program string has been programmed (eg ' String 1 3) If all or most of the previously programmed units are being disabled, then the floating gates of the previously programmed units have a negative charge. Due to this negative charge on the floating idle, the precharge cannot be completed. This results in a lower initial potential of one of the channel regions below the NAND string and also makes the subsequent self-boosting of the H9599.doc -12-200807422 channel region inefficient. Therefore, the booster of the channel towel of the unselected NAND string may become It is high enough and there may still be a word for the last line "program Wei. For example, when # is applied to WL3, ^ is programmed to disable units 46 and 44 on the string, then these memories Each of the units 44, 46, 48 has a -negative charge on its floating gate, which will limit the level of boost of the self-lifting process and may result in disturbing the program of unit 42. In view of the above problems, as an improvement, a scheme called erased area self-improvement ("EASB") has been proposed. In the EASB scheme, when a high stylized voltage is applied to the word line WL2, to reduce or prevent program disturb with respect to the memory unit 44 on a prohibited string, the volts are applied to the word line WL1 to cause the memory. Unit 46 is turned off. Unit 46 then isolates the channel region of string 13 on the bit line side of cell 与 from the channel region of string 13 on the source line side of cell 46. In other words, the channel regions of cells 42, 44 are isolated from the channel regions of cells 48. Since cells 46 and 48 are more likely to have a negative charge at their floating gates, and thus cells 42 and 44 will not have a negative charge on their floating gates, the channel regions of 5 memory cells 46 and 48 may be reduced. Self-boosting does not affect, at least or less, the channel potential in memory unit 44. Therefore, the channel potential of the channel regions of the memory cells 44 and 42 can be self-raised to a voltage level by the high stylized voltage Vpgm and the pass voltage (for example, at 1 volt volts). The voltage level is higher than when the memory is used. The channel region of body unit 44 is subject to self-improvement in memory cells 46 and 48 and the voltage level achieved by self-improvement in memory cells 42 and 44. This prevents the program from staging the memory unit 24 from being disturbed. 119599.doc -13· 200807422 Figure 4 illustrates the typical EASB program forbidden work. Vdd is applied to bit line 70, thus raising the NAND string and disabling it. The erased area self-elevation is defined as applying a sufficiently low voltage (in this case, volts) to the drain side neighbor of the selected word line (the program voltage Vpgm is applied to the side) to make it programmed and The erased channel area is isolated. The shaded areas in Figures 4 and 5 illustrate the channel area in which the potential or voltage has been raised to a high level. However, when the size of the memory unit is scaled down, the program disturb 脔L becomes more severe, even for the eASB method and its variants. Undesirable phenomena such as gate induced buckling leakage (GIDL), banded tunneling (BTBT), penetration, or any other undesired phenomenon that can cause program disturbances are usually caused by high vertical and lateral directions in or between flash cells. The electrical field is triggered and will become worse as the memory cell is scaled down because the applied voltage used in the flash memory cell cannot be easily scaled down. This resistance scaling constraint tends to increase the electric field as scaling proceeds. This illustration is illustrated in Figure 5. As shown in Fig. 5, btbt & GIDL is a common phenomenon triggered by a high electric field at the junction of the isolation unit (the channel region having a high boost potential is shown as a shaded region in Fig. 5). When the isolation unit is programmed to a high threshold voltage and, or when the boosted channel potential is high, the field at the isolation unit where the control gate is applied to the volts will become larger. This enhancement is triggered by the GIDL or any other phenomenon that causes the program to disturb the high-voltage location. As illustrated in Figure 5, due to the lightning! The undesired carriers generated by the U-electricity % will be injected to the closest to the high-potential smog a from the #电伹路 (usually the unit whose control gate is applied with a relatively high voltage) Therefore, & 'heart, inside the gate. The combination of the low voltage on the word line 119599.doc -14- 200807422 (which isolates the two track regions or regions) and the high boost channel potential (which produces a high zeta potential on the isolation unit) increases the electric field. . The electric field in or between the memory cells is strongly dependent on the (4) power-limited (four) state and the voltage applied to the isolation unit. When the stylization is closer to the gate of the drain side, the vertical electric field at the isolation unit increases. This is because when the program is close to the gate of the drain select gate, the erased channel region or region on the drain side of the isolation unit is small or very small. This means that the capacitance of the erased channel region or region on the drain side of the isolation unit is small, so that the lifting efficiency is high and the high program voltage Vpgm2 boosting effect is more strongly felt. Therefore, when the stylization is closer to the unit of the gate selection gate on the drain side, the program that is enhanced by the memory in the f element or the position of the high power is worse. The scale reduction has also become worse. Therefore, the desired situation provides a stylized solution by which the above difficulties can be alleviated or reduced. SUMMARY OF THE INVENTION As described above, in a conventional stylized scheme such as EASB, when the programming is closer to the unit of the gateless gate selection, the high electric field enhancement scheme disturbing feature is worse. This is because the memory cells are usually programmed in a predetermined order so that the cells closest to the source side selection gates are first programmed and sequentially programmed to the cell closest to the drain side selection gate. . In the case of EASB or any other variation thereof, the word line (to which all defined voltages including the isolation voltage are applied) is kept at a constant distance from the selected word line to which Vpgm is applied. In the case of the EASB method, a low isolation voltage is applied adjacent to the selected word line (hereinafter referred to as "selected word line", and the program voltage 119599.doc -15-200807422 is applied to Vpgm) The word line on the source side and the source side (referred to as "isolated word line" in the text). When choosing a word line close to the gate of the drain side, the EASB method will increase the disturb of the high electric field enhancement program.

Capacitance This is because, as explained above, when the selected word line is closer to the drain side selection gate, the capacitance of the lifted isolation channel of the erased region will be smaller. Since an isolation cell is immediately below a corresponding isolation word line, the distance between the isolation word line and another component (eg, word line, bit or source line, drain or source select gate) also indicates isolation The distance between the unit and this component. One aspect of the present invention is based on the fact that by separating the isolated word line from the selected word line, when stylized closer to the word line of the drain side select gate than when stylizing the word line further from the gate A larger distance to alleviate the above problems is achieved in one embodiment. Typically, separating the isolated word line from the selected word line by a greater distance means separating the isolated word line from the selected word line by a larger number of word lines. More generally, the distance between the isolated word line and the selected word line (or the number of word lines) by staging at least some (eg, two or more) word lines of the word lines The adjustment is performed (e.g., by increasing) as a function of the distance between the selected word line and the drain side selection gate (or the number of word lines). Preferably, the adjustment is such that the distance between the isolated word line and the selected word line (or the number of word lines) is an inverse function of the distance between the selected word line and the bit line (or the number of word lines), and Whether the stylization is sequentially from a unit close to the source line to a unit close to the bit line. For example, the embodiment - the embodiment employs - wherein the stylized sequence of memory cells is programmed in a prescribed order to first select the cell closest to the source side to select the interpole in the stylized path Stylized, H9599.doc -16 - 200807422 and sequentially programmed to the unit closest to the gate selection gate on the drain side. In this embodiment, during a time interval of the stylized cycle, a low isolation voltage is applied to a greater distance from the selected word line (compared to the early time interval of the stylized cycle) The isolation word line. In other words, when the stylized gate is selected toward the drain side, the number of word lines separating the isolation unit from the selected word line can be increased. As a result, the channel area or area on the drain side of the isolation unit will not be too small, so that its capacitance will not be as small as

The excessive vertical and/or lateral electric field due to the application of the program voltage Vpgm can be generated. The above aspect of the present invention can suppress excessive increase in the connection of the isolated word line unit, especially when selecting a close to When the drain side selects the sub-line of the gate for stylization. Also, since the isolated word lines can be physically further from the k-th sub-line, program disturb can be minimized. The above aspects of the present invention can be combined with any type of lifting method currently in existence. For example, another promotion method (for example, the conventional EASB method or its variant) can be applied to a word line selected for stylization and then selected to be closer to the gate line of the bungee selection gate. The position of the isolated word line can be fixed (i.e., the isolation voltage is applied to the same fixed word line). Another option is to increase the number of word lines separating the isolated word line from the selected word line, either continuously or discontinuously or in any other manner, as the stylization proceeds toward the gateless selection gate. In these embodiments, all other word lines between the isolated word line and the selected word line can be set to any voltage. However, if the choice = to maintain the conductivity of the NAND string on the drain side, but not too high to avoid the high electric field in or around the word line, then these embodiments are the most 119599.doc _ 17- 200807422 ^ . If the boosting may not be filled when the gate is selected for the gate side of the stylized side, the relative power may be applied to the word line between the isolated word line and the selected word line. The above-mentioned evil samples are not limited to _ which stylizes the memory unit in the prescribed order, so that in the stylized cycle, the single-green material that is closest to the source-side selection interpole is formed. ^ Close to the scheme of the «side« gate unit. Even if the (fourth) to the infinite order is not prepared, it is so stylized that it avoids the above-mentioned situation that can lead to high lateral electric fields (for example, in the - EAS_ type stylized scheme) When it is too close to the drain side selection gate, the advantage of Datong can be obtained by increasing the isolation word line and the selected word by stylizing _ or more close to the drain side and selecting the word line of the gate. The spacing between the lines to reduce this high vertical and lateral electric field. In accordance with another aspect of the invention, the programming is so such that the isolated word line and the selected word line are separated by at least two word lines. This reduces the high vertical and lateral electric fields that were originally present in the easb class and the privateization method and system. In one embodiment, all word lines between the isolated word line and the selected word line can be set to any voltage. However, this embodiment is most effective if a sufficiently high voltage is selected to maintain the conductivity of the non-polar side NAND string 'but not too high to avoid enhancing the high electric field in or around the isolated word line'. If the boost may not be sufficient when the stylization is selected toward the gate, the relatively high voltage may be applied to the word line between the isolated word line and the selected word line. This aspect of the invention can be combined with any type of lifting method currently in existence. For example, in the initial part of the stylized loop, another lifting method (for example, ea 119599.doc -18 - 200807422 using the easb method or its variant) can be applied to a certain word line. The programming can then be such that in the remainder of the stylized cycle, the isolated word line is separated from the selected word line (to which the program voltage is applied) by at least two word lines. This aspect of the invention is not robust - in which the memory cells are programmed in a predetermined order so that the cells closest to the source side selection gates are first programmed and programmed in the stylized cycle. The scheme that is closest to the unit that selects the gate on the drain side. The gate distance can be selected from the drain side by selecting the number of word lines between the isolated word line and the selected word line (for example, by increasing the number to two or more) The function combines this aspect of the invention with the other aspect described above. The various features described above can be combined into many different combinations. [Embodiment] 'Memory System FIG. 1 is a block diagram illustrating an exemplary memory system in which various aspects of the present invention may be implemented. A memory cell array comprising a plurality of memory cells arranged in a matrix is controlled by a row of control circuits 2, a column of control circuits 3, a c source control circuit 4 and a c_p well control circuit 5. In this example, the memory cell array i is of the NAND type, and this type has been described in the above-referenced "Background" and incorporated herein by reference. The control circuit 2 is connected to the bit line (BL) of the memory cell array to read the data stored in the memory unit (M), determine the state of the memory unit (10) during a program operation, and control the bit The potential level of the line (BL) is to promote stylization or prohibit stylization. The column control circuit 3 is connected to the word line (WL) to select (four) word line (WL), apply 119599.doc -19. 200807422 to take power > 1, apply and control the fine person + ea The programmed voltage of the potential line of the potential line of the diameter line, and the erased electric star with the (4) coupling of the memory unit's minefield (unit p well) formed thereon. c source control

The secondary source is connected to the common source line of the memory unit (5). The C-P well control circuit 5 controls the cell P well voltage. /^ The data stored in the memory unit (M) is read by the row control circuit 2 and = ΓΙ / 〇 line and - data input / output buffer 6 output to external program data borrowed into the memory unit The external two output buffers 6 are outputted from the external 1/0 line and transmitted to the row control circuit 2. The temporary device 0 and the line are connected to a controller 9. The controller 9 includes various types of 己 ° 己 (which includes a volatile random access memory (RAM) 〇) 〇 used to control the command data input of the flash memory device to the command circuit 2 The circuit 7 is connected to an external control line connected to the controller 9. Life Beckham will notify the flash memory of what kind of job is requested. The input machine is transferred to the state machine 8'. The state machine 8 controls the row control circuit 2, the column (four) circuit 3, the pole control circuit 4, the c_p well control circuit 5, and the data output buffer is 6 ° state machine 8 can output Status data of the flash memory, such as READY/BUSY (ready/busy) or simple wrist L (success/failure). (4) Device 9 connection - the host system can be connected to it, for example, a person knows the t-bit camera, Game controller, - cellular phone, -: body player (for example, MP3 player) or a number of assistants. The main start command (such as 'storage data to memory array m or self memory H9599.doc 200807422 The array 1 reads the data and provides or receives the data separately. The controller converts the commands into command signals that can be interpreted and executed by the command circuit 7. The controller also typically includes means for writing user data to the memory. Array or buffer memory for reading user data from a memory array. A typical memory system includes an integrated circuit chip 11A including a controller 9, and one or more of each including a memory array and The integrated circuit, the input/output circuit and the state machine circuit, the integrated circuit chip 1B, can integrate the memory array and the controller circuit in one system on one or more integrated circuit chips. The card can be incorporated as part of the host system, or can be included in a removable memory card that can be detachably inserted into the host system. The card can include the entire memory system, or can be A controller and a memory array with associated peripheral circuitry are provided in a single card. For example, several card implementations are set forth in U.S. Patent No. 5,887,145, the disclosure of which is expressly incorporated herein Figure 6 illustrates the EASB program inhibiting operation of the modified U.S. Patent Application Publication No. 2005/0174852 No. 1. The main difference between the operation of Figure 6 and the operation of the EASB method of Figure 4 is that no isolation voltage is applied. Adjacent to the selected word line of the Vpgm word line, thereby suppressing the 13⁄4 vertical electric field below the edge of the isolation cell of the isolation unit. Instead, the intermediate voltage Vlow(0 V<Vlow&l t; Vpgm) applied to the source side neighbor of the selected Vpgm word line' followed by an isolation voltage applied to the source side neighbor to which the word line is applied by Vlow. Although the modified EASB method of Figure 6 can be successfully Reducing the isolation unit 119599.doc -21· 200807422 However, it is desirable to further suppress the high electric field in the scaled NAND to suppress program disturb, during the bungee side word threading (special centering) Increase the electric field.

Figure 7A is a cross-sectional view of a NAND array illustrating one embodiment of the present invention in which the isolated word line is disposed at a selected word line to which it is applied away from the program voltage vpgm. ® 7B - an enlarged view of the portion of the isolation unit controlled by the Figure 7 isolated isolation word line. A circle with a negative sign indicates the electrons that are programmed and stored in the floating gate of each cell. As illustrated in Figures 7A and 7B, in contrast to the familiar or modified EASB scheme of Figure 6, an isolated low voltage (typically volts) is applied further to a selected or Vpgm word line. The zigzag line and the intermediate voltage are applied to a plurality of word lines located between the isolation and the Vpgm word line. The effect of the effect illustrated by the intermediate voltage (Vlowl, Vlow2, Vlow3) applied to a smaller shaded area below the word line, does not raise the channel area below the word line or raise it to a level 4-6 The use of EASB or modified EASB schemes has a low potential. Therefore, a high electric field at the isolation unit (which is controlled by the isolated word line) can be suppressed as compared with the conventional EASB or the modified EASB operation. In addition, the isolated drain side channel now includes a unit that has been programmed in a previously programmed sequence, which can moderately reduce the enhancement of the V5gm boost by the program voltage Vpgm and reduce the Vpgm boost. In the EASB type or the modified EASB type lifting method of -6, the isolated word line follows the selected word line in a locking step size, so that when the selected word line selects the gate toward the gate side to perform a word line, the word is isolated. The line will also be connected to the pole side 119599.doc •22- 200807422 Select the gate for a word line. In other words, or the boundary between the regions is determined by the position of the selected word line

The isolation channel location at the isolation unit is determined. It should be noted that in the schemes of Figures 7A and 7B, the above is no longer necessary, so that the (four) boundary of the isolated channel region or region can be determined in a manner that is independent of the position of the selected word line. The number of word lines between the isolated and selected word lines can be selected in any manner to reduce high vertical and lateral electric fields. Further, any voltage can be applied to the word lines for the same purpose. Preferably, the voltage applied to the 'intermediate word line is high to maintain the conductivity of the NAND string channel boosted by the immersed side, but not so high that an extremely high electric field is formed at any cell within the NAND string. . Because of this, it is important to look at the extent to which the selected word line is close to the drain side of the selected word line and change the length of the boost channel between the isolated word line and the selected word line (VpgnUfe is added to it). In other words, the optimal position of the isolated word line is defined so that even in the most extreme cases (for example, in a unit that is programmed next to or very close to the gate of the drain side), the isolation unit (which is isolated by the word) Line control) will also not have a high electric field difference. Preferably, the isolation voltage is about or about volts. Vl〇wl,

Vlow2 and Vlow3 are preferably in the range of from 3 volts to a voltage lower than Vpass. Vpass is preferably in the range of from 7 volts to volts, and the mode voltage Vpgm is preferably in the range of from 16 volts to 25 volts. If it is desirable that the voltage applied to the word line between the selected word line and the isolated word line has the same lifting effect on the channel region, then Vlowl, Vlow2, and Vlow3 are in the range of 3 volts to Vpgm. . Figure 8 is a diagram showing an example of a voltage applied to a word line for each selected word line in the case of a 16 word line (WL0 to WL15) NAND string, illustrated by 119599.doc -23-200807422 Another embodiment of the invention. This embodiment assumes that the stylized sequence is from the source side to the drain side word line so that programming is started by selecting the word line WL0 in a stylized cycle, then WL1, WL2 and in this order until WL15 is selected. In the table, each column indicates a word line selected for programming (ie, by applying Vpgm to the selected word line), and an entry in the column and 16 rows indicates when the column is selected. The word line is applied to the voltage of all 16 word lines. For example, the fifth column 1 〇 2 labeled "WL4" on the left side of the table means the word line WL4 selected for programming. The entries in this column of the table contain the following entries: "v vpass" in the rows below "WL〇" and "WL1", "Viso" in the row below "WL2", and "viow" in the row below "WL3" "Vpgm" in the row below "WL4" and "Vpass" in the row below "WL5" to "WL15". This means that when word line WL4 is selected for programming in the stylized cycle, Vpass is applied to word lines WL0 and WL1, isolation voltage Viso is applied to WL2, and program voltage Vpgm is applied to selected word lines WL4 and Vpass to WL5 to WL15. Similarly, every other column in the table of Figure 8 contains entries for different voltages applied to the 16 word lines when one of the remaining 15 word lines is selected for programming. In Fig. 8, Vis 〇 indicates the isolation voltage, Vpgm indicates the program voltage, and Vpass indicates an intermediate voltage '. The intermediate voltage is used to increase the channel area of the cell string to be disabled to reduce program disturb. Figure 8 is an illustration of the voltage applied to each word line in one embodiment. The table in Figure 8 assumes that the stylized sequence follows the basic rules of NAND flash programming, which means that the word line is implemented from the source side to the drain side. In this example 119599.doc -24-200807422, the modified EASB method illustrated in Figure 6 is used to program the word lines WL0 to WL 11, but for the remainder of the buckling side word threading (ie When the word lines WL12 - WL15 are programmed, the channel isolation voltage (usually Viso) is fixed at word line 9. In other words, when word lines WL12-WL15 are programmed, a channel isolation voltage is applied to word line 9 or WL9. This suppresses various types of high electric field enhancement program disturbances at the isolation unit (which is controlled by the isolated word line) during high word threading. Figure 9 is a table illustrating another example of the voltage applied to a selected word line for each program in the case of a 16 word line NAND string to illustrate yet another embodiment of the present invention. As in Figure 8, in the table of Figure 9, each column indicates the word line selected for programming (i.e., by applying Vpgm to the selected word line), and 16 of the columns The entries in the row indicate the voltage applied to all 16 word lines when this word line in this column is selected. In this example, when the word lines WL7-WL15 are programmed, the shift of each of the two word lines of the selected word line causes the Viso to shift the gate to the drain gate by one word line, but when the word line is programmed The WL0-WL6 follows the modified EASB scheme of Figure 6. Viso indicates the isolation voltage, Vpgm indicates the program voltage, and Vpass indicates an intermediate voltage that is used to boost the channel region of the cell string to be disabled to reduce program disturb. Figure 9 is a robust example of a high electric field protection boost scheme, but now Vis is gradually shifting to a higher numbered word line at a slower rate so that the trip side lift does not become too low. Since the channel lifts under Vpgm become too low' then the cells near the isolated word line cannot withstand Vpgm stress and will be disturbed by the process. If the Viso is far enough away from the selected Vpgm word line, it will not appear. 119599.doc -25- 200807422 The program disturbed by the high electric field near the isolated sub-line. 3 Although the (4) 9 embodiment of the towel '# selected word line shifts two word lines, the isolated electric power [applying to the word line to the drain side of the selection gate shifts a word line can make the isolated word line (its Controlled by the isolation unit) when the selected word line shift = the same number of word lines as the two word lines, the drain (4) (four) pole shift _ word, friend and s, when the selected word line shifts η words When the line (where n is a positive number greater than one), the isolated word line is shifted by one word 1 toward the drain side selection gate. The shifting of the isolation voltage can be continuous or intermittent. For some applications, the desired situation is constructed - still * same as the above rule of shifting or irregular shifting example a, in a possible regular pattern, as long as the isolated word line remains in the selected sub-line On the source side, the isolated word line can shift the gate by m gate lines when the selected word line is shifted by p word lines, where m and P are 0 or a positive integer. In the embodiment of FIG. 8, the modified EASB stylization scheme of FIG. 6 is used until the selected word line is closer to the drain side than the source side select gate, or the bit line is closer to the source. The line is closer. Therefore, in Fig. 8, this scheme is followed until the word line WL9 is selected, at which point the isolation voltage becomes fixed. In Figure 9, the modified EASB stylization scheme is followed until the selected word line WL 7 ' at this point shifts the one of the word lines when the selected word line is shifted by two word lines. Thus, in the embodiment of both Figures 8 and 9, the modified EASB stylization scheme of Figure 6 is used until the word line selected for stylization reaches a predetermined position relative to the drain and source side select gates. At this point the isolation voltage becomes fixed or shifted at a lower rate than the selected word line. Preferably, the predetermined position is located at a distance of about 15% of the distance between the drain gate and the source side selection gate from the gateless selection gate of the 119599.doc -26-200807422, or at a distance The line is not greater than a distance of about 15% of the distance between the bit and the source line. Although in the embodiment of FIG. 8, the isolated word line becomes fixed at WL9, when the isolated word line (which controls the isolation unit) is not fully fixed, for example, one word line can be shifted by the selected word line. One of the alternatives (rotation) is alternately selected (rotated) between WL8 and WL9 or between wl9 and WL10 to obtain substantially the same advantages. Alternatively, the rotation may also have an irregular pattern. These and other variations are within the scope of the invention. Although the modified £8 solution of FIG. 6 is used in the embodiment of FIGS. 8 and 9, the unmodified version of FIGS. 4 and 5, and other different variants of the EASB scheme may alternatively be used until the selected word line arrives at one. The above predetermined location. In all of these schemes, the number of word lines (if any) separating the isolated word line from the selected word line remains substantially constant when programmed from the source side to the predetermined position. The problem sought to be overcome is the high vertical and transverse electric fields in the channel region of the isolation unit or near the isolation unit. In another embodiment of the invention, the electric fields can be reduced by separating the isolated word lines (which control the isolation cells) from the selected word lines by two or more word lines. This separation can be performed when the selected word line is close to the drain side and the gate is selected and in other cases. However, preferably in combination with the above features, to further reduce such electric fields, for example, the number of word lines separating the isolated word line from the selected word line can be adjusted in the manner described above. Any voltage can be applied to the word line to separate the isolated word line from the selected word line to reduce these electric fields. Preferably, the voltage applied to the intermediate word line is sufficiently high to maintain the conductivity of the raised NAND string channel on the drain side, but not too much 119599.doc • 27· 200807422 high: to form at any cell within the NAND string Extremely high electric field. For example. The voltage within the range can be applied to one or more of the word lines used to separate the isolated word line from the selected word line: about 3 volts high to Vpass 43 volts high to a voltage lower than Vpass. If the potential of the channel region below these word lines is to be raised, the applied voltage can be between about 3 volts high and the program voltage Vpgm. Preferably, one or more of the word lines of the separated isolation word line and the selected word line are closer to the drain side selection gate than to the source side selection gate, and thus the bit line Closer than the source line. In one embodiment, one or more of the word lines separating the isolated word line from the selected word line are no more than about 15 〇/〇 of the distance between the bit line and the source line. As described above, if the isolation word line is also shifted toward the bit line while the stylization is being made toward the bit line and close to the bit line, there may be a difference between the isolated word line and the drain side selection gate. The inability to prohibit the insufficient improvement of the channel region in the drain side of the transistor string. This is the special case where the electro-crystals between the isolated word line and the selected word line have been programmed such that the transistors have a negative charge on their floating gates, thereby making their channel regions more inefficient. This composite has a shorter effect on the length of the side channel. For example, this will be such that the distance between the isolated word line and the bit line (or the gateless selection gate) is not greater than the distance between the drain side selection gate and the source side selection gate by 1 5%. . In this case, it is preferable to apply a voltage higher than Vpass to the word line separating the isolated word line from the selected word line. Thus, as illustrated in Figure 9, a boost voltage such as Vhil 'Vhi2, Vhi3, Vhi4, or Vhi5 can be applied to the word line separating the isolation ion line from the selected word line. In this particular case, the voltage range of these boosting voltages may be such that Vpass<Vhil<Vhi2<Vhi3<Vhi4< 119599.doc -28 - 200807422

Vhi5<Vpgm. It will be noted from Figure 9 that when the selected word is threaded to approach the drain side select gate and when the drain side channel region becomes shorter and shorter, the isolated word line and the selected word line are separated. The word lines apply increasing voltages (Vhi 1 to Vhi2 to Vhi3 to Vhi4 to Vhi5) to compensate for the continuous decrease (which is also caused by the continuously decreasing length of the drain side channel region). In this case, a voltage higher than Vpass is used to improve the lifting efficiency of the drain side channel. Obviously, higher (or lower) boost voltages other than those in this example can be used and such voltages are also within the scope of the invention. In the above embodiment, the solution generally adopts the following process: • program the memory unit in a predetermined order, so that the unit closest to the source side selection gate is first programmed in the stylized cycle, and It is then programmed to the unit closest to the gate selection gate on the drain side. However, this is not required, and the spacing between the selected word line and the isolated word line can be adjusted in the manner described above and/or by separating the selected sub-line from the isolated word line by two or more word lines. Obtaining substantially the same advantages, even if the stylized sequence of the source-side selection gate to the gate-side selection gate is not followed. The invention has been described with reference to the various embodiments thereof, and it is understood that various modifications and changes may be made thereto without departing from the scope of the invention as defined by the appended claims. All references cited herein are incorporated herein by reference. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a type of memory system in which the memory cell array of the present invention can be constructed and improved in operation. 2A is a plan view of a prior art NAND array. H9599.doc -29- 200807422 Figure 2B is a cross-sectional view of the prior art NAND array of Figure 2A taken along line A-A. FIG. 3A is a circuit diagram showing three NAND strings of FIG. 2A. Figure 3B is a circuit diagram of a number of NAND arrays, each array being controlled by a common set of word lines. Figure 4 is a cross-sectional view of a NAND array illustrating the conventional EASB program inhibit operation. The isolated word line is the source side neighbor of the selected Vpgm word line. A circle with a negative sign indicates the electrons that are programmed and stored in the floating gate of each cell. Figure 5 is a cross-sectional view of a NAND array illustrating the BTBT or GIDL enhanced by the high electric field present in the operation banned by the conventional EASB program of Figure 4. A circle with a negative sign indicates the electrons that are programmed and stored in the floating gate of each cell. Figure 6 is a cross-sectional view of a NAND array, which is illustrated in U.S. Patent Application Publication No. 2005/0174852 A1, which was filed by Gerdt Jan Hemink on February 6, 2004 and published on August 11, 2005. The modified EASB program in the serial number 1〇/774,014) prohibits the operation, and the disclosure is incorporated herein by reference. The intermediate voltage Vlow is applied to the source side neighbor of the word line at Vpgm, and the isolation voltage is applied to the source side neighbor of the word line under Vlow. A circle with a negative sign indicates the electrons that are programmed and stored in the floating gate of each cell. Figure 7A is a cross-sectional view of a NAND array illustrating one embodiment of the invention in which the isolation word lines are disposed away from the selected word line at Vpgm. Figure 7B is an enlarged view of a portion of the isolation unit in the array of Figure 7A. 119599.doc -30- 200807422 A circle with a negative sign indicates the electrons that are programmed and stored in the floating gate of each cell.

Figure 8 is a table illustrating an example of the voltage applied to a selected word line for each program in the case of a 16 word line NAND string to illustrate another embodiment of the present invention. This embodiment assumes that the stylized sequence is from the source side to the drain side word line, and each column indicates the number of selected word lines for programming, and each line indicates the voltage applied to each word line. Vis 〇 indicates the isolation voltage, Vpgm indicates the program voltage, and vpass indicates an intermediate voltage, which is used to boost the channel area of the cell string to be suppressed to reduce program disturb. Figure 9 is a table illustrating another example of the voltage applied to each of the selected word lines in the case of a 16 word line NAND string to illustrate yet another embodiment of the present invention. This embodiment assumes that the stylized sequence is from the source side to the drain side word line, and each column indicates the number of selected word lines for programming, and each line indicates the voltage applied to each word line. In this example, each 2 word line shift of the selected word line shifts the Vis to the drain side select gate by one word line. Viso indicates the isolation voltage, the external card indicates the program voltage, and the external (10) indicates the intermediate voltage, which is used to increase the channel area of the cell string to be suppressed to reduce program disturb. In this application, the same reference numerals are used for the same components for simplicity of explanation. [Main component symbol description] 1 s memory cell array 2 row control circuit 3 column control circuit 119599.doc -31 · 200807422 / 4 c source control circuit 5 cp well control circuit 6 data input / output buffer 7 command circuit 8 state machine 9 controller 10 volatile random access memory (RAM) 11A integrated circuit chip 11B integrated circuit chip 11 NAND string 12 bit line 13 NAND string 14 bit line 15 NAND string 16 bit line 19 middle Dielectric layer 20 Select transistor 22 Memory unit 24 Memory unit 26 Memory unit 28 Memory unit 30 Select transistor 40 Bipolar side select transistor 42 Memory unit 119599.doc 32- 200807422 44 Memory unit 46 Memory Body unit 48 memory unit 50 source side selection transistor 64 memory unit 70 bit line 102 fifth column 119599.doc -33-

Claims (1)

200807422 X. Patent application scope: ^ A method for staging a memory system, the system includes a charge storage transistor string for storing different charge states, the strings comprising a brother-and-second string, The first and second strings are each connected between one of the plurality of bit lines and a source line and are controlled by a plurality of common word lines, the method comprising: The system is programmed by applying a program voltage to the word lines one at a time to program all the transistors in the first string; 』 during the stylization period Ρ θ1, will be (several) first And raising a voltage level to at least some of the transistors in the second string between the selected word line and the one or more bit lines connected to the first and second strings to If the potential of the channel region of the transistor is raised to a value closer to the voltage of the 耘-type voltage or a plurality of values to reduce the program disturbance, and during the stylization, the - is less than the (etc.) - a second potential level of the electric dust level is combined between the selected word line and the source line. The second middle: a small isolated charge storage transistor having a source and a drain, / a voltage level such that the second channel is on the source side of the at least one isolation transistor and the second channel is on the second channel of the second string on the bottom side of the at least one isolation transistor The region is electrically isolated such that the isolated transistor is located at (several) locations separated from the selected word line, Wherein the selected word line of ^ όhai is located between the first position of the first distance _ r of the one bit line and the distance of the one line distance from the one bit line of the one bit line When the second position is at a position, the coupling 119599.doc 200807422 separates the position of the at least one isolation transistor from the second position by a greater number of word lines from the first position to reduce program disturb. 2. The method of claim 1, wherein the second location is closer to the one bit line than to the source line. 3. The method of claim 1, wherein the second distance is no more than about 〇5〇/〇 of the distance between the source line and the one bit line. 4. The method of claim 1, wherein the programming is to program the system by applying the program voltage from the word lines located near the source line to the words located near the one bit line The lines are sequentially applied to the word lines such that the selected word lines are located at a number of locations that gradually decrease from the bit line by a number of distances as the stylization proceeds. 5. The method of claim 4, wherein the programmatically applies the program voltage sigma to the pre-located position between the bit line and the source line and the one bit line When the word line is equal, the position of the at least one isolation transistor is substantially fixed. 6. The method of claim 5, wherein the predetermined location is located at a distance from the one bit that is no greater than about 15% of the distance between the source line and the one bit line. 7. The method of claim 4, wherein when the programmatically applies the program voltage to the word lines between the source line and the predetermined position, the position of the isolated transistor is Not fixed. 8 · If the request item is 7 $, + #, 义万法, where the programmatically applies the program voltage to the word lines located between the source line and the predetermined position, the name is &gt; The position of an isolated transistor moves one word line toward the one bit line toward the one bit 119599.doc 200807422. The method of claim 4, wherein the programmatically applies the program voltage to the word lines between the one bit line and the gate line of the source line and the one bit line. The position of the isolation transistor is shifted by one word line toward the one bit το line when the selected sub-line moves the n-th word line toward the one bit line, and is a positive integer. The method of claim 9, wherein when the programmatically applies the program voltage to the word line between the source line and the predetermined position, the position of the isolated transistor is And moving the parent-child line toward the one bit line to move the word line to the one bit line. 11. The method of claim 9, wherein the predetermined position is not greater than the source line Approximately 15% of the distance from the one bit line. 12. The method of claiming, wherein when the programmatically applies the program voltage to the word lines, the at least one isolated power The crystal is located at a location(s) separating the at least one separate word line from the selected word line. 13. The method of claim 12, wherein the step comprises: (s) a third voltage bit: a coupling to the at least one Separating the word line, wherein the (equal) third voltage level maintains a conductivity of the second channel region extending between the isolation transistor and the selected word line, and does not enhance one of the channel regions 14. The method of claim 13, wherein at least one of the third dust levels is Between 3 volts and the (equal) first boost voltage level. The method of claim 12, further comprising: fitting the third voltage level 119599.doc 200807422 to the at least one gossip + δ each ^ , ^ knife ion line, wherein the (equal) third electric dust level: the potential of the (part) portion of the '-channel region extending between the isolating transistor and the selected word line is raised to be closer to One or more values of the program voltage are used to reduce program disturb. 16. The method of claim 15 wherein at least one of the third electromigration levels is between about 3 volts and the program voltage. The method of claim 4, wherein the isolation transistor and the selected one are separated when the stylized from the predetermined position between the source line and the one bit line toward the one bit line 18. The method of claim 17, wherein when the stylized word line from the moth is adjacent to the source line to the viewing position, if present, the isolation is separated The difference between the number of word lines of the transistor and the selected word line remains substantially odd. 19. The method of claim 17, wherein the position is located at a distance from the one bit line that is not greater than about 15% of a distance between the source line and the one bit line. A method for programming a memory system, the system comprising a charge storage electro-ceramic for storing different states of charge, the (four) string comprising a first and a second string, the first and second strings being each connected to a plurality of bits, between one of the lines and a source line, and controlled by a + common word line', the method comprising: applying a 耘 voltage to the word lines one at a time by a selected word line Stylizing all of the transistors in the first string to program the system; coupling (right) the first boost voltage level to the second &quot;at least some of the selected word line and the one bit line a transistor for raising the potential of the plurality of channel regions of the second 119599.doc 200807422 2::: two to a value of one of the more connected voltages or a plurality of values to reduce the program (4); The second voltage is separated from the second voltage level by the (equal) first voltage level. Between the money selection word line and the source line, the second string is small to one having a source and a immersed charge storage transistor: the Γ position is such that the second string is at least one isolated Source of the crystal:: = one of the first channel regions is electrically isolated from the second string of the at least one isolated transistor; and the -first: channel region on the pole side, the at least one isolated charge storage transistor and The selected word line separates at least two word lines; and combines (s) third voltage bits (four) to the two equal word lines between the selected word line and the isolation transistor, wherein the One of the (equal) third voltage levels of one of the at least two word lines is less than the (equal) first voltage level to reduce program disturb. The method of claim 20, wherein one of the at least two word lines coupled by one of the (etc.) third voltage levels is located from the bit line to the source The line is closer. 22. The method of claim 20, wherein one of the at least two word lines coupled by one of the (equal) third voltage levels is located no greater than the source from the one bit line A distance of about 15% of the distance between the line and the one bit line. 23. The method of claim 20, wherein the programming is to program the system by directing the program voltage from the word lines located near the source line to the words located near the one bit line The lines are sequentially applied to the word lines such that as the stylization proceeds, the selected word lines are located at a number of locations that are gradually decreasing from the 119599.doc 200807422 - bit lines. The method of claim 23, wherein when the programmatically applies the program voltage to 兮玺AA + between a bit line and a predetermined position between the source line and the bit line; The at least one isolated transistor is substantially fixed in position. 25. The method of claim 24, wherein the predetermined position is located at a distance of about 15% of a distance between the source line 不4 and the green one δ hai. . 26. The method of claim 23, wherein the programmatically applies the program voltage between the bit line and the pre-turn position between the source line and the bit line. The position of the at least one isolated transistor is not fixed. The method of claim 26, wherein the programmatically applies the program voltage to the predetermined position between the bit line and the source line and the one of the bit lines. When the word line is equal, the position of the at least one isolation transistor moves one word line toward the bit line when the selected word line moves each word line toward the bit line, and η is a positive integer. 28. The method of claim 27, wherein the programmatically applies the program voltage to the word lines between the source line and the predetermined position, the position of the isolated transistor is The selected word line moves a word line toward the bit line as it moves the parent-child line toward the bit line. The method of claim 26, wherein the predetermined location is located at a distance from the one bit line that is no greater than about 15% of a distance between the source line and the one bit line. </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; And does not raise the potential of one of the channel areas of this part. 31. The method of claim 30, wherein at least one of the third voltage levels is between 3 volts and the (etc.) first boost voltage level. 32. The method of claim 20, wherein the (equal) third voltage level increases the potential of the portion of the second channel region extending between the isolation transistor and the selected word line to be close to the The value of the program voltage - or multiple values to reduce program disturb. 33. The method of claim 32, wherein at least one of the third (four) levels is between 3 volts and the program voltage. 34. The method of claim 20, wherein the third voltage level coupled to the at least two word lines is less than the (etc.) first voltage level to reduce program disturb. The method of claim 2, wherein the third voltage level is (four) the at least three word lines between the selected word line and the isolation transistor, and the center plane is combined to the The (equal) third voltage level of at least three word lines is at the (fourth) level to reduce program disturb. 36. The method of claim 20, wherein the spitting is performed from the source line and the predetermined position between the source and the read toward the one bit line, the isolation transistor and the selected word The number of lines of the number of lines of the knife 37. According to the method of claim 36, wherein the product is added. If + ~ / Tian M ^ A from the right trunk line adjacent to the source line to the predetermined position兮所,登~ Α ^ The difference between the number of word lines from the isolated transistor and the selected sub-line is 119599.doc 200807422 3 8. The method of claim 36, wherein the predetermined position is located from the one bit The line one is not greater than a distance of about Β% of the distance between the source line and the one bit line. 39. The method of claim 20, wherein a portion of the stylized loop for programming the system During the period, the number of word lines separating the isolation transistor from the selected word line is not constant. 40. A method for privately digitizing a memory system, the system including a charge storage transistor for storing different charge states a string containing a first and a second string, the first and the first The two strings are each connected between one of the plurality of bit lines and a source line and are controlled by a plurality of common word lines, the method comprising: applying a program voltage to the selected word line one at a time The word line is programmed to program all of the transistors in the first string; during the stylization, a first boost voltage level is coupled to the selected word line and connected to the first At least some of the transistors in the second string between the one bit lines of the second string increase the potential of the plurality of channel regions of the plurality of transistors in the second string to be closer to the program voltage One or more values to reduce program disturb; and during the stylization, a first voltage level less than the (equal) first voltage level is coupled to the selected word line and the source line At least one of the second string has a source and a drain of an isolated charge storage transistor, and a voltage level of Shai is a poor level of the body. a - channel region on the source side and the second string at the And one of the second channel regions on the pole side is electrically isolated such that the at least one isolation transistor of the 119599.doc 200807422 is located at (several) locations separate from the selected word line; A distance between the at least one isolation transistor and the selected word line is adjusted as a function of a distance of the selected word line from the bit line during stylization of at least some of the word lines. The method of claim 40, wherein the distance between the isolation and the selected word line is adjusted to be an inverse function of one of the distances between the selected word line and the bit line. The materialization-memory (4) system includes a charge storage transistor string for storing different charge states, the strings including a first and a second string, and the first and second strings are each connected to a plurality of Between one of the bit lines and a source line and controlled by a plurality of common word lines, the apparatus includes: a circuit to which the word lines are applied by applying - a program voltage - a selected word line Stylize the system by stylizing all the transistors in the first string During the stylization, the circuit couples the (several) first boost voltage level to the second string between the selected word line and the one of the bit lines connected to the first and second strings At least some of the transistors increase the potential of the plurality of channel regions of the plurality of transistors in the second string to a value or values that are closer to the program voltage to reduce program disturb; and during the stylization The circuit couples a second voltage level less than the (equal) first voltage level to the selected word line and the source line. At least one of the second string has a source and a drain Isolating charge storage electricity 119599.doc 200807422 The crystal 'the second electrical level is such that the second string is on the source side of the at least one isolated transistor - the first channel region and the second string are in the at least one Separating one of the second channel regions on the drain side of the isolation transistor such that at least one isolation transistor is located at (several) locations separated from the selected word line; Wherein the selected word line is located at a first position of the first distance from the one bit line at two different times and at a second distance from the one bit line that is less than the first distance At the two positions, the coupling separates the position of the at least one isolated transistor from the second position by a greater number of word lines than the position of the younger one to reduce program disturb. 43. The device of claim 42, wherein the second location is closer to the one bit line than to the source line. 44. The device of claim 42, wherein the second distance is no greater than about 5% of a distance between the source line and the one bit line. 45. The device of claim 42, wherein the circuit stylizes the system by directing the program voltage from the word lines located near the source line to the word lines located adjacent the one bit line The word lines are applied sequentially such that the selected word line is located at a number of locations where the distance from the one bit line gradually decreases as the stylization proceeds. 46. The device of claim 45, wherein the programmatically applies the program voltage to the word between the bit line and a pre-position between the source line and the one bit line. The position of the at least one isolated transistor is substantially fixed. 47. The apparatus of claim 46, wherein the predetermined location is located at a distance from the one of the bits 119599.doc -10- 200807422 that is not greater than about i5% of the distance between the source line and the one of the bit lines Distance. 48. The device of claim 45, wherein when the programmatically applies the program voltage to the word lines between the one bit line and the predetermined position, the position of the at least one isolated transistor is not fixed. 49. The device of claim 48, wherein when the programmatically applies the program voltage to the word lines between the source line and the predetermined position, the position of the at least one isolated transistor is The selected word line moves one word line toward the one bit line as it moves each word line toward the one bit line. 50. The device of claim 45, wherein the programmatically applies the program voltage to the word between the one bit line and a predetermined position between the source line and the one bit line. In the case of a line, the position of the isolation transistor moves a word line toward the one bit line as the selected word line moves each of the word lines toward the one bit line, and η is a positive integer. The device of claim 50, wherein when the programmatically applies the program voltage to the word lines between the source line and the predetermined position, the position of the at least one isolated transistor is The selected word line moves one word line toward the one bit line as it moves each word line toward the one bit line. 52. The device of claim 5, wherein the predetermined location is located at a distance from the one bit line that is no greater than a distance of about 5 〇/〇 between the source line and the one bit line. 53. The device of claim 42, wherein the at least one isolated transistor is located at least one separate word line from the selected word line when the programmatically applies the program voltage to the word lines. ) at the location. 119599.doc -11 - 200807422 54. The apparatus of claim 53, wherein the circuit couples (s) a third voltage level to the at least one separate word line 'where the (equal) third voltage level causes an edge The second channel region extends a portion of the isolation transistor and the selected word line to maintain conductivity and does not raise the potential of the portion of the channel region. 55. The apparatus of claim 54, wherein at least one of the third voltage levels is between about 3 volts and the (etc.) first boost voltage level. 56. The apparatus of claim 53, wherein the circuit couples at least one of the (equal) third voltage levels to the at least one separate word line, wherein the (equal) to the second voltage level The (several) potential of the second channel region extending over a portion of the isolated electrical body and the selected word line is boosted to a value or values that are closer to the 4 program voltage to reduce program disturb. The device of claim 56, wherein at least one of the third voltage levels is between about 3 volts and the programmed voltage. 5. The apparatus of claim 45, wherein the isolating transistor and the device are separated when the staging is performed from a predetermined position between the source line and the one bit line toward the one bit line The difference in the number of word lines of the selected word line increases. 59. The apparatus of claim 58, wherein the program is separated from the word line of the selected word line if present, from the plurality of word lines adjacent to the source line to the predetermined position. One difference in the number of lines remains approximately constant. 60. The apparatus of claim 58, wherein the predetermined location is located at a distance from the one bit line that is no greater than about 5% of the distance between the source line and the one bit line. 119599.doc -12- 200807422 61. A device for programming a memory system, the system comprising a charge storage transistor string for storing different states of charge, the strings comprising a first and a second string The first and second strings are each connected between a plurality of ones, a friend and a source line, and are controlled by a plurality of common word lines, and the device includes a circuit by using a program Applying the voltage to the word lines one at a time to program all of the transistors in the first string to program the system; the circuit couples the first boost voltage level(s) to the selected word line And at least some of the transistors in the second string between the (five) and 70th lines increase the potential of the plurality of channel regions of the right-handed transistor in the first string of the first string to be closer to the voltage of the program One or more values to reduce program disturb, at least one of the voltage levels isolating the circuit to engage a second voltage level less than the first voltage level between the selected word line and the source line At least one of the first strings has a source a second charge level of the drain-isolated charge storage transistor, wherein the second string is on the source side of the at least one isolated transistor and the second string is isolated from the at least one One of the second channel regions on the drain side of the crystal is electrically isolated, the at least one isolated money storage transistor is separated from the selected word line by at least two word lines; and the selected word line is coupled to the circuit Lightly isolating the at least two word lines between the transistors by (s) a third voltage level, wherein (4) to the third voltage level of the at least two of the at least two word lines _ 119599.doc • 13 - 200807422 Less than the (equal) first voltage level to reduce program disturb. 62. The device of claim 61, wherein one of the at least two word lines facing one of the (etc.) third voltage levels is located from the bit line to the source line Closer. 63. The device of claim 61, wherein one of the at least two word lines to which one of the third voltage levels is coupled is located no greater than the source from the one bit line A distance of about 15% of the distance between the polar line and the one bit line. 64. The device of claim 61, wherein the circuit stylizes the system by patterning the program voltage from the word lines located near the source line to the word lines located near a bit line The word lines are sequentially applied such that when the rendering proceeds, the selected word line is located at a number of locations where the distance from the one bit line gradually decreases. 65. The apparatus of claim 64, wherein the programmatically applies the program voltage sequentially between the one bit line and the pre-turn position between the source line and the one bit line. At least one of the isolated transistors is substantially fixed in position. 66_, as in the case of the spray item 65, wherein the predetermined position is located at a distance from the one bit line that is not greater than a distance of about 5 〇 / 该 between the source line and the one bit line. 67. The apparatus of claim 64, wherein the programmatically applies the program voltage sequentially between the one bit line and the source line and the one bit line - between predetermined positions When the word line is used, the position of the at least one isolation transistor is not fixed. 119599.doc -14- 200807422 68. The apparatus of claim 67, wherein the programmatically applies the program voltage to the gate of the one bit line and the source line and the one bit line/ When the word lines are preliminarily positioned, the position of the at least one isolation transistor moves a word line toward the bit line when the selected word line moves every n word lines toward the bit line, η A positive integer. 69. The apparatus of claim 68, wherein when the programmatically applies the program voltage to the word lines between the source line and the predetermined position, the at least one isolated transistor is positioned The selected word line moves one word line toward the bit line as it moves each word line toward the bit line. 70. The apparatus of claim 67, wherein the predetermined location is located at a distance from the one bit line that is no greater than about Μ% of the distance between the source line and the one bit line. 71. The device of claim 61, wherein the third voltage level causes the second channel region to extend between a portion of the isolation transistor and the selected word line. Conductive without raising the potential of one of the channel regions of this portion. The device of claim 71, wherein at least one of the third voltage levels is between 3 volts and the (etc.) first boost voltage level. The apparatus of claim 61, wherein the circuit faces at least one of the third voltage levels to a charge storage transistor between the isolation transistor and the selected word line. The potential of the portion of the second channel region extending between a portion of the isolation transistor and the selected word line is raised to a value that is closer to one or more values of the program voltage. 74. The device of claim 73, wherein at least one of the third voltage levels 119599.doc -15- 200807422 is between 3 volts and the program voltage. The level of the voltage is reduced to reduce the device of the process, wherein the (specific) third voltage level that is consumed to the at least two word lines is less than the (first) first electrical disturbance. 76? The device of claim 61 wherein the third voltage level is consumed by at least three word lines between the selected word line and the isolated transistor, and : the (equal) third voltage level coupled to the at least three word lines is small: the (equal) first voltage level to reduce program disturb. 77. The device of claim 61, wherein the isolating transistor and the selected word are separated when the staging is performed from the predetermined position between the source line and the one bit line toward the one bit line One of the differences in the number of word lines of the line increases. 78. The apparatus of claim 77 wherein the difference between the number of word lines separating the isolated transistor from the selected word line is substantially when the stylization proceeds from the plurality of word lines adjacent to the ^ line to the predetermined position Constant. 79. The device of claim 77, wherein the predetermined location is located at a distance from the one bit line that is no greater than about 5% of the distance between the source line and the one bit line. 80. The device of claim 61, wherein the number of word lines separating the isolated transistor from the selected word line is not constant during a portion of the programmed cycle for programming the system. 81. A device for programming a memory system, the system comprising a charge storage transistor string for storing different states of charge, the strings comprising a first and a second string, the first and the first The two strings are each connected between one of the plurality of bit lines and a source line and are controlled by a number of common word lines 119599.doc -16- 200807422 'The method includes: a circuit' by using a program Applying a voltage to the word lines one at a time to program all of the transistors in the first string to program the system; During the stylization, the circuit couples the (several) first boost voltage level to the second string between the selected word line and the one bit 7G line connected to the first and second strings. At least some of the transistors increase the potential of the plurality of channel regions of the right dry transistor in the second string to a value that is closer to the program voltage or a plurality of values to reduce program disturb; and in the stylization During the period, the circuit couples a first voltage level less than the (equal) first voltage level to the selected word line and the source line. At least one of the first string has a source and a drain. Isolating the charge storage transistor 'the second voltage level is such that the second string is on the source side of the at least one isolated transistor and the second string is on the at least one isolated transistor (4) The second channel region on the side is electrically isolated ^ such that the at least one isolation transistor is located apart from the selected word line (if the stylization of at least some of the word lines in the word line such as the shoulder, the a distance from the transistor to the selected word line is adjusted to &amp; a function of the distance from the bit line to the bit line. 82. The device of claim 81 wherein the isolation and the selected isolation are adjusted to be a 0 word line between the selected word line and the bit line Distance between One of the letters 119599.doc