WO2007110910A1

WO2007110910A1 - Circuit simulator

Info

Publication number: WO2007110910A1
Application number: PCT/JP2006/306139
Authority: WO
Inventors: Kumiko Teramae; Atsushi Takeuchi
Original assignee: Fujitsu Limited
Priority date: 2006-03-27
Filing date: 2006-03-27
Publication date: 2007-10-04
Also published as: JP4486693B2; JPWO2007110910A1

Abstract

A circuit simulator for simulating a circuit having a linear circuit comprises an LU decomposition result storage area where the analysis of a linear circuit and the results of the LU decomposition of a linear circuit matrix corresponding to the linear section composed of a linear element are associated with each other for each of pseudo-variable step and stored, LU decomposition result read means for reading the results of the LU decomposition corresponding to the pseudo-variable step matching the analyzing step being executing by referring to the LU decomposition result storage area, and first analyzing means for solving a linear circuit matrix equation by using the results of the LU decomposition.

Description

Specification

Circuit simulator

Technical field

TECHNICAL FIELD [0001] The present invention relates to a circuit simulator, and more particularly to a circuit simulator that performs a circuit simulation at a high speed by performing a process according to the characteristics of elements constituting the circuit. Background art

[0002] General-purpose circuit simulators generally simulate the characteristics of the elements that make up a circuit (resistors' capacitance, inductance, etc.) and non-linear characteristics (MOS transistors, diodes, etc.). Yes. In circuit simulation, there was a problem that a large amount of data was generated and processing time was significant.

[0003] Therefore, in order to shorten the simulation time and reduce the data amount of the simulation result, for example, Japanese Unexamined Patent Application Publication No. 2003-337842 (Patent Document 1) describes the first simulation for confirming the basic operation. It is proposed to analyze the results and perform a second simulation with detailed analysis steps when it is determined that detailed analysis of the circuit operation is necessary.

[0004] Further, in order to reduce the analysis time of the designer and improve the convergence of the circuit, for example, Japanese Patent Application Laid-Open No. 2002-197132 (Patent Document 2) describes a circuit under test before performing this analysis. In order to obtain the DC characteristic value of the initial condition, the slow start power supply element that has the slow start characteristic for the power supply element specified in the input data and holds this set potential until a predetermined convergence judgment time after reaching the set potential And perform preliminary transient analysis during the slow start-up period, set the potential of each contact of the circuit under test when the convergence judgment time is reached as the operating point of this circuit under test, and set this operating point after setting this operating point. By executing the analysis, the change of each node of the circuit is calculated during the preliminary transient analysis, and the convergence is judged, so it is proposed to automatically determine whether the operating point of the input data is obtained. RU

[0005] Further, in order to make tracking of the solution curve highly stable and accurate, for example, Japanese Patent Laid-Open No. 2002-318990 (Patent Document 3) discloses a comparison result between an estimated error value and an allowable error value. Based on the above, it is proposed to control the optimal step width by calculating a small step width. I am planning.

Patent Document 1: Japanese Unexamined Patent Publication No. 2003-337842

Patent Document 2: JP 2002-197132 A

Patent Document 3: Japanese Patent Laid-Open No. 2002-318990

Disclosure of the invention

Problems to be solved by the invention

[0006] The circuit is composed of a linear element and a nonlinear element, and the characteristic of the linear element is constant regardless of the current change Z voltage change ratio, but the characteristic of the nonlinear element is the current change Z voltage change. The conversion ratio is not constant. For this reason, when analyzing a circuit, processing is also performed on linear elements at the same time as analysis steps reduced by the characteristics of nonlinear elements. there were.

[0007] In the conventional circuit simulation as described above, a simulation method that considers the difference between the characteristics of a linear element and the characteristics of a nonlinear element has been proposed. Therefore, the characteristics of the elements constituting the circuit are considered. Efficient analysis cannot be performed.

The present invention has been made in view of such problems, and an object of the present invention is to provide a circuit simulator that performs circuit simulation at a high speed by performing processing according to the characteristics of elements constituting the circuit. And

Means for solving the problem

[0009] In order to solve the above problems, the present invention provides a circuit simulator for simulating a circuit including a linear circuit, wherein the linear circuit is analyzed with a linear element for each of a plurality of pseudo-variable steps. An LU decomposition result storage area that stores the LU decomposition result of the linear circuit matrix corresponding to the configured linear part in association with the LU decomposition result storage area, and matches the analysis step being executed with reference to the LU decomposition result storage area An LU decomposition result reading unit that reads the LU decomposition result corresponding to the pseudo variable step and a first analysis unit that solves a linear circuit matrix equation using the LU decomposition result are configured.

[0010] In such a circuit simulator, the analysis step for the linear part of the circuit configuration is analyzed from the start to the end of the analysis process, based on the analysis steps specified by the user, using several analysis steps assumed in advance, In addition, in order to use the pre-calculated LU decomposition result, Analysis processing can be performed at high speed. Therefore, analysis processing of the entire circuit can be performed at high speed.

[0011] As means for solving the above problems, the present invention provides a circuit simulation method,

Also, a computer-readable storage medium storing a program for causing a computer to perform circuit simulation processing can be used.

The invention's effect

[0012] According to the present invention, the analysis step for the linear portion of the circuit configuration is performed from the start to the end of the analysis process, based on the analysis step specified by the user, using several analysis steps assumed in advance, Since the LU decomposition result calculated in advance is used, analysis processing can be performed at high speed. Accordingly, the analysis process for the entire circuit can be performed at high speed. Brief Description of Drawings

FIG. 1 is a block diagram showing a hardware configuration of a simulator according to an embodiment of the present invention.

FIG. 2 is a flowchart for explaining an outline of circuit simulation processing according to the embodiment of the present invention.

FIG. 3 is a schematic diagram for explaining division processing using a circuit matrix.

FIG. 4 is a flowchart for explaining a first analysis process for analyzing a linear circuit performed in step S12 of FIG.

FIG. 5 is a flowchart for explaining the next analysis step determination process.

FIG. 6 is a flowchart for explaining a second analysis process for analyzing the nonlinear circuit performed in step S32 of FIG.

FIG. 7 is a flowchart for explaining the convergence determination process in step S13 of FIG.

Explanation of symbols

[0014] 20 circuit matrix

30 linear circuit matrix

31 Linear element

32 Linear external terminal 40 Nonlinear circuit matrix

41 Nonlinear elements

42 Nonlinear external terminal

51 CPU

52 Memory unit

53 Table Unit

54 Output unit

55 Input unit

56 1 unit

57 Storage device

58 Dryino

59 Storage media

71 First analysis result storage area

72 Second analysis result storage area

75 Join result storage area

80 Pseudo variable step storage area

81 LU decomposition result storage area

100 simulator

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0016] In the present invention, among the elements constituting the circuit, a component part composed of elements having linear characteristics such as resistance, capacitance, and inductance is defined as a linear part, and an element having non-linear characteristics such as a MOS transistor and a diode. By implementing the analysis part for the linear part of the linear part and the nonlinear part of the nonlinear part separately, the circuit simulation process can be performed at a higher speed.

The simulator 100 in the present embodiment has a hardware configuration as shown in FIG. 1, for example. FIG. 1 is a block diagram showing a hardware configuration of a simulator according to an embodiment of the present invention. In FIG. 1, a simulator 100 is a terminal controlled by a computer, and includes a CPU (Central Processing Unit) 51, a memory unit 52, a display unit 53, an output unit 54, and an input unit 55. The communication unit 56, the storage device 57, and the driver 58 are connected to the system bus B.

The CPU 51 controls the simulator 100 according to a program stored in the memory unit 52. The memory unit 52 is composed of RAM (Random Access Memory), ROM (Read-Only Memory), etc., and is obtained by a program executed by the CPU 51, data necessary for processing by the CPU 51, and processing by the CPU 51. Stored data. Also, a part of the memory capacity 52 is allocated as a work area used for processing by the CPU 51.

The display unit 53 displays various information necessary under the control of the CPU 51. The output unit 54 has a printer or the like and is used for outputting various information in accordance with instructions from the user. The input unit 55 includes a mouse, a keyboard, and the like, and is used for a user to input various information necessary for processing with the simulator 100. The communication unit 56 is a device for controlling communication between the simulator 100 and the external device when the simulator 100 is connected to the external device via, for example, the Internet or a LAN (Local Area Network). It is. The storage device 57 is composed of, for example, a hard disk unit, and stores data such as programs for executing various processes.

[0021] A program for realizing the processing performed by the simulator 100 is, for example, a CD-ROM.

Provided to the simulator 100 by a storage medium 59 such as (Compact Disc Read-Only Memory). That is, when the storage medium 59 storing the program is set in the driver 58, the driver 58 reads the program from the storage medium 59, and the read program is installed in the storage device 57 via the system bus B. . When the program is activated, the CPU 51 starts its processing according to the program installed in the storage device 57. The medium for storing the program is not limited to a CD-ROM, and any medium that can be read by a computer may be used. The program for realizing the processing according to the present invention may be downloaded via the network by the communication unit 56 and installed in the storage device 57. [0022] In the circuit simulation process according to the embodiment of the present invention executed by the CPU 51, the circuit is divided into a linear part and a nonlinear part using a circuit matrix, and a first analysis process corresponding to the linear part is performed. The second analysis process is performed on the nonlinear part, and the analysis results are converged by the waveform relaxation method.

FIG. 2 is a flowchart for explaining an outline of the circuit simulation processing according to the embodiment of the present invention.

In the flowchart shown in FIG. 2, the process on the A side is a process for the linear part, and the process on the B side is a process for the nonlinear part. The CPU 51 acquires circuit data according to user input (step Sl) and generates a circuit matrix (step 2). The user inputs connection information for connecting elements and analysis control information such as analysis steps. The CPU 51 performs a dividing process of dividing the circuit into a linear part and a nonlinear part using the circuit matrix (step S3).

First, the process for the linear part on the A side will be described. The CPU 51 initializes the nonlinear external terminal belonging to the nonlinear part in the circuit matrix to zero (0) (step S11), and performs a first analysis process for analyzing the linear circuit (step S12).

In the waveform relaxation loop, it is determined whether or not the force is the initial analysis (step S 12-2).

In the first analysis, the CPU 51 connects the analysis result of the linear circuit as a voltage source to the linear external terminal belonging to the nonlinear circuit (step 15).

On the other hand, in the waveform relaxation loop, when it is the second or later analysis, whether the voltage at the nonlinear external terminal of the nonlinear circuit has converged by executing the convergence judgment process based on the analysis result of the first analysis process. (Step S13), it is determined whether or not the convergence determination result indicates unconvergence (Step S14).

[0027] When the convergence determination result indicates that the convergence is not converged in step S14, the CPU 51 connects the analysis result of the nonlinear circuit to the nonlinear external terminal belonging to the nonlinear circuit as a voltage source (step S15 ).

[0028] On the other hand, if the convergence determination result indicates convergence in step S14, the combined result based on the analysis result of the linear circuit and the analysis result of the nonlinear circuit is output to the combined result storage area 75 (step S16). ), The circuit simulation is terminated. [0029] Next, processing for the nonlinear part on the B side will be described. After step S3, the CPU 51 initializes the linear external terminal belonging to the linear part in the circuit matrix to zero (0) (step S31), and performs a second analysis process for analyzing the nonlinear circuit (step S32).

[0030] In the waveform relaxation loop, it is determined whether or not the force is the first analysis (step S32-2).

In the first analysis, the CPU 51 connects the analysis result of the nonlinear circuit as a voltage source to the nonlinear external terminal belonging to the linear circuit (step 35).

On the other hand, in the waveform relaxation loop, when the analysis is performed for the second time and thereafter, the convergence judgment process is executed based on the analysis result of the second analysis process, and the voltage at which the linear external terminal voltage of the linear circuit has converged. Judgment is made (step S13), and it is judged whether or not the convergence judgment result indicates unconvergence (step S14).

[0031] When the convergence determination result indicates that the convergence is not converged in step S14, the CPU 51 connects the analysis result of the linear circuit to a linear external terminal belonging to the linear circuit as a voltage source (step S35).

On the other hand, when the convergence determination result indicates convergence in step S14, the combined result based on the analysis result of the linear circuit and the analysis result of the nonlinear circuit is output to the combined result storage area 75 (step S16). ), The circuit simulation is terminated.

[0033] The dividing process for dividing the circuit into a linear part and a nonlinear part using the circuit matrix in step S3 of FIG. 2 and the coupling process by the waveform relaxation loop will be described with reference to the schematic diagram shown in FIG. FIG. 3 is a schematic diagram for explaining division processing using a circuit matrix.

In FIG. 3, for example, when the non-linear portion is configured as a subcircuit, the CPU 51 describes the circuit configuration with respect to the circuit matrix 20 of the entire circuit generated in step S2 of FIG. The data capacity of the circuit is divided by deleting the sub-circuit that calls the nonlinear circuit, thereby dividing the linear circuit part and the nonlinear circuit part.

[0035] For example, if the circuit has a circuit configuration in which PCB (Printed Circuit Board) and LSI (Large Scale Integration) are integrated, the LSI circuit mounted on the PCB is defined as a sub-circuit. The circuit configuration data power that describes the circuit configuration is also modeled by integrating it with the LSI by calling the subcircuit.

[0036] In addition to resistors, capacitors, and inductances, LSI interiors use non-linear elements such as mosfet. is described. In such a circuit model, the external terminal of the subcircuit is the connection part to the PCB (such as a package pin). A small resistor is connected in series at the connection between the PCB and LSI.

[0037] Therefore, by dividing the linear circuit portion and the non-linear circuit portion by setting the circuit matrix that can also obtain the circuit configuration power from which the sub-circuit is removed as the linear element portion 31 and the portion corresponding to the LSI as the non-linear element portion 41. can do.

Then, a nonlinear circuit matrix 40 is generated by the nonlinear element unit 41, the nonlinear external terminal unit 42, and the linear terminal unit 32. In addition, a linear circuit matrix 30 is generated by the linear element unit 31, the nonlinear external terminal unit 42, and the linear terminal unit 32.

[0039] The linear circuit matrix 30 and the non-linear circuit matrix 40 generated in this way, that is, separated from the circuit matrix 20, are stored in predetermined storage areas, respectively, and the first analysis process and the second analysis process are performed. And the waveform relaxation loop (repeating process from step S12 to step S15 and repeating process from step S32 to step S35 in FIG. 2).

In the processing for the linear part on the A side in FIG. 2, the linear circuit matrix 30 is referred to. In step S11, the nonlinear external terminal 42 of the linear circuit matrix 30 is initialized to OV (voltage zero), and in step S12, the linear circuit is analyzed using the linear circuit matrix 30 (first analysis process). Also, in step S15, the nonlinear circuit analysis result obtained in step S32 (nonlinear external terminal voltage) is obtained until the nonlinear external terminal part 42 (nonlinear external terminal voltage) of the linear circuit matrix 30 is converged by the waveform relaxation loop. Voltage) is set to the nonlinear external terminal portion 42 of the linear circuit matrix 30.

Similarly, in the process for the nonlinear part on the B side in FIG. 2, the nonlinear circuit matrix 40 is referred to. In step S31, the linear external terminal 32 of the nonlinear circuit matrix 40 is initialized to 0 V (voltage zero), and in step S32, the nonlinear circuit is analyzed using the nonlinear circuit matrix 40 (second analysis process). Also, in step S35, until the linear external terminal 32 (linear external terminal voltage) of the nonlinear circuit matrix 40 is converged by the waveform relaxation loop, the linear circuit analysis result (linear external terminal voltage) obtained in step S12 is converged. ) Is set in the linear external terminal portion 32 of the nonlinear circuit matrix 40.

In this embodiment, the voltage at the linear external terminal is defined as a polygonal power supply, and the nonlinear external terminal Connect to. Similarly, the voltage at the nonlinear external terminal is defined as a polygonal line power supply and connected to the linear external terminal.

[0043] Therefore, by using the analysis results of the other, it can be considered that the linear circuit matrix 30 and the nonlinear circuit matrix 40 are combined when the voltages at the linear external terminal 32 and the nonlinear external terminal section 42 converge. it can.

Next, the first analysis process for analyzing the linear circuit performed in step S12 of FIG. 2 will be described with reference to FIG. FIG. 4 is a flowchart for explaining a first analysis process for analyzing the linear circuit performed in step S12 of FIG.

[0045] The ratio of the voltage change to the current change in the linear portion is constant regardless of the voltage. Therefore, in the first analysis process shown in FIG. 4, several types of analysis steps are prepared in advance as pseudo-variable steps, and the linear circuit matrix 30 is calculated and stored in the storage area for each analysis step. Repeat the process of finding the solution of the circuit equation with reference to the linear circuit matrix 30 corresponding to.

First, the CPU 51 sets the analysis step designated by the user as At (step S51). The CPU 51 acquires At from the analysis control information acquired from the user in step S1 in FIG. 2 and sets it as the analysis step.

[0047] The CPU 51 determines a plurality of pseudo variable steps AtZ2, At / 4, ···, 2Δt, 4Δt, ··· using the analysis step At, and stores the pseudovariable steps. Store in area 80 (step S52). For analysis step At specified by user, 1Z2, 1/4, 1/8, 1/16, ..., 2 times, 4 times, 8 times, 16 times, etc. A multiple in a ratio sequence may be determined in advance as a pseudo variable step. Also, for analysis step At specified by the user, 1/2, 1/3, 1/4, 1/5, ..., 2 times, 3 times, 4 times, 5 times, ... Thus, it is also possible to predetermine the multiple of the arithmetic progression as a pseudo variable step. In this way, quantization is performed as a plurality of pseudo-variable steps.

[0048] Then, the CPU 51 calculates circuit matrix elements corresponding to each pseudo-variable step, and as a result of LU-decomposing the circuit matrix elements, the circuit matrix after LU decomposition is associated with the pseudo-variable steps and LU-decomposed. The result is stored in the result storage area 81 (step S53).

The CPU 51 sets the analysis step Δt to the current analysis time time-pre. Also, User force Acquired analysis control information force Obtain the time from the start to the end of the analysis and set it to the final analysis time time-end.

[0050] Thereafter, the CPU 51 determines whether or not the current analysis time time-pre has reached the final analysis time time-end (step S54).

[0051] When the current analysis time time-pre becomes the final analysis time time-end, the first analysis process is terminated. On the other hand, if the current analysis time time-pre is not the final analysis time time-end in step S54, the CPU 51 searches the LU decomposition result storage area 81 for a pseudo variable step that matches the analysis step At, The LU decomposition result corresponding to the pseudo variable step is read (step S55).

[0052] Then, the CPU 51 obtains a converged solution by performing Yuton iteration while performing forward substitution and backward substitution on the circuit equation using the LU decomposition result read from the LU decomposition result storage area 81 (step S56). ). The CPU 51 outputs the convergence solution as the first analysis result to the first analysis result storage area 71 (step S57).

[0053] Thereafter, the CPU 51 sets the analysis step At to the previous step At-pre, performs the next analysis step determination process (step S58), and returns to step S54.

The next analysis step determination process will be described with reference to FIG. FIG. 5 is a flowchart for explaining the next analysis step determination process. In FIG. 5, the CPU 51 sets twice the previous step Δt—pre as the next step Δt—next (step S61).

[0055] Then, the CPU 51 determines whether the power exceeds the current analysis time time-pre and the next step At-next, which is the value of the broken line power supply. S62). If the next defined time time-def of the broken line power supply is not exceeded, the process proceeds to step S64.

[0056] On the other hand, if the next defined time time-def is exceeded in step S62! /, The next defined time time-def will be entered in the next step At-next. A value obtained by subtracting the current analysis time time_pre is set (step S63).

[0057] By such a determination in step S62, the analysis step in a state where there is no waveform change can be extended.

Then, the CPU 51 refers to the pseudo variable step storage area 80 and defines it in advance. The pseudo-variable step closest to the next step Δ t—next is selected, the pseudo-variable step of the value is selected, the pseudo-variable step is set as the analysis step At (step S64), and the next analysis step is determined. The process ends.

Next, the second analysis process for analyzing the nonlinear circuit performed in step S32 in FIG. 2 will be described with reference to FIG. FIG. 6 is a flowchart for explaining the second analysis process for analyzing the nonlinear circuit performed in step S32 of FIG.

[0060] The ratio of the voltage change to the current change in the nonlinear portion is not constant. Therefore, in the second analysis process shown in FIG. 6, the ratio of the voltage change to the current change in the non-linear part is large! In the state, the analysis step is emphasized, and in the state where this ratio is small, the analysis step is enlarged. In the analysis step, the elements of the nonlinear circuit matrix are calculated, LU decomposition is performed, and the solution of the circuit equation is obtained repeatedly.

First, the CPU 51 sets an analysis step designated by the user as At (step S71).

The CPU 51 sets the analysis step Δt to the previous step Δt-pre and the current analysis time time-pre. Also, the time from the start to the end of the analysis control information force analysis acquired from the user is acquired and set to the final analysis time time-end. Thereafter, the CPU 51 determines whether or not the current analysis time time-pre has reached the final analysis time time-end (step S72).

[0063] When the current analysis time time-pre becomes the final analysis time time-end, the second analysis processing is terminated. On the other hand, if the current analysis time time-pre is not the final analysis time time-end in step S72, the CPU 51 calculates circuit matrix elements of the nonlinear circuit matrix 40 and performs LU decomposition (step S73).

[0064] Then, the CPU 51 can obtain a convergent solution by performing -Yutton iteration while performing forward substitution and backward substitution (step S74). Newton iteration modifies variable values. The CPU 51 outputs the converged solution as the second analysis result to the second analysis result storage area 72 (step S75).

Thereafter, the CPU 51 performs the next analysis step determination process (step S76), and returns to step S72.

Next, the convergence determination process in step S13 of FIG. 2 will be described with reference to FIG. Figure 7 is the same as Figure 2. It is a flowchart for demonstrating the convergence determination process in step S13.

[0067] When the convergence determination process is executed after the first analysis process in step 12 in FIG. 2, the first analysis result storage area 71 is referred to, and after the second analysis process in step 32 in FIG. When it is executed, the second analysis result storage area 72 is referred to. The external terminal voltage storage area 77 used by the convergence judgment process is used for the process for the linear part (A side in Fig. 2) and for the process for the nonlinear part (B side in Figure 2). And having a region.

In FIG. 7, for convenience of explanation, for example, the linear external terminal and the non-linear external terminal are collectively referred to as external terminals, and linear and non-linear are omitted.

[0069] The CPU 51 obtains the voltage of the previous external terminal from the external terminal voltage storage area 77 (step S82). Further, the CPU 51 refers to the first analysis result storage area 71 or the second analysis result storage area 72, acquires the voltage of the external terminal from the current analysis result, and stores it in the external terminal voltage storage area 77 (step S83). ).

[0070] Then, the CPU 51 calculates the difference between the current external terminal voltage and the previous external terminal voltage (step S84), and determines whether the difference is within the allowable error range (step S84). Step S85). If the difference is not within the allowable error range, the CPU 51 sets non-convergence as the convergence determination result (step S85-4).

On the other hand, if it is determined in step S84 that the difference is within the allowable error range, the CPU 51 sets convergence as a convergence determination result (step S86).

As described above, in the present invention, in the processing for the linear portion, an analysis step that can be set in advance is created as a plurality of pseudo variable steps, and the LU decomposition result for the linear circuit portion at each pseudo variable step is calculated. .

[0073] Therefore, it is not necessary to perform LU decomposition at the pseudo variable step that is actually set as the analysis step in the first analysis process for analyzing the linear circuit each time the first analysis process is executed. Therefore, the processing time and the load on the CPU 51 can be reduced, and high-speed processing can be realized.

Further, as shown in FIG. 3, since the linear circuit matrix 30 and the non-linear circuit matrix 40 are generated from the circuit matrix 20, it is possible to separately execute the process for the linear circuit and the process for the non-linear circuit. Become. Therefore, the processing for the linear circuit depends on the characteristics of the nonlinear element. Instead, processing can be performed.

The present invention is not limited to the specifically disclosed embodiments, and various modifications and changes can be made without departing from the scope of the claims.

Claims

The scope of the claims

[1] A circuit simulator for simulating a circuit including a linear circuit,

For the analysis of the linear circuit, an LU decomposition result storage area for storing the LU decomposition result of the linear circuit matrix corresponding to the linear part composed of linear elements corresponding to each of the plurality of pseudo variable steps, and

LU decomposition result reading means that reads the LU decomposition result corresponding to the pseudo variable step that matches the currently executed analysis step with reference to the LU decomposition result storage area, and a linear circuit matrix using the LU decomposition result A circuit simulator having a first analysis means for solving an equation.

[2] pseudo variable step means for generating the plurality of pseudo variable steps using a predetermined basic step;

First matrix element calculation means for calculating a linear circuit matrix element for each of the plurality of pseudo variable steps;

LU decomposition means for performing LU decomposition on the linear matrix based on the linear circuit matrix elements;

LU decomposition result storage means for storing the LU decomposition result obtained by the LU decomposition means in association with the LU decomposition result storage area for each of the plurality of pseudo variable steps generated by the pseudo variable step means. The circuit simulator according to claim 1, further comprising:

[3] A pseudo variable step storage area for storing the plurality of pseudo variable steps generated by the pseudo variable step means;

3. The circuit simulator according to claim 2, further comprising: a next analysis step determining unit that determines a next analysis step for simulating the linear portion by referring to the pseudo variable step storage area.

[4] The next analysis step determining means, wherein the pseudo variable step closest to the next step obtained by extending the previous step is selected and determined as the next analysis step. Circuit simulator.

[5] When the circuit is composed of a mixture of a linear part and a nonlinear part, the circuit is connected to a line. 2. The circuit simulator according to claim 1, further comprising a dividing unit that divides the shape part and the nonlinear part.

[6] The dividing means includes

6. The circuit is divided by generating a linear circuit matrix corresponding to the linear part and a nonlinear circuit matrix corresponding to the nonlinear part using a circuit matrix of the circuit. The circuit simulator described.

[7] second analysis means for solving a nonlinear circuit matrix equation for the nonlinear part;

The circuit simulator according to claim 1, further comprising a convergence determination unit that determines whether the first analysis result by the first analysis unit or the second analysis result by the second analysis unit has converged. .

[8] second analysis means for solving a nonlinear circuit matrix equation for the nonlinear part;

Convergence determination means for determining whether or not the first analysis result by the first analysis means or the second analysis result by the second analysis means has converged,

When the convergence determination means determines that the first analysis result by the first analysis means does not converge, the second analysis result by the second analysis means is connected to a nonlinear external terminal belonging to the nonlinear portion as a voltage source. The circuit simulator according to claim 1, further comprising first external terminal connecting means.

[9] second analysis means for solving a nonlinear circuit matrix equation for the nonlinear part;

When it is determined by the convergence determining means that the second tail analysis result by the second analysis means does not converge V ヽ, the first external analysis result by the first analysis means is used as a voltage source and the linear external The circuit simulator according to claim 1, further comprising second external terminal connection means for connecting to the terminal.

[10] second analysis means for solving a nonlinear circuit matrix equation for the nonlinear part;

When the first analysis result by the first analysis means has converged by the convergence determination means 2. The circuit simulator according to claim 1, wherein when the determination is made, the first analysis result and the second analysis result by the second analysis means are combined.

11. The circuit simulator according to claim 7, wherein the second analysis means calculates a nonlinear circuit matrix element and performs LU analysis for each analysis step.

[12] A circuit simulation method for simulating a circuit composed of a linear part and a nonlinear part,

LU decomposition result storage procedure for storing the LU decomposition result of the linear circuit matrix corresponding to the linear part composed of linear elements in the LU decomposition result storage area in correspondence with the plurality of pseudo variable steps;

An LU decomposition result reading procedure for reading the LU decomposition result corresponding to the pseudo variable step that matches the currently executed analysis step with reference to the LU decomposition result storage area; and a linear circuit matrix using the LU decomposition result A circuit simulation method having a first analysis procedure for solving an equation.

[13] A computer-readable storage medium storing a program that causes a computer to perform a circuit simulation process for simulating a circuit including a linear circuit.

For the analysis of linear circuits, the LU decomposition result storage procedure for storing the LU decomposition result of the linear circuit matrix corresponding to the linear part composed of linear elements in the LU decomposition result storage area for each of the pseudo variable steps. When,

An LU decomposition result reading procedure for reading the LU decomposition result corresponding to the pseudo variable step that matches the currently executed analysis step with reference to the LU decomposition result storage area; and a linear circuit matrix using the LU decomposition result A computer-readable storage medium storing a program for executing a first analysis procedure for solving an equation.