JPH10240796A - Circuit simulation method and record medium for recording circuit simulation program and circuit simulation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain variation analysis on which the variation of electric characteristic value being process data corresponding to a wiring capacity or a writing resistance or the like is reflected. SOLUTION: A net list in which parasite element values are described with functions by using process data (a button capacity per a unit writing area or the sheet resistance of wiring or the like) corresponding to the parasitic element values of a wiring capacity or a writing resistance or the like as a variable is generated from layout data, and worst case analysis is operated by using this. That is, the variation width of the variable of each parasitic element value described with functions is previously set (P2), either the maximum value or the minimum value decided by this is used as the central value of the variable, the central values are substituted in the variable only by the number of all the combination of the central value, and the parasitic element value is calculated (P3), and also circuit characteristic analysis (circuit simulation) is operated (P4). Thus, the variation of circuit characteristics corresponding to the variation of the variable being process data is obtained (P7).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit simulation method for simulating the operation of an integrated circuit using a netlist extracted from data indicating a layout pattern of an integrated circuit, and a recording medium storing a circuit simulation program. And a circuit simulation apparatus.

[0002]

2. Description of the Related Art In a development process of a semiconductor integrated circuit, an operation of verifying a design result by a circuit simulation or the like is performed. In the conventional circuit simulation technology, a circuit connection is represented by a netlist (that is, connection information), and when a bias condition or a command to be analyzed is input,
It has a function of establishing a node equation of the circuit, executing a matrix operation based on the node equation, obtaining a voltage value and a current value of each node, and outputting a result. A circuit simulation program having such a function is SPICE, which is developed by UCB (University of California, Berkeley) and whose source code is open to the public.
(Simulation Program with Integrated Circuit Empha
(short for sis) is widely and generally known.

A tool having a function of extracting a netlist including circuit component elements and circuit connection information required for verifying a design result of an integrated circuit by the above-described circuit simulation from layout data is commercially available.

As a conventional tool for extracting a netlist including circuit component elements and circuit connection information from layout pattern data of a semiconductor integrated circuit, for example, Cadence Design Systems (Cadence Design Systems) is known.
Analysis with netlist extraction function such as Dracula (trade name) of Ems) and CheckMate (MaskPE) (trade name) of Mentor Graphics Tools are commercially available.

In the extraction of the netlist, the parasitic elements (specifically, the parasitic capacitance and the parasitic resistance) of the wiring section have been neglected before. However, in recent years, it is necessary to consider these parasitic elements in verification by a circuit simulation or the like. The importance of has been recognized. For this reason, a function of extracting a netlist in consideration of the parasitic capacitance and the parasitic resistance of the wiring portion from the layout data has been added to the commercially available tools. Further, Japanese Unexamined Patent Publication No.
In Japanese Patent No. 1444941, a parasitic resistance of a wiring or the like is accurately extracted from mask pattern data (layout data), and a value of the parasitic element is evaluated and determined based on a relationship between the extracted parasitic element and a driving element. And determine
A data processing device capable of generating a simulation netlist and the like has been disclosed. Further, Japanese Patent Application Laid-Open
JP-A-216958 also discloses a logic / circuit design support apparatus capable of obtaining transistor-level logic / circuit drawing data including back-annotated parasitic capacitance and parasitic resistance information from layout pattern data (layout data). .

Hereinafter, a conventional netlist extraction method for extracting a netlist describing the configuration of an integrated circuit to be subjected to circuit simulation from layout data in consideration of the parasitic capacitance and resistance of the wiring portion as described above ( Hereinafter, a “conventional example” will be described.

When extracting a netlist from layout data, a file (hereinafter referred to as a "rule file") that describes extraction rules such as rules for extracting parasitic capacitance and parasitic resistance from layout data is usually prepared. You. The rule file contains process data such as wiring capacitance per unit area or unit length, wiring resistance, and sheet resistance. Based on the process data and information obtained from the layout data, each node of the circuit to be designed is , Or the value of the parasitic resistance between the nodes is calculated.

FIG. 3 shows an example of a wiring structure in an integrated circuit from which a netlist is extracted. FIG. 3A is a top view showing an aluminum wiring (Al wiring).
(B) is a cross-sectional view of the Al wiring taken along the line XX. In the example shown in this figure, the Al wiring 100 is formed on a silicon substrate (Si substrate) 103 via an interlayer insulating film 102. When extracting the netlist from the layout data, the distributed constant circuit realized by the layout pattern indicated by the layout data is approximated by a predetermined lumped constant circuit based on the extraction rule specified in the above-described rule file. Now, in this conventional example, based on an approximate model specified as an extraction rule, the number of wiring division stages, and the like, as shown in FIG.
And 20 are set on the Al wiring 100 to divide the Al wiring 100 at these nodes, and add a resistor R10 between the nodes 10 and 20, and add a capacitance Cb + Cf1 + Cf2 between the node 20 and the Si substrate 103, respectively. Fig. 3
Is approximated by an L-type network (hereinafter, this approximation is referred to as “L-type approximation”). in this case,
The wiring structure shown in FIG. 3 is represented by an equivalent circuit shown in FIG. Here, the resistance R10 is the wiring resistance existing between the nodes 10 and 20 (see FIG. 3A), and the capacitance Cb is the capacitance existing between the bottom surface of the Al wiring 100 and the Si substrate 103 (“bottom capacitance”). ), And the capacitances Cf1 and Cf2 are capacitances (referred to as “fringe capacitances”) between the side wall surface of the Al wiring 100 and the Si substrate 103 (see FIG. 3B). In the example shown in FIG.
= Cf2.

In the rule file, an approximation model such as the L-type approximation, the number of division stages, and the like are set. In addition, electric characteristic values determined by a process for manufacturing an integrated circuit, that is, a sheet of the Al wiring 100 are set. A resistance value, a bottom capacitance value per unit wiring area, a fringe capacitance value per unit wiring fringe length (perimeter), and the like are stored. Based on the information included in such a rule file, the wiring resistance R10, the bottom capacitance Cb, and the fringe capacitances Cf1 and Cf2 can be calculated using the layout data. That is, in the above-described conventional example, the wiring resistance R10 is calculated as “sheet resistance value × wiring length / wiring width”, and the bottom capacitance Cb is obtained.
Is "Bottom capacitance value per unit wiring area x Wiring area"
Then, the fringe capacitances Cf1 and Cf2 can be calculated by “fringe capacitance value per unit wiring fringe length × wiring fringe length”.

For example, numerical values such as sheet resistance = 0.1Ω / □, bottom capacitance per unit area = 0.01 fF / μm ² , and fringe capacitance per unit wiring fringe length of 0.005 fF / μm are given to the rule file. If the layout data based on the number of divisions given in the rule file gives a value of 10 μm for the wiring length between the nodes 10 and 20 and 1 μm for the wiring width, then R10 = 1Ω,
Cb = 0.1 fF, Cf1 = Cf2 = 0.05 fF, and a netlist as shown in FIG. 14 is extracted for the wiring structure shown in FIG. In this netlist, names starting with “R” and “C” indicate element names of resistance and capacitance (capacitor), respectively, and “10” and “2”.
“0” is a code indicating the node set on the Al wiring 100, and “0” is a ground point (hereinafter referred to as “ground node”).
Is a sign indicating The first row of the netlist indicates that the value of the wiring resistance R10 between the nodes 10 and 20 is 1Ω, and the second row indicates the bottom capacitance C between the nodes 20 and 0.
The third line indicates that the value of b = C20 is 0.1F.
The value of fringe capacitance Cf1 = C21 between 0 and 0 is 0.05F, and the fourth row shows that the fringe capacitance Cf between nodes 20 and 0 is
It shows that the value of f2 = C22 is 0.05F, respectively.

In the course of developing a semiconductor integrated circuit, it is possible to predict variations in circuit characteristics due to process variations,
In order to re-predict the circuit characteristics when the wiring or interlayer film formation process is changed, a netlist corresponding to the process variation and change is required. By the way, in the netlist extracted from the layout data according to the above-described prior art (the above-described prior art, Japanese Patent Application Laid-Open No. 5-149491, and Japanese Patent Application Laid-Open No. 5-216958), as shown in FIG. Is expressed as a “numerical value”. Therefore, in order to respond to process variations and changes, it is necessary not only to create a rule file reflecting new process data,
Even if there is no change in the layout pattern, the work of extracting the netlist from the layout data must be performed again, requiring much labor and time.

In order to solve such a problem, a function description netlist in which the function of the parasitic element value is described is extracted,
Layout verification that executes a function description netlist extraction method that does not require the function description netlist to be extracted again even if the parasitic element value is changed, and facilitates the calculation of parasitic elements for changes in integrated circuit processes and layouts. An apparatus is disclosed in JP-A-6-337904.

This layout verifying device is provided for each parasitic element extracted based on layout data of a semiconductor integrated circuit.
(Parasitic capacitance element and parasitic resistance element) Calculate parasitic element values such as capacitance value and resistance value that occur parasitically based on parasitic element parameters, and connect information file containing parasitic elements
A layout verification apparatus that performs layout verification based on a (function description netlist file), a parasitic element value function creation unit that creates a parasitic element value function that expresses a parasitic element value as a function of a parasitic element parameter, A parasitic element value calculation unit that calculates a parasitic element value by substituting element parameters into a parasitic element function, a corresponding net extraction unit that extracts a net to which a parasitic element extracted from a function description net list is added, layout data A layout data change point extraction unit that extracts a change point of the parameter, and a parasitic element value function change unit that changes the parasitic element value function by changing a coefficient of the parasitic element value function corresponding to the change point. The function to easily change the parasitic element value corresponding to the change and the parasitic element value function corresponding to the parasitic element It had the ability to display with.

[0014]

In recent years, as semiconductor integrated circuits have become finer and more highly integrated, worst-case analysis and statistical analysis (hereinafter referred to as "variation" Analysis) is becoming increasingly important. With the progress of miniaturization and high integration of integrated circuits, when so-called deep submicron designs are performed, it is considered that wiring delays are more dominant than gate delays. In this case, it is important to reflect variations in the capacitance value and resistance value of the wiring.

However, the conventional variation analysis using circuit simulation can only vary the model parameters describing the characteristics of the transistor. On the other hand, by using the function description netlist extraction method and the layout verification device disclosed in Japanese Patent Laid-Open No. 6-337904, the capacitance value and resistance value of the wiring can be obtained without repeatedly extracting the netlist from the layout data. It is possible to obtain a netlist in a case where an electrical characteristic value (a sheet resistance value or a capacitance value per unit area) as the corresponding process data changes. However, JP-A-6-3
Japanese Patent No. 37904 does not refer to such a circuit simulation using a netlist, and does not suggest a variation analysis using the above-described circuit simulation.

Therefore, in the present invention, even when circuit characteristics are predicted again by circuit simulation in response to process variations or changes, it is not necessary to perform a new netlist extraction operation, and the wiring capacity and wiring It is an object of the present invention to provide a circuit simulation method, a circuit simulation device, and the like that enable a variation analysis such as a worst case analysis or a statistical analysis that reflects a variation in an electrical characteristic value that is process data corresponding to a resistance.

[0017]

A first circuit simulation method according to the present invention for solving the above-mentioned problem is a circuit simulation method for simulating an operation of an integrated circuit whose circuit configuration is specified by a netlist. A function represented by a constant that is a parameter indicating a geometric shape of the layout pattern of the integrated circuit and a variable that is an electrical characteristic value determined by a process for manufacturing the integrated circuit, and Using a netlist describing the circuit configuration of the integrated circuit using a function indicating a parasitic element value including a value of a parasitic capacitance or a parasitic resistance, quantifying the parasitic element value described by the function in the netlist, Performing the simulation using the converted parasitic element values. .

A second circuit simulation method according to the present invention is the first circuit simulation method according to the first circuit simulation method, wherein a variation width is set for each of the variables.
A step of calculating each of the parasitic element values from the function using either the maximum value or the minimum value of the variable within the range of the variation as a representative value of the variable.
And a third step of performing the simulation using the parasitic element values calculated in the second step, and repeatedly executing the second and third steps for all combinations of the representative values for each of the variables Then, by obtaining a circuit characteristic value of the integrated circuit as a result of the simulation for each combination of the representative values, a variation width of the circuit characteristic value is obtained.

According to a third circuit simulation method of the present invention, in the first circuit simulation method, a first distribution is set for each of the variables.
A step of setting a representative value of the variable based on the distribution set for each variable; and a step of setting the parasitic element from the function based on the representative value of the variable set in the second step. A third step of calculating each of the values, and a fourth step of performing the simulation using the parasitic element values calculated in the third step, wherein a fourth step is performed for all combinations of the representative values for each of the variables. 2. A distribution of the circuit characteristic value is obtained by repeatedly executing a third step and a fourth step to obtain a circuit characteristic value of the integrated circuit as a result of the simulation for each combination of the representative values. And

A fourth circuit simulation method according to the present invention is the third circuit simulation method described above, wherein in the first step, a Gaussian distribution is set as the predetermined distribution.

A recording medium storing a first circuit simulation program according to the present invention is a recording medium storing a circuit simulation program for causing a computer to simulate an operation of an integrated circuit whose circuit configuration is specified by a netlist. A function represented by a constant that is a parameter indicating a geometric shape of the layout pattern of the integrated circuit and a variable that is an electrical characteristic value determined by a process for manufacturing the integrated circuit, and Using a netlist describing the circuit configuration of the integrated circuit while using a function indicating a parasitic element value including a value of a parasitic capacitance or a parasitic resistance, quantifying the parasitic element value described by the function in the netlist, Simulation using the optimized parasitic element values Performed, and characterized by recording a circuit simulation program for realizing that capability to the computer.

According to a second aspect of the present invention, there is provided a recording medium storing a second circuit simulation program, wherein the circuit simulation program has a variation width for each of the variables. A first step of setting;
A second step of calculating each of the parasitic element values from the function using either the maximum value or the minimum value of the variable within the range of the variation as a representative value of the variable;
And a third step of performing the simulation using the parasitic element values calculated in the second step, and repeatedly executing the second and third steps for all combinations of the representative values for each of the variables. The function of obtaining a circuit characteristic value of the integrated circuit as a result of the simulation for each combination of the representative values to obtain a variation width of the circuit characteristic value is realized by a computer.

According to a third aspect of the present invention, there is provided a recording medium storing a third circuit simulation program, wherein the circuit simulation program has a predetermined distribution for each of the variables. A first step of setting
A second step of setting a representative value of the variable based on the distribution set for each of the variables, each of the parasitic element values from the function based on the representative value of the variable set in the second step And a fourth step of performing the simulation using the parasitic element values calculated in the third step, wherein the second and third steps are performed for all combinations of the representative values for each of the variables. The third and fourth steps are repeatedly executed to obtain a circuit characteristic value of the integrated circuit as a result of the simulation for each combination of the representative values, thereby realizing a function of obtaining a distribution of the circuit characteristic value in the computer. It is characterized by having

In the recording medium storing the fourth circuit simulation program according to the present invention, in the recording medium storing the third circuit simulation program, a Gaussian distribution is set as the predetermined distribution in the first step. It is characterized by:

A first circuit simulation apparatus according to the present invention is a circuit simulation apparatus for simulating an operation of an integrated circuit whose circuit configuration is specified by a netlist, and shows a geometric shape of a layout pattern of the integrated circuit. A function represented by a constant that is a parameter and a variable that is an electrical characteristic value determined by a process for manufacturing an integrated circuit, and is a function indicating a parasitic element value including a parasitic capacitance or a parasitic resistance value of the layout pattern. Using a netlist describing the circuit configuration of the integrated circuit while using the numerical value of the parasitic element value described by the function in the netlist, the simulation is performed using the numerical value of the parasitic element value,
It is characterized by:

According to a second circuit simulation apparatus of the present invention, in the first circuit simulation apparatus, setting means for setting a variation width for each of the variables, and the variable within a range of the variation width. Element value calculation means for calculating each of the parasitic element values from the function using either the maximum value or the minimum value of the variables as a representative value of the variable, and using the parasitic element value calculated by the element value calculation means. Simulation execution means for performing the simulation, and for all combinations of the representative values for each of the variables, repeatedly performing the calculation of the parasitic element value by the element value calculation means and the simulation by the simulation execution means, As a result of the simulation for each combination of representative values, By obtaining road characteristic values, and an analyzing means for determining the variation range of the circuit characteristic value, characterized in that it comprises a.

A third circuit simulation apparatus according to the present invention is the first circuit simulation apparatus, wherein the first circuit sets a predetermined distribution for each of the variables.
Setting means, second setting means for setting a representative value of the variable based on the distribution set for each variable, and a function based on the representative value of the variable set by the second setting means. Calculating means for calculating each of the parasitic element values;
Simulation execution means for performing the simulation using the parasitic element value calculated by the calculation means; and setting and calculation of the representative value of the variable by the second setting means for all combinations of the representative value for each of the variables. Means for calculating each of said parasitic element values and means for repeatedly executing said simulation by means of simulation executing means to obtain circuit characteristic values of said integrated circuit as a result of said simulation for each combination of said representative values. Analysis means for obtaining a distribution of characteristic values.

According to a fourth circuit simulation device of the present invention, in the third circuit simulation device, the first setting means sets a Gaussian distribution as the predetermined distribution.

In a fifth circuit simulation method according to the present invention, a constant which is a parameter indicating a geometric shape of a layout pattern of the integrated circuit and an electric characteristic value which is determined by a process for manufacturing the integrated circuit. A first step of deriving a function that is a function expressed by a variable and that indicates a value of a parasitic capacitance or a parasitic resistance of the layout pattern, and corresponds to a process for manufacturing an integrated circuit to be simulated. A second step of obtaining the value of the variable, and a description of the value of the parasitic capacitance or the parasitic resistance based on the description of the function derived in the first step and the definition of the value of the variable obtained in the second step. A third step of generating a netlist as a first netlist, and a first netlist generated in the third step A fourth step of digitizing a parasitic capacitance value or a parasitic resistance value described by a function, and specifying the circuit configuration of the integrated circuit with the netlist generated in the third step, and digitizing the circuit configuration in the fourth step. And simulating the operation of the integrated circuit using the parasitic capacitance value or the parasitic resistance value.

In a sixth circuit simulation method according to the present invention, in the fifth circuit simulation method, in the first step, the capacitance value per unit area or unit length of the layout pattern is used as the variable as the variable. It is characterized in that a function indicating the value of the capacity is derived.

In a seventh circuit simulation method according to the present invention, in the fifth circuit simulation method, in the first step, a resistance value or a sheet resistance value per unit length of the layout pattern is set as the variable. It is characterized in that a function indicating the value of the parasitic resistance is derived.

According to an eighth circuit simulation method according to the present invention, in any one of the fifth to seventh circuit simulation methods, the resistance value per unit length, the sheet resistance value, and the unit area per unit length of the layout pattern are provided. A sixth step of designating an electric characteristic value to be used as the variable from among the electric characteristic values including a capacitance value per unit length and a capacitance value per unit length, wherein the first step includes: The function is derived only for the parasitic capacitance and the parasitic resistance calculated using the electric characteristic values specified in the step.

A ninth circuit simulation method according to the present invention is the circuit simulation method according to any of the fifth to eighth circuit simulation methods, wherein the circuit is described by the first netlist generated in the third step. A seventh step of generating a second netlist with a reduced number of elements by combining parasitic capacitances connected in parallel in the configuration; and in the fourth step, the first netlist generated in the third step is provided. 7th place instead of netlist
Digitizing the parasitic capacitance value or the parasitic resistance value described by the function in the second netlist generated in the step,
In the fifth step, the circuit configuration of the integrated circuit is specified by the second netlist generated in the seventh step instead of the first netlist generated in the third step, and the numerical value is determined in the fourth step. The operation of the integrated circuit is simulated using the converted parasitic capacitance value or parasitic resistance value.

A tenth circuit simulation method according to the present invention is the circuit simulation method according to any of the fifth to eighth circuit simulation methods, wherein the circuit is described by the first netlist generated in the third step. An eighth step of generating a third netlist with a reduced number of nodes by combining parasitic capacitance or parasitic resistance in the configuration is provided. In the fourth step, the first netlist generated in the third step is provided. In place of the netlist, a parasitic capacitance value or a parasitic resistance value described as a function in the third netlist generated in the eighth step is quantified, and in the fifth step, the parasitic capacitance value or the parasitic resistance value generated in the third step is generated. In addition to specifying the circuit configuration of the integrated circuit with the third netlist generated in the eighth step instead of the one netlist, Performing a simulation of operation of the integrated circuit by using the digitized parasitic capacitance or parasitic resistance in four steps, it is characterized in that.

According to an eleventh circuit simulation method according to the present invention, in any one of the fifth to eighth circuit simulation methods, the function derived in the first step is obtained in the second step. A ninth step of generating a fourth netlist in which the values of the parasitic capacitance or the parasitic resistance are quantified in the first to third netlists by substituting the values of the variables is provided. .

A recording medium storing a fifth circuit simulation program according to the present invention is a recording medium storing a circuit simulation program for causing a computer to execute an operation simulation of an integrated circuit whose circuit configuration is specified by a netlist. A function represented by a constant that is a parameter indicating a geometric shape of a layout pattern of the integrated circuit and a variable that is an electrical characteristic value determined by a process for manufacturing an integrated circuit, wherein the layout A first step of deriving a function indicating a value of a parasitic capacitance or a parasitic resistance of the pattern; a second step of obtaining a value of the variable corresponding to a process for manufacturing an integrated circuit to be simulated; Description of function derived in one step and second step A third step of generating, as a first netlist, the netlist representing the value of the parasitic capacitance or the parasitic resistance according to the acquired definition of the value of the variable; A fourth step of digitizing a parasitic capacitance value or a parasitic resistance value described by a function in the netlist, and specifying the circuit configuration of the integrated circuit by the netlist generated in the third step, and digitizing in the fourth step And a fifth step of simulating the operation of the integrated circuit using the parasitic capacitance value or the parasitic resistance value, and recording a circuit simulation program for causing a computer to execute the fifth step.

A fifth circuit simulation apparatus according to the present invention is a circuit simulation apparatus for simulating the operation of an integrated circuit whose circuit configuration is specified by a netlist, and shows a geometric shape of a layout pattern of the integrated circuit. A function represented by a constant that is a parameter and a variable that is an electrical characteristic value determined by a process for manufacturing an integrated circuit, and derives a function indicating a value of a parasitic capacitance or a parasitic resistance of the layout pattern. Function deriving means, value obtaining means for obtaining a value of the variable corresponding to a process for manufacturing the integrated circuit to be simulated, and description of the function derived by the function deriving means and obtained by the value obtaining means The value of the parasitic capacitance or parasitic resistance by the definition of the value of the variable List generating means for generating a netlist as a first netlist; digitizing means for numerically expressing a parasitic capacitance value or a parasitic resistance value described by a function in the first netlist; Simulation execution means for specifying the circuit configuration of the integrated circuit and performing the simulation using the parasitic capacitance value or the parasitic resistance value quantified by the quantification means.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Various embodiments of the present invention will be described below with reference to the drawings. <1. Configuration Common to Various Embodiments> First, a configuration common to various embodiments of the circuit simulation apparatus according to the present invention will be described. A circuit simulation apparatus as an embodiment of the present invention performs a circuit simulation using layout data indicating a design layout pattern of a semiconductor integrated circuit, and generates a netlist indicating a circuit configuration of the integrated circuit from the layout data A list extraction unit and a simulation unit that simulates the operation of an integrated circuit specified by the generated netlist (a circuit simulation device in a narrow sense)
It is composed of

FIG. 2 is a block diagram showing a hardware configuration of a circuit simulation apparatus as an embodiment of the present invention. The hardware of the circuit simulation apparatus is a computer such as an engineering workstation, and includes a main body 50 including a CPU 56 and a memory 58, a hard disk device 52, a keyboard 54, and a CRT 60. Then, based on a predetermined program stored in the memory 58, the CP
When U56 operates, a netlist is extracted from the layout data of the semiconductor integrated circuit, and a simulation of the operation of the integrated circuit specified by the netlist is performed. That is, a program (hereinafter, referred to as a “netlist extraction program”) for implementing a network extraction method described below is stored in the memory 58.
And a program for executing a circuit simulation method described below (hereinafter referred to as a “simulation program”). The computer operates as a netlist extraction device when the CPU 56 executes the netlist extraction program. Then, when the CPU 56 is executing the simulation program, it operates as a circuit simulation execution device (a circuit simulation device in a narrow sense) (realization of the simulation unit).

<1.2 Configuration of Net List Extraction Unit> Next, various configuration examples of the net list extraction unit in the circuit simulation apparatus according to the embodiment of the present invention will be described. <1.2.1 Structural Example 1> In this structural example, as in the description of the conventional example, the extraction of the netlist for the wiring structure shown in FIG. 3 will be described as an example. In this configuration example, a rule file describing an extraction rule for extracting a parasitic capacitance and a parasitic resistance from the layout data, and layout data indicating a layout pattern of the semiconductor integrated circuit are stored in the hard disk device 52 in advance. Here, based on the extraction rules described in the rule file, that is, based on the approximate model and the number of divisions of the wiring structure specified in the rule file, the nodes 10 and 20 are set on the Al wiring 100 as in the conventional example. The Al wiring 100 is divided at these nodes, and the nodes 10 and 20 are divided.
By adding a resistor R10 between the node 20 and a capacitor Cb + Cf1 + Cf2 between the node 20 and the Si substrate 103, the wiring structure shown in FIG. 3 is approximated by an L-shape (see FIG. 4). Further, in this configuration example, in the rule file, electrical characteristic values such as a sheet resistance value of the Al wiring 100, a bottom capacitance value per unit wiring area, and a fringe capacitance value per unit wiring fringe length are given as process data. In addition, parameter names "RAL", "CBAL", and "CFAL" are given to these electrical characteristic values, respectively, which is different from the conventional example in this point.

FIG. 1A is a flowchart showing a procedure for extracting a netlist in this configuration example. In the netlist extraction unit of this configuration example, first, in step S10, the above-described rule file is
Read from 2. Subsequently, in step S12, the layout data is read from the hard disk device 52.
Thereafter, in step S14, based on the rule file read in step S10, a netlist is generated from the layout data read in step S12 as follows, and the generated netlist is stored in the hard disk device 52. (Netlist extraction).

FIG. 1B is a flowchart showing the detailed procedure of extracting the net list in step S14. As shown in this flowchart, when extracting a netlist, first, a node is set on a pattern of wiring or the like represented by layout data based on the number of divisions specified by a rule file (step S).
20). Next, the transistor is recognized from the layout data and information about the transistor is extracted (step S22). Then, based on the approximation model specified in the node setting and the rule file, a distributed constant circuit corresponding to the layout pattern is approximated by a lumped constant circuit,
A function indicating the values of the parasitic capacitance and the parasitic resistance constituting the lumped constant circuit, the variable being a sheet resistance value RAL, a bottom capacitance value CBAL per unit wiring area, and a fringe capacitance value CFAL per unit wiring fringe length. Is derived (step S24). Derivation of this function requires numerical values indicating the geometric shape of the layout pattern, such as the wiring length, wiring width, and wiring area. These numerical values are obtained from the layout data. After deriving the functions indicating the values of the parasitic capacitance and the parasitic resistance, connection information indicating the addition of the parasitic capacitance and the parasitic resistance to the node is generated (step S26). Using the functions and connection information obtained in this way and the electrical characteristic values as process data read from the rule file, a description of a function indicating the value of the parasitic capacitance or Parameters RAL and C indicating electrical characteristic values as data
A netlist including definitions of BAL and CFAL values (definition of values of variables of the above function) is generated (step S2).
8).

In general, the wiring resistance R10 is calculated by "RAL x wiring length / wiring width", the bottom capacitance Cb is calculated by "CBAL x wiring area", and the fringe capacitances Cf1 and Cf2 are calculated by "CFAL x wiring fringe length". Therefore, for example, if the numerical value of the wiring length between the nodes 10 and 20 = 10 μm and the wiring width = 1 μm is obtained from the number of divisions and the layout data specified in the rule file, R10 = 10 ·
RAL [Ω], Cb = 10 · CBAL [fF], Cf1 = C
f2 = 10 · CFAL [fF] In this case, the netlist L shown in FIG.
st_nt is generated. The netlist Lst_nt is different from the conventional example shown in FIG. 14 in that the parasitic capacitance value and the parasitic resistance value are described by a function having parameters RAL, CBAL, and CFAL as variables (hereinafter, a parasitic function by such a function). "Function description" for description of capacitance value and parasitic resistance value
).

In this configuration example, the values of the parameters RAL, CBAL, and CFAL indicating the electrical characteristic values corresponding to the process for manufacturing the target integrated circuit are given to the rule file. RA in the first three lines (lines starting with “.PARAM”)
L, CBAL, and CFAL values are defined (hereinafter, such a command for defining parameter values is referred to as “PARA”).
M command ”). The fourth to seventh lines of this netlist correspond to the first to fourth lines of the conventional netlist shown in FIG. 14, and the fourth line of this netlist is a wiring between nodes 10 and 20. The value of the resistor R10 is 10 · RAL
The fifth line indicates that the value of the bottom capacitance Cb = C20 between the nodes 20 and 0 is 10 · CBAL [F], and the sixth line indicates the fringe between the nodes 20 and 0. Capacity Cf1
= C21 is 10 · CFAL [F], and the seventh line indicates that the value of the fringe capacitance Cf2 between the nodes 20 and 0 is 10 · CFAL [F]. . Node 0 is a ground node indicating a ground point.

The netlist Ls of this configuration example shown in FIG.
At t_nt, the values of RAL, CBAL and CFAL are PA
Although the format is defined by the RAM command, it may be defined in another format. If the layout design has been completed but the process to be used for manufacturing has not been determined, appropriate temporary values for the parameters RAL, CBAL, and CFAL are defined in the netlist, and then the process is determined. At this point, the line of the PARAM command in the netlist may be modified to define the correct values for those parameters. When a large-scale integrated circuit is targeted, the size of the netlist becomes enormous, but the number of lines defining the parameters is very small, and a line such as a PARAM command is searched using a normal text editor or the like. And can be easily modified.

In this configuration example, the wiring structure (FIG. 3) operating as an RC distributed constant circuit is approximated (L-type approximation) by a lumped constant circuit which is an L-type network (see FIG. 4). As an approximate model using a lumped circuit with a structure, π
Other approximation models such as approximation by a type network (π type approximation) and approximation by a T type network (T type approximation) may be used. In this configuration example, the number of division stages is specified when the distributed constant circuit is approximated by the lumped constant circuit. However, as a specific specification method, from a hole for connecting to a wiring of another layer to a hole is specified. It is possible to use a method in which one wiring is regarded as one and the number of divisions therebetween is designated. Alternatively, instead of specifying the number of division steps, a method of designating the number of sheets and dividing by the number of sheets may be used, or a resistance value or a wiring length may be designated to specify the resistance value or the wiring length. May be divided. When a wiring structure is approximated by a lumped constant circuit, the approximation accuracy is improved as the number of division stages increases, regardless of which approximation model is used. However, as the number of division stages increases, the size of the extracted netlist also increases.

As described above, according to the present configuration example, parameter names are given to the sheet resistance of the wiring, the bottom capacitance per unit wiring area, and the like, and a function using these parameters as variables in the extracted netlist is given. Is described as a parasitic resistance value or a parasitic capacitance value (see FIG. 5). For this reason, when the process fluctuates due to the process variation, the above-described parameter is simply redefined to the corresponding value after the fluctuation, that is, the PARAM command in the netlist is corrected without extracting the netlist again. can do. Then, by performing a circuit simulation or the like using the netlist after the parameter redefinition, it is possible to predict a change in circuit characteristics due to a process change. Also, when the process is changed while the layout pattern remains the same, it can be dealt with by simply redefining the parameter to a value corresponding to the process after the change (only by modifying the PARAM command). There is no need to extract the list again.

<1.2.2 Configuration Example 2> A second configuration example (hereinafter, referred to as “configuration example 2”) of a netlist extraction unit in a circuit simulation apparatus as an embodiment of the present invention will be described. The hardware configuration of the netlist extraction unit of this configuration example is the same as that of Configuration Example 1 described above.

The procedure for extracting a net list in this configuration example is basically the same as that in the above configuration example 1 and is as shown in FIG. 1, but the details of the procedure are slightly different. Less than,
This will be described with reference to the flowchart of FIG.

First, in step S10, a rule file is read from the hard disk device 52. In this rule file, in addition to the same information as in the above configuration example 1, it depends on processes such as a sheet resistance value RAL, a bottom capacitance value CBAL per unit wiring area, and a fringe capacitance value CFAL per unit wiring fringe length. Among the parameters that indicate the electrical characteristics to be used, information for specifying parameters used as variables when describing the parasitic capacitance value and the parasitic resistance value in the netlist as a function is included (hereinafter, this specification is referred to as “ Variable specification).

In the following step S12, the layout data is read from the hard disk device 52, as in the first configuration example.

Then, in step S14, based on the rule file read in step S10, a net list is generated from the layout data read in step S12 as follows (net list extraction).

In the netlist, a line (parameter definition line) defining the values of the above parameters RAL, CBAL and CFAL by a PARAM command, and a parasitic capacitance or a parasitic expressed by using a parameter specified in a rule file. The part of the line describing the resistance (the line of the function description) is generated in the same manner as in the first configuration example. On the other hand, as for the parasitic capacitance or the parasitic resistance expressed by using the parameter not specified in the rule file, the parasitic capacitance value or the parasitic resistance value is calculated in the same manner as in the conventional example, and the calculated value is netted. Write in the list. That is, for these parasitic capacitance values or parasitic resistance values,
As before, describe with numerical values.

For example, if the formation process of the interlayer film is scheduled to be changed after the extraction of the netlist (the wiring process is not changed), the bottom capacitance Cb and the fringe capacitances Cf1 and Cf2 may change in the future. However, the wiring resistance R10 does not change. In this case, in this configuration example, the sheet resistance value RA of the wiring is stored in the rule file.
No variable is specified for L. Thus, the value of the wiring resistance R10 is described as a numerical value in the netlist, and a netlist Lst_nt as shown in FIG. 6 is generated for the wiring structure shown in FIG.

According to this configuration example, the above parameters RAL and CB indicating the electrical characteristics depending on the process.
Of the AL, CFAL, etc., only the parasitic capacitance value or the parasitic resistance value expressed using the parameter specified by the variable in the rule file is described by a function, and the other parasitic capacitance value or the parasitic resistance value is described by a numerical value. . Therefore, for example, if only the interlayer film forming process is likely to be changed, the parasitic resistance value (wiring resistance value) is considered not to change. Thus, the description format of the parasitic resistance value and the parasitic capacitance value can be selected according to the purpose, such that the parasitic resistance value is described by a numerical value and the parasitic capacitance value is described by a function in the netlist. Thus, efficient netlist extraction suitable for the purpose can be performed.

<1.2.3 Configuration Example 3> A third configuration example (hereinafter, referred to as “configuration example 3”) of a netlist extraction unit in a circuit simulation apparatus as an embodiment of the present invention will be described. The hardware configuration of the netlist extraction unit of this configuration example is also the same as that of the first configuration example.

The procedure for extracting the netlist in this configuration example is as shown in FIG. In this configuration example, as in the configuration example 1, the rule file is read (step S1).
0), reading of layout data (step S1)
2), extraction of netlist by function description (step S
Perform 14). However, a predetermined parasitic element synthesis condition is described in the rule file. In this configuration example, in step S16, based on the parasitic element synthesis condition,
A parasitic element such as a parasitic capacitance or a parasitic resistance described by the extracted netlist is synthesized, and step S12 is performed.
Is converted into a netlist obtained by combining parasitic elements.

In the synthesis of the parasitic elements in step S16, when the rule file specifies that a plurality of parasitic elements existing between the same nodes are combined into one as the above-mentioned parasitic element synthesis condition, the following is performed. Processing is performed. For example, node 2 in the equivalent circuit shown in FIG.
A capacitor which is a plurality of parasitic elements between 0 and node 0 (ground node), that is, a capacitor representing the bottom capacitance Cb and two capacitors representing the fringe capacitances Cf1 and Cf2 are connected to one of the capacitance values (Cb + Cf1 + Cf2). Replace with one capacitor. Then, the netlist extracted in step S14 is converted into an equivalent circuit in which three capacitors are replaced by one capacitor, that is, a netlist describing the equivalent circuit shown in FIG. The netlist after this conversion is as shown in FIG. 9. In the fifth row of this netlist, the capacitance value of the capacitor C20 connected between the nodes 20 and 0 is 10 · C
BAL + 10.CFAL + 10.CFAL is shown.

As described above, by combining the parasitic elements in step S16, the number of parasitic elements can be reduced, or the number of nodes can be reduced together with the parasitic elements as described later, so that the scale of the netlist is reduced. . In the synthesis of the parasitic elements shown in FIG. 8, all the parasitic elements before the synthesis are function descriptions, but the same synthesis can be performed even when the parasitic elements described numerically are mixed. Obviously,

FIG. 10 shows another example of synthesis performed in step S16. This is because, as the parasitic element synthesizing condition, a parasitic element in a lumped constant circuit obtained by dividing a wiring structure and approximating it with a π-type network (hereinafter, such approximation is referred to as “π-type division approximation”). This indicates a case where is specified in the rule file. In this case, the π-type network shown in FIG.
Is converted to the π-type network shown in FIG. The synthesizing method itself by this conversion is publicly known, whereby the resistance value R1,
The two resistors of R2 are replaced by one resistor of resistance value R1 + R2, and the three capacitors of capacitance values C0, C1, C2 are replaced by capacitance values C0 + {R2 / (R1 + R2)} C1, C2 + @ R1 /.
(R1 + R2)｝ C1 is replaced with two capacitors, and the number of nodes is reduced by one. In this way, the netlist can be compressed by combining the parasitic elements. Then, the same synthesis can be further performed on the circuit after the synthesis, and such synthesis for netlist compression can be repeated in the π-type division approximation of the wiring structure. At this time, as described above, it is possible to combine the parasitic resistance value and the parasitic capacitance value while keeping the function description. However, when the circuit simulation is performed using the compressed netlist, the simulation accuracy is reduced as compared with the case where the uncompressed netlist is used. That is, there is a trade-off between the compression of the netlist by the combining method shown in FIG. 10 and the simulation accuracy. Therefore, in this configuration example, a threshold is set in advance for the resistance between the nodes, and the combination is repeated while the resistance between the nodes in the combined circuit is equal to or less than the threshold, and the resistance between the nodes is set to the threshold. When it exceeds, the synthesis is stopped. This makes it possible to balance the compression of the netlist with the simulation accuracy.

In the above description, the netlist is compressed by combining with the RC network obtained by the π-type division approximation, but other combining methods can be applied. Further, even when the function description and the numerical description are mixed as in the configuration example 2, the netlist can be compressed by synthesizing the parasitic elements.

<1.2.4 Configuration Example 4> A fourth configuration example (hereinafter, referred to as “configuration example 4”) of a netlist extraction unit in a circuit simulation apparatus as an embodiment of the present invention will be described. The hardware configuration of the netlist extraction unit of this configuration example is also the same as that of the first configuration example (see FIG. 2), and the operation of the CPU 56 based on the netlist extraction program stored in the memory 58 allows the semiconductor integrated circuit to operate. A net list is extracted from the layout data. In the present configuration example, the netlist extracting means is realized based on the netlist extracting program as described above, and means for converting a function description of a parasitic element in the netlist into a numerical description (hereinafter, referred to as “numerizing means”). Is realized.

FIG. 11 is a flowchart showing the operation of the digitizing means in this configuration example. In the present configuration example, a netlist is extracted in the same manner as in the configuration example 1 (see FIG. 1), and then the function description for the parasitic element in the netlist is converted into a numerical description by the procedure shown in the flowchart of FIG. You.

First, in step S 50, the netlist extracted according to the procedure shown in FIG. 1, that is, the netlist in which the function description is given to the parasitic element (hereinafter referred to as “function description netlist”)
Read from 2. Next, in step S52, the function description in this netlist is rewritten into a numerical description, thereby converting it into a netlist in which the parasitic elements are numerically described, that is, a conventional netlist (see FIG. 14). Specifically, the parameters RAL, CBAL, and CFAL, which are variables in the function indicating the parasitic capacitance value and the parasitic resistance value described in the netlist read in step S50, are defined by the PARAM command in the netlist. The function values are calculated by substituting the values of the parameters. Then, the function indicating the parasitic capacitance value and the parasitic resistance value in the netlist is replaced with the calculated function value (numerical value). However, if necessary, the function description netlist may be stored.

For example, when a net list is printed out or a circuit simulation is performed based on the net list, the parasitic capacitance and the parasitic resistance are numerically described without using a function description because of a small data amount. A conventional netlist (hereinafter referred to as "function-free netlist") may be more desirable. In some cases, it is desired to check the values of the parasitic capacitance and the parasitic resistance. In such a case, it is possible to obtain the function-free netlist by the above-described digitizing means without extracting the netlist again. Therefore, according to the present configuration example, both the function description netlist and the function non-use netlist can be obtained according to the purpose only by performing the netlist extraction once.

It is not necessary for the numerical value converting means to numerically convert all parameters which are variables of a function indicating a parasitic capacitance value or a parasitic resistance value in the function description netlist.
Of these parameters, only the parameters specified in advance may be replaced with numerical values.

<1.2.5 Other Configuration Examples> In the above, each configuration example of the netlist extraction unit has been described by taking the parasitic element in the wiring structure as an example. However, the present invention is limited to the wiring structure. Instead, it can be applied to any structure and can be applied to any process. For example, the parasitic capacitance value and the parasitic resistance value of the diffusion layer in the MOS transistor structure are also calculated from the capacitance value per unit area or unit length, the sheet resistance value, and the layout data. Similarly, a function description netlist can be generated. The contact resistance and through-hole resistance are also calculated from the resistance value per hole and the number of holes.
Alternatively, the resistance value can be calculated from the resistance value per unit hole area and the hole area, and a netlist having a function description can be generated for them as in the above-described configuration examples. Further, when describing other parasitic elements such as parasitic inductors in a netlist extracted from layout data, the function description can be applied to the parasitic elements in the same manner as described above, and the same effect as described above can be obtained. Can be obtained.

<1.3 Configuration of Simulation Unit> Next, the configuration of the simulation unit (configuration common to various embodiments) in the circuit simulation apparatus as an embodiment of the present invention will be described. Although the hardware configuration of the simulation unit is the same as that of the netlist extraction unit of the above configuration example 1 as described above (see FIG. 2),
The program stored in the memory 58 and executed by the CPU 56 is different. That is, in the computer having the hardware configuration shown in FIG. 2, when the CPU 56 operates based on the simulation program stored in the memory 58, the function description netlist extracted in the above configuration example 1 and the like is read and the semiconductor integrated circuit is read. A simulation unit (a circuit simulation device in a narrow sense) that simulates the operation described above is realized. In the simulation unit, circuit simulation control information, a function description netlist extracted from layout data of a target semiconductor integrated circuit (hereinafter, referred to as a “target circuit”), and information indicating characteristics of various circuit elements ( Hereinafter, “element characteristic information”) is stored in the hard disk device 52.

FIG. 12 is a functional block diagram conceptually showing the configuration of the present simulation unit realized in this way. As shown in this figure, this simulation unit conceptually includes an input unit 30, an analysis unit 35, and an output unit 40, similarly to a conventional circuit simulation apparatus. Here, the input unit 30 has a function description netlist reading means 32 and a numerical value means 34, which is different from the conventional one. The simulation unit includes a circuit simulation control information holding unit 42 and a function description netlist holding unit 4 realized by the hard disk device 52.
4 and an element characteristic information holding unit 46. The function description netlist reading means 32 reads the netlist from the function description netlist holding unit 44, recognizes a PARAM command from the netlist, obtains a parameter value, and describes a value of a circuit element. "
A function indicating the parasitic capacitance value and the parasitic resistance value is obtained by recognizing the portion surrounded by. The aforementioned digitizing means 34 digitizes the parasitic element value described by the function in the function description netlist for specifying the configuration of the integrated circuit to be simulated, and is obtained by the function description netlist reading means 32. By calculating the values of these functions using the values of the functions and parameters, the parasitic capacitance value and the parasitic resistance value can be quantified and a function-free netlist can be obtained. In the variation analysis (worst case analysis or Monte Carlo analysis) described later, the numerical value means 34 sets the maximum value or the minimum value of the variable of the function under a predetermined variation width as a representative value (see FIG. 15),
Alternatively, a value of a variable of the function obtained by sampling under a predetermined distribution characteristic is set as a representative value (in the case of FIG. 17 described later), and a parasitic element value is calculated by the function using the representative value. (Parasitic capacitance value and parasitic resistance value are quantified).

FIG. 13 is a flowchart showing the operation of the simulation section. In the simulation unit, first, in step S100, the input unit 30
The circuit simulation control information, the function description net list of the target circuit, and the element characteristic information are read from the circuit simulation control information holding unit 42, the function description net list holding unit 44, and the element characteristic information holding unit 46, respectively. At this time, the function-unused netlist is obtained by the function description netlist reading means 32 and the digitizing means 34 in the input unit 30 as described above.

In the next step S110, the analysis unit 35
Simulates the operation of the target circuit based on the data read in step S100 (execution of circuit simulation). At this time, the configuration of the target circuit is specified by a function-free netlist. As a means for executing a circuit simulation, SPICE (Simulation Progr.
An existing circuit simulation program such as am with Integrated Circuit Emphasis) can be used.

Thereafter, in step S120, the voltage (change) at a predetermined node of the target circuit obtained by the circuit simulation is output to the hard disk device 52 or the CRT 60 as a simulation result.

According to the simulation section as described above, the function description netlist can be read as data indicating the configuration of the circuit to be simulated. Therefore, when the layout data is the same and the process is changed, or when the process is changed. If there is a variation, the circuit simulation is performed by correcting the PARAM command line in the function description netlist without extracting the netlist from the layout data again, so that changes in circuit characteristics due to process changes and variations can be easily performed. Can be predicted. Further, when layout data is obtained but the process is not determined, a process having a desired circuit characteristic is determined and the process is optimized by repeating a circuit simulation while variously changing parameters with a PARAM command. be able to.

The above description of the operation of the present simulation section is for a basic operation common to various embodiments of the present invention, and the present simulation section performs a variation analysis such as a worst case analysis or a statistical analysis. In this case, as will be described later, the circuit simulation (circuit characteristic analysis) is repeated a predetermined number of times by changing the value of a variable (electrical characteristic value) in a function expressing a parasitic element value such as a parasitic capacitance or a parasitic resistance ( 15 and 17),
As a result, circuit characteristic values (signal delay time, power consumption, etc.) for various values of the variables are obtained.

<2. Description of Various Embodiments> Next, various embodiments of the circuit simulation apparatus according to the present invention will be described.
The description will focus on features unique to the embodiment. <2.1
First Embodiment> A circuit simulation apparatus according to a first embodiment of the present invention will be described. As can be seen from the above description of the simulation unit, the circuit simulation apparatus has a geometric shape constant Cns which is a parameter indicating a geometric shape of a layout pattern in an integrated circuit.
t_arg and an electric characteristic variable Var_elc which is an electric characteristic value determined depending on a process for manufacturing an integrated circuit.
It has the function of simulating the operation of an integrated circuit using a function description netlist that describes the electrical characteristic values (parasitic capacitance value, parasitic resistance value, etc.) of the parasitic element according to a function expressed by using There is.

By providing such a function, it is considered that the influence of the wiring delay becomes dominant as compared with the influence of the gate delay. In such a circuit simulation, it is easy to accurately consider variations in the capacitance value and resistance value of the wiring of the integrated circuit. As a result, there is an effect that a circuit simulation for analyzing a variation width of a circuit characteristic (specifically, a delay time of a signal, power consumption of an integrated circuit, or the like) can be accurately executed.

As described above, the circuit simulation apparatus according to the present embodiment includes a netlist extraction unit and a simulator unit. Then, by the netlist extraction unit,
A function description netlist describing the configuration of the integrated circuit (target circuit) to be simulated is generated, and the simulator simulates the operation of the target circuit using the function description netlist. The details of the netlist extraction unit in the present embodiment are as described above (see <1.2 Configuration of Netlist Extraction Unit> and FIG. 1). On the other hand, in the simulation section of the present embodiment, a worst case analysis is performed by a predetermined circuit simulation method, which is a feature unique to the present embodiment. Therefore, a circuit simulation method for performing a worst case analysis in the simulation unit of the present embodiment will be described below.

<2.1.1 Circuit Simulation Method of First Embodiment> In the circuit simulation method, the function description netlist Lst_nt is an electrical characteristic value determined depending on a process for manufacturing an integrated circuit. The predetermined process data Dt_pr is handled as a variable (electric characteristic variable Var_elc), and the electric characteristic variable Va
Variations in circuit characteristics can be easily analyzed by providing variations in r_elc.

More specifically, the specified electrical characteristic variable Va
If a variation width ΔVar is given to r_elc and a simulation is performed using the maximum value or the minimum value, variation also occurs in circuit characteristics. Maximum value Var_m of the obtained circuit characteristics
Analyze the dispersion of circuit characteristics using ax and the minimum value Var_min, or the best value and the worst value (specifically, the maximum value and the minimum value or the best value and the worst value such as the signal delay time and the power consumption of the integrated circuit). I have. Such an analysis is called a worst case analysis or a worst corner analysis. The circuit simulation method is a method for performing the worst case analysis (worst corner analysis).

The function description type netlist Ls shown in FIG.
T_nt will be described as a specific example. The sheet resistance value RAL of the Al wiring and the bottom capacitance value CBAL per unit wiring area are selected as the electrical characteristic variable Var_elc,
The variation width ΔVar of RAL is set to 0.05 to 0.2, and the variation width ΔVar of CBAL is set to 0.005 to 0.
Set to 02. Under this condition, the representative value Var_rp of the variable
(RAL, CBAL) = (0.05,0.005),
(0.05, 0.02), (0.2, 0.005),
(0.2, 0.02) (that is, the number of combinations N
By executing the circuit characteristic analysis for each of the corner conditions of _cmb), four types of circuit characteristics can be obtained. That is, by executing a circuit simulation for each of the four corner conditions, four values can be obtained for the delay time of the predetermined signal, the power consumption of the integrated circuit, and the like. By analyzing this result, it is possible to obtain the strength of correlation between each electrical characteristic variable Var_elc and the circuit characteristics, and the best and worst values of the circuit characteristics.

FIG. 15 is a flowchart for explaining the worst case analysis executed by the circuit simulation method of the present embodiment.

The worst case analysis has first to third steps. When the worst case analysis is started (step P1), first, a first step is executed. Here, the first step is to determine the electric characteristic variable V
This is a step of setting a variation width ΔVar for each of ar_elc. Such a first step is, as shown in step P2 of FIG. 15, an electric characteristic variable Var_elc.
Inputting the variation width ΔVar for each of
Integrated circuit subject to worst-case analysis (target circuit)
Description netlist Ls for specifying the circuit configuration of
It is configured to include a step of inputting t_nt and a step of inputting electrical characteristics (element characteristic information) concerning elements constituting the target circuit.

The second step executed after the first step is, as shown in step P3 of FIG. 15, a variable (specifically, RAL or CBAL) in each parasitic element D_stry.
Or the like, using either the maximum value Var_max or the minimum value Var_min as the representative value Var_rp of the variable.
This is a step of obtaining a parasitic element value V_stry (specifically, a parasitic capacitance value, a parasitic resistance value, etc.) for each stry.

The third step (step P4) executed after the second step is a step of executing a circuit characteristic analysis of the target circuit using the parasitic element value V_stry for each parasitic element D_stry obtained in the second step. is there.

In the worst case analysis, the first step (step P2) to the third step (step P2)
By repeating the second step (step P3) and the third step (step P4) a predetermined number of times according to the number N_cmb of all combinations of the representative values using step 4) (step P3 → step P4 → step P5 Yes
→ Step P6 → Step P3...), And the variation width of the circuit characteristics is obtained.

Finally, the obtained variation width of the circuit characteristics is output in step P7, and the worst-case analysis ends (step P8).

By using the first to third steps as described above and using the predetermined process data Dt_pr as a variable in the function description netlist Lst_nt to give a variation to the process data Dt_pr, the maximum variation in the circuit characteristics is obtained. There is an effect that the value and the minimum value (or the best value and the worst value) can be obtained. In addition, by using such variations in circuit characteristics, it is possible to accurately perform worst case analysis (particularly, worst-case corner analysis) that can analyze variations in circuit characteristics due to variations in wiring processes and the like, which has been difficult in the past. It has the effect of becoming Further, by analyzing the result of such worst-case analysis, it is possible to accurately obtain the correlation strength between the parasitic element value V_stry of each parasitic element D_stry and the circuit characteristic, and the best value and the worst value. This has the effect.

<2.1.2 Circuit Simulation Program of First Embodiment> The worst-case analysis by the above-described circuit simulation method is performed by the CPU 56 executing a circuit simulation program described below.

The circuit simulation program is a storage medium (specifically, a magnetic storage medium such as a floppy disk or a magnetic tape) which can be read using a computer which is hardware for realizing the circuit simulation apparatus of the present embodiment. Means or CD-ROM (C
ompact Disk-ROM) or the like.

The circuit simulation program read from the storage medium is stored in an internal storage means (specifically, a semiconductor storage device such as an EEPROM or a RAM, a magnetic disk) provided in a circuit simulation apparatus (computer). , Etc.)
It is read out as appropriate according to the execution of the circuit simulation method.

The circuit simulation program includes a geometric shape constant Cnst_arg and an electrical characteristic variable Va.
Parasitic element D_str according to a function expressed using r_elc
It has a circuit characteristic variation analysis routine program that analyzes circuit characteristic variations by simulating the operation of the target circuit using a function description type netlist describing the electrical characteristic values of y.

Such a circuit characteristic variation analysis routine program includes a first program step, a second program step, and a third program step. Here, the first program step is a program step for setting the variation width ΔVar for each of the electrical characteristic variables Var_elc. In particular, the first program step when executing the worst-case analysis routine program includes a program step of inputting a variation width ΔVar for each of the electric characteristic variables Var_elc, a program step of inputting a function description netlist Lst_nt, And a program step of inputting electrical characteristics (element characteristic information) of elements constituting a target circuit which is an integrated circuit.

The second program step is a program step of obtaining a parasitic element value V_stry for each parasitic element D_stry by using either the maximum value Var_max or the minimum value Var_min of the variable in each parasitic element D_stry as a representative value Var_rp of the variable. It is.

Further, the third program step is a program step for executing a circuit characteristic analysis using the parasitic element value V_stry for each parasitic element D_stry obtained in the second program step.

Such a circuit characteristic variation analysis routine program uses the first to third program steps to calculate the number N of all combinations of representative values.
By repeating the circuit characteristic analysis using the second program step and the third program step a predetermined number of times according to _cmb, it is possible to execute a worst case analysis for obtaining a variation width of the circuit characteristic.

<2.1.3 Hardware Configuration of First Embodiment> The circuit simulation apparatus of the present embodiment performs a worst-case analysis by using a function description netlist Lst_nt for specifying a circuit configuration of an integrated circuit. And a means for executing a circuit simulation using the quantified parasitic element value V_stry (corresponding to step P5). ), Etc., which are realized by a computer program. Therefore, as shown in FIG. 2, the circuit simulation apparatus according to the present embodiment includes a CPU 56 that performs various arithmetic processing and the like by executing a predetermined program as shown in FIG. A storage medium (hard disk device 52 in the figure) holding various programs such as programs,
A storage means (memory 58 in the figure), a keyboard 54 for inputting various operation commands and parameters, a CRT 60 for displaying a circuit simulation process and results, a peripheral device for reading the above-mentioned storage medium (not shown), etc. It is configured at the center.

As described above, the basic configuration of the required circuit simulation apparatus is the same as the basic configuration of the conventional circuit simulation apparatus, and therefore the hardware resources (that is, the circuit simulation environment) of the conventional circuit simulation apparatus are used. ) Is effectively used to realize a circuit simulation environment easily and at low cost.

<2.2 Second Embodiment> Next, a circuit simulation apparatus according to a second embodiment of the present invention will be described. Note that the same parts as those already described in the first embodiment are denoted by the same reference numerals, and redundant description will be omitted.

The circuit simulation apparatus of this embodiment is conceptually composed of a netlist extraction unit and a simulator unit. The configuration and operation of the netlist extraction unit are the same as those of the first embodiment. However, the simulation unit of this embodiment performs Monte Carlo analysis by a predetermined circuit simulation method, which is a feature unique to this embodiment. It has become. Therefore, a circuit simulation method for performing the Monte Carlo analysis in the simulation unit of the present embodiment will be described below.

<2.2.1 Circuit Simulation Method of Second Embodiment> The Monte Carlo analysis performed by the present circuit simulation method is a statistical analysis method generally used in variation analysis, and the function description netlist L
In st_nt, predetermined process data Dt_pr, which is an electrical characteristic value determined depending on a process for manufacturing an integrated circuit, is treated as a variable (electrical characteristic variable Var_elc), and a predetermined distribution characteristic (Var_elc) is assigned to the electrical characteristic variable Var_elc. It is characterized in that statistical variation analysis of circuit characteristics is easily performed by giving a Gaussian distribution characteristic (Chr_dst) described later.

Specifically, in the Monte Carlo analysis method, the specified electrical characteristic variable Var_elc is sampled along a Gaussian distribution or a constant distribution by the number of samplings N_smpl (several tens to several hundreds), and each of them is executed. The circuit simulation method of the present embodiment is executed using the sampling values of (1) and (2), and a statistical analysis is performed on the calculated result (which also shows the distribution).

Next, a Monte Carlo analysis method for the characteristic variation of the circuit having the wiring 100 having the structure shown in FIG. 3B will be described. The bottom capacitance C shown in FIG.
Consider a case where b fluctuates due to variations in interlayer film thickness (however, for simplicity, fringe capacitances Cfl and Cf2 are ignored).

In the Monte Carlo analysis, the function description netlist Lst_nt is extracted using the layout data Dt_lyt of the integrated circuit having the load of the wiring 100. In the function description netlist Lst_nt, FIG.
, The bottom capacitance per unit area (Cb)
Is given an electrical characteristic variable Var_elc called CBAL, and a Gaussian distribution characteristic Chr_dst is set for CBAL. However, the function description netlist L of FIG.
In st_nt, the value of CBAL is specified (CBA
L = 0.01F), where the type of distribution, center value, standard deviation σ, etc. are specified based on the Gaussian distribution characteristic Chr_dst instead of this specified value. In setting the analysis conditions in the Monte Carlo analysis, the number of samplings N_smpl and the like are set.

When a circuit simulation is performed under such conditions, the bottom capacitance CBAL per unit area is sampled at a frequency as shown in FIG.
The variation in circuit characteristics reflecting the variation in L is shown in FIG.
It is calculated as shown in FIG. Here, FIG.
FIG. 16B is a histogram showing an example of the variation of the bottom capacitance CBAL per unit wiring area, and FIG. 16B is a histogram showing the variation of the circuit characteristic value.

The center value and the σ value (dispersion value) of the circuit characteristic are obtained based on the histogram of FIG. And statistical analysis such as investigating.

FIG. 17 is a flowchart for explaining the Monte Carlo analysis executed by the circuit simulation method of the present embodiment.

The Monte Carlo analysis according to the circuit simulation method of the present embodiment has a first step, a second step, and a third step. When the Monte Carlo analysis is started (Step Q1), first, a first step is executed (Step Q2). Here, the first step is a step of setting a predetermined distribution characteristic Chr_dst concerning the electric characteristic for each of the electric characteristic variables Var_elc. The first step (step Q2) is, as shown in FIG. 17, a step of inputting the distribution characteristic Chr_dst for each of the electric characteristic variables Var_elc, and a step of inputting the number of samplings N_smpl for the number of repetitions of the statistical analysis. Inputting a function description netlist Lst_nt for specifying a circuit configuration of an integrated circuit (target circuit) to be subjected to Monte Carlo analysis, and inputting electrical characteristics (element characteristic information) of elements constituting the target circuit And the step of performing

In this embodiment, as described above, the Gaussian distribution characteristic Chr_dst is used as the distribution characteristic Chr_dst. As described above, in the function description netlist Lst_nt, the predetermined process data Dt_pr is used as the electric characteristic variable Var_elc, and the Gaussian distribution characteristic Chr_dst is given to the electric characteristic variable in the function representing the parasitic element value V_stry of the parasitic element D_stry. In other words, by providing the Gaussian distribution characteristic Chr_dst to the bottom capacitance CBAL per unit wiring area, the sheet resistance value RAL of the wiring, the fringe capacitance CFAL per unit wiring fringe length, etc. There is an effect that it can be executed well and easily.

Further, a second step (step Q2) following the first step is based on the distribution characteristic Chr_dst set for each electric characteristic variable Var_elc, and the value of each electric characteristic variable Var_elc (specifically, RAL or This is a step of setting a value such as CBAL.

A third step (step Q3) following the second step is a parasitic element value V_stry (specifically, a parasitic element value V_stry for each parasitic element D_stry) based on the value of the electrical characteristic variable Var_elc set in the second step. This is a step of obtaining a capacitance value, a parasitic resistance value, and the like.

A fourth step (step Q4) following the third step is a parasitic element value V_stry obtained in the third step.
Is a step of performing a circuit characteristic analysis of the target circuit by using.

The present Monte Carlo analysis includes the first step (step Q2) to the fourth step (step Q2).
4), by repeating the third step (step Q3) and the fourth step (step Q4) for the set number of sampling times N_smpl (step Q3).
→ Step Q4 → Step Q5 No → Step Q6
→ Step Q3 →...) A feature is that a Monte Carlo analysis is performed as a statistical analysis, thereby obtaining a variation width of circuit characteristics.

When the circuit characteristic analysis is executed for the set number of sampling times N_smpl (that is, step Q5).
FIG. 16 shows the variation in the calculated circuit characteristics (specifically, the signal delay time and the power consumption of the integrated circuit).
After the step Q7 of outputting as a histogram as shown in (b) is executed, the Monte Carlo analysis ends (step Q8).

As described above, the Monte Carlo analysis method is used for the variation analysis, and the parasitic element value V_ of the designated parasitic element D_stry is used.
Var_elc electrical characteristic variable in function expressing stry
In accordance with a Gaussian distribution for sampling the number of times N_smpl, and using each value to execute Monte Carlo analysis that can easily realize statistical variation analysis of circuit characteristics due to variation in wiring process and the like, which was difficult in the past. There is an effect that a circuit simulation can be performed. By executing such a circuit simulation, a variation (histogram) of the circuit characteristic reflecting a variation of predetermined process data as an electrical characteristic variable Var_elc (in a function expressing a parasitic element value V_stry of a desired parasitic element D_stry) Is obtained.
Furthermore, based on the histogram of the variation in the circuit characteristics,
Statistical analysis such as obtaining the center value or σ value of the circuit characteristics, and considering the strength of the correlation between the predetermined process data (or the parasitic element value V_stry) as the electric characteristic variable Var_elc and the circuit characteristics is performed with high accuracy. This has the effect that it can be easily executed.

In the above description of the Monte Carlo analysis, the distribution is given only for one kind of electric characteristic variable Var_elc, that is, the process data CBAL (bottom capacitance per unit wiring area) (FIG. 16A).
In this case, the outline of the distribution of the circuit characteristics (the histogram in FIG. 16B) can be said to be intuitively predictable.
However, usually, a plurality of kinds of electric characteristic variables Var_elc
Distribution is given to each of the electric characteristic variables Var_elc
The type of distribution may differ depending on the type of distribution), and a histogram indicating the variation in circuit characteristics corresponding thereto is obtained by the circuit simulation method (Monte Carlo analysis) of the present embodiment. In this case, since it is difficult to intuitively predict the distribution (variation) of the circuit characteristics, the circuit simulation (Monte Carlo analysis) of the present embodiment is particularly effective.

As described above, according to the circuit simulation method of the second embodiment, in the function description netlist Lst_nt, the process data Dt_pr is used as the electrical characteristic variable Var_elc, and the parasitic element value V_stry of the parasitic element D_stry is used. By providing the predetermined distribution characteristic Chr_dst, there is an effect that the statistical variation analysis of the circuit characteristic can be performed accurately and easily. Further, by analyzing the result of such statistical variation analysis, the parasitic element value V_try of each parasitic element D_stry is analyzed.
And the circuit characteristic can be obtained with high accuracy and the best value and worst value of the correlation.

<2.2.2 Circuit Simulation Program of Second Embodiment> The worst case analysis by the above-described circuit simulation method is executed by the CPU 56 executing a circuit simulation program described below.

The present circuit simulation program is a program for executing the circuit simulation method of the present embodiment, and can be read out by using a computer which is hardware for realizing the circuit simulation apparatus of the present embodiment. The storage medium (specifically, a magnetic storage unit such as a floppy disk or a magnetic tape, or an optical storage unit such as a CD-ROM (Compact Disk-ROM)) is provided.

The circuit simulation program read from the storage medium is stored in an internal storage means (specifically, a semiconductor storage device such as an EEPROM or a RAM, a magnetic disk) provided in a circuit simulation apparatus (computer). , Etc.)
It is read out as appropriate according to the execution of the circuit simulation method.

The present circuit simulation program comprises a first program step, a second program step, and a third program step.
It has a program step and a fourth program step. The first program step comprises the electrical characteristic variable V
This is a program step for setting a predetermined distribution of electrical characteristics for each of ar_elc. In particular, a first program step in the statistical analysis routine program includes a distribution characteristic Chr_d for each of the electrical characteristic variables Var_elc.
a program step for inputting st, a program step for inputting the number of samplings N_smpl for statistical analysis,
Including a program step of inputting a function description netlist Lst_nt for specifying a circuit configuration of a target circuit which is an integrated circuit, and a program step of inputting electrical characteristics (element characteristic information) of elements forming the target circuit. It is configured.

The second program step is a program step for setting the value of each electric characteristic variable Var_elc based on the distribution characteristic Chr_dst set for each electric characteristic variable Var_elc.

The third program step is a program step for obtaining a parasitic element value V_stry for each parasitic element D_stry based on the electric characteristic variable Var_elc set in the second program step.

The fourth program step is a program step for executing a circuit characteristic analysis using the parasitic element value V_stry obtained in the third program step.

This circuit simulation program is based on repeating the circuit characteristic analysis using the third program step and the fourth program step for the number of times of sampling N_smpl, thereby obtaining the distribution of circuit characteristics (for example, FIG. 16).
This is a statistical analysis routine program for obtaining a circuit characteristic value histogram as shown in FIG.

<2.2.3 Hardware Configuration of Second Embodiment> The circuit simulation apparatus of the present embodiment uses a function description netlist Lst_nt for specifying the circuit configuration of an integrated circuit in order to perform the above Monte Carlo analysis. Numericalizing means (corresponding to step Q3 in FIG. 17) for quantifying the parasitic element value V_stry described by the function, and means for executing a circuit simulation using the quantified parasitic element value V_stry (corresponding to step Q5) These are realized by a computer program. Therefore, the circuit simulation apparatus of the present embodiment is similar to the circuit simulation apparatus of the first embodiment in hardware (see FIG. 2), and executes a predetermined program to execute various arithmetic processing and the like.
6. A storage medium (hard disk device 52 in the figure) holding various programs such as the above-described circuit simulation program and netlist extraction program, storage means (memory 58 in the figure), and input of various operation commands and parameters. A keyboard 54, a CRT 60 for displaying a circuit simulation process and results, and peripheral devices (not shown) for reading the above-mentioned storage medium are mainly configured.

<3. Others> First Embodiment or Second Embodiment
As described above, the circuit simulation apparatus of the embodiment operates as a netlist extraction unit when the CPU 56 executes the netlist extraction program in the computer having the hardware configuration shown in FIG. A function description netlist Lst_nt can be generated from the data.

In the first and second embodiments, the parasitic element value V_stry of the wiring structure in the integrated circuit is described.
(Specifically, a circuit simulation (circuit characteristic analysis) is performed by using a function description netlist Lst_nt in which a function is described (parasitic capacitance element value and parasitic resistance element value). However, the present invention is not limited to this. Not something. As described above, for example, the parasitic capacitance and the parasitic resistance of the diffusion layer in the MOS transistor structure are also calculated from the capacitance and the sheet resistance per unit area or unit length and the layout data. Also, the function description netlist can be generated by the netlist extraction unit in the circuit simulation device of the present invention. Also,
Regarding the contact resistance and the through-hole resistance, the resistance value can be calculated from the resistance value per one hole and the number of holes, or from the resistance value per unit hole area and the hole area. A netlist can be generated as a function description. further,
Even when another parasitic element such as a parasitic inductor is described in a netlist extracted from the layout data, the function description can be similarly applied to the parasitic element. Therefore, the simulation unit in the circuit simulation apparatus of the present invention can perform a circuit characteristic variation analysis (worst case analysis, Monte Carlo analysis, etc.) by circuit simulation using such various function description netlists.

[0128]

According to the first circuit simulation method, the recording medium on which the first circuit simulation program is recorded, or the first circuit simulation apparatus according to the present invention, the integrated circuit to be simulated is obtained by the function description netlist. The circuit configuration is specified. For this reason, when the layout data is the same and the process is changed or the process varies, the definition of the variable value in the function description netlist is corrected without re-extracting the netlist from the layout data, and the circuit simulation is performed. , It is possible to easily predict a change in circuit characteristics due to a change or variation in the process. Further, when the layout data is obtained but the process is undetermined, by repeating the circuit simulation while variously changing the definition of the variable value in the function description netlist, it is possible to determine a process having desired circuit characteristics. Process optimization can be performed.

According to the second circuit simulation method, the recording medium on which the second circuit simulation program is recorded, or the second circuit simulation apparatus according to the present invention, the predetermined process data is stored in the function description netlist by using the electrical characteristics. By giving variation to the process data by using it as a variable indicating the value (electrical characteristic variable), the maximum value and the minimum value (or the best value and the worst value) of the variation in the circuit characteristics can be obtained. As a result, worst-case analysis for analyzing variations in circuit characteristics due to variations in wiring processes and the like, which has been difficult in the past, can be performed with high accuracy.

According to the third or fourth circuit simulation method, the recording medium storing the third or fourth circuit simulation program, or the third or fourth circuit simulation apparatus according to the present invention, the function description netlist A circuit which uses predetermined process data as a variable indicating an electrical characteristic value (electrical characteristic variable) and gives a predetermined distribution characteristic to the predetermined process data, thereby reflecting a variation in the predetermined process data. The variation (distribution) of the characteristics can be obtained.
As a result, variations (distribution) of circuit characteristics due to variations in wiring processes and the like, which were difficult in the past, are obtained, and a center value or σ value of the circuit characteristics is obtained based on the variations, or predetermined process data as electrical characteristic variables is obtained. Statistical analysis such as consideration of the strength of correlation between (or a parasitic element value) and circuit characteristics can be performed accurately and easily.

According to the fifth to seventh circuit simulation methods, the recording medium storing the fifth circuit simulation program, or the fifth circuit simulation apparatus according to the present invention, the configuration of the integrated circuit to be simulated is reduced. The generated netlist is generated, and in the generated netlist, the value of the parasitic capacitance or the parasitic resistance is a variable per unit area or per unit length, such as a capacitance value per unit area or a resistance value or a sheet resistance value. It is described as a function and the values of those variables are defined separately. Then, a circuit simulation is performed using such a function description netlist. For this reason, when the layout data is the same and the process is changed or the process varies, the definition of the variable value in the function description netlist is corrected without re-extracting the netlist from the layout data, and the circuit simulation is performed. , It is possible to easily predict a change in circuit characteristics due to a change or variation in the process. Further, when the layout data is obtained but the process is undetermined, by repeating the circuit simulation while variously changing the definition of the variable value in the function description netlist, it is possible to determine a process having desired circuit characteristics. Process optimization can be performed.

According to the eighth circuit simulation method of the present invention, the electric characteristics including a resistance value per unit length, a sheet resistance value, a capacitance value per unit area, and a capacitance value per unit length. Only the specified one of the values is used as a variable of the function representing the parasitic capacitance value or the parasitic resistance value. Therefore, for example, when only the interlayer film formation process is likely to be changed, the parasitic resistance (wiring resistance) is considered to not change. Therefore, by not specifying a variable for the sheet resistance, the parasitic resistance is represented by a numerical value. And describe the parasitic capacitance value as a function,
The description format of the parasitic resistance value and the parasitic capacitance value can be selected according to the purpose. Thus, an efficient netlist suitable for the purpose can be generated, and a circuit simulation can be performed using the netlist.

According to the ninth circuit simulation method of the present invention, a plurality of parasitic capacitances existing between the same nodes are combined with a function description and the number of elements is reduced. The size of the netlist can be reduced while retaining the advantages of the netlist generated by the method. Then, by using this netlist, circuit simulation can be performed efficiently.

According to the tenth circuit simulation method of the present invention, the number of nodes and the number of elements are reduced by combining the parasitic capacitance or the parasitic resistance as it is with the function description. The size of the netlist can be reduced while retaining the advantages of the netlist. Then, by using this netlist, circuit simulation can be performed efficiently.

According to the eleventh circuit simulation method of the present invention, first, a function description netlist is generated, and then a parasitic capacitance value or a parasitic resistance value described by a function in the netlist is digitized. Therefore, a function-free netlist can be obtained without having to generate a netlist again. Therefore, by performing the generation of the netlist only once, both the function description netlist and the function non-use netlist can be obtained according to the purpose.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a procedure for extracting a netlist according to a first configuration example of a netlist extraction unit in a circuit simulation apparatus of the present invention.

FIG. 2 is a block diagram showing a hardware configuration of a circuit simulation device as an embodiment of the present invention.

3A and 3B are a top view and a cross-sectional view illustrating an example of a wiring structure in an integrated circuit from which a netlist is extracted.

FIG. 4 is a diagram showing an equivalent circuit of the wiring structure shown in FIG. 3;

FIG. 5 is a diagram showing an example of a netlist obtained by a configuration example 1 of the netlist extraction unit.

FIG. 6 is a diagram showing an example of a netlist obtained by a configuration example 2 of the netlist extraction unit.

FIG. 7 is a flowchart illustrating a procedure of extracting a netlist according to a configuration example 3 of the netlist extraction unit.

FIG. 8 is a diagram showing an example of a circuit in which parasitic elements are combined by the configuration example 3 of the netlist extraction unit.

FIG. 9 is a diagram showing an example of a netlist obtained by a configuration example 3 of the netlist extraction unit.

FIG. 10 is a diagram showing the synthesis of a parasitic element with respect to a π-type division approximation circuit according to Configuration Example 3 of the netlist extraction unit.

FIG. 11 is a flowchart showing the operation of a digitizing means in Configuration Example 4 of the netlist extraction unit.

FIG. 12 is a functional block diagram showing a configuration of a simulation unit of the circuit simulation device according to the embodiment of the present invention.

FIG. 13 is a flowchart showing a basic operation of the simulation unit.

FIG. 14 is a diagram showing an example of a netlist obtained by a conventional netlist extraction method.

FIG. 15 is a flowchart illustrating a worst case analysis performed by the circuit simulation method according to the first embodiment.

FIG. 16A is a diagram illustrating a variation in bottom capacitance per unit wiring area as a histogram, and FIG. 16B is a diagram illustrating variation in circuit characteristic values as a histogram.

FIG. 17 is a flowchart illustrating a Monte Carlo analysis performed by the circuit simulation method according to the second embodiment;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 30 ... Input part 32 ... Function description net list reading means 34 ... Numericalization means 35 ... Analysis part 40 ... Output part 42 ... Circuit simulation information holding part 44 ... Function description net list holding part 46 ... Element characteristic information holding part 50 ... Main body (Computer body) 52 Hard disk drive 56 CPU 58 Memory R10 Parasitic resistance (wiring resistance) Cb Bottom capacitance (parasitic capacitance) Cf1, Cf2 Fringe capacitance (parasitic capacitance) RAL Sheet resistance CBAL Unit wiring area Bottom capacitance per unit CFAL ... Fringe capacitance per unit wiring fringe length D_stry ... Parasitic element Lst_nt ... Function description netlist

Claims (21)

[Claims] 1. A circuit simulation method for simulating an operation of an integrated circuit whose circuit configuration is specified by a netlist, wherein a constant which is a parameter indicating a geometric shape of a layout pattern of the integrated circuit and an integrated circuit are manufactured. Circuit configuration of the integrated circuit using a function expressed by a variable that is an electrical characteristic value determined by a process for indicating a parasitic element value including a value of a parasitic capacitance or a parasitic resistance of the layout pattern. A circuit simulation method, comprising: using a netlist describing the above, digitizing parasitic element values described by functions in the netlist, and performing the simulation using the digitized parasitic element values. 2. The circuit simulation method according to claim 1, wherein: a first step of setting a variation width for each of the variables; and a maximum value or a minimum value of the variables within the range of the variation width. A second step of calculating each of the parasitic element values from the function using any of the variables as a representative value of the variable; and a third step of performing the simulation using the parasitic element values calculated in the second step. Repeating the second and third steps for all combinations of the representative values for each of the variables to obtain a circuit characteristic value of the integrated circuit as a result of the simulation for each combination of the representative values A variation width of the circuit characteristic value. 3. The circuit simulation method according to claim 1, wherein: a first step of setting a predetermined distribution for each of the variables; and a representative of the variables based on the distribution set for each of the variables. A second step of setting a value; and a third step of calculating each of the parasitic element values from the function based on the representative value of the variable set in the second step.
And a fourth step of performing the simulation using the parasitic element value calculated in the third step. A second, third, and fourth step for all combinations of the representative values for each of the variables A circuit characteristic value of the integrated circuit is obtained as a result of the simulation for each combination of the representative values to obtain a distribution of the circuit characteristic value. 4. The circuit simulation method according to claim 3, wherein in the first step, a Gaussian distribution is set as the predetermined distribution. 5. A recording medium on which a circuit simulation program for causing a computer to execute a simulation of an operation of an integrated circuit whose circuit configuration is specified by a netlist is stored, and wherein a geometric shape of a layout pattern of the integrated circuit is indicated. A function expressed by a constant that is a parameter and a variable that is an electrical characteristic value determined by a process for manufacturing an integrated circuit, and is a function indicating a parasitic element value including a parasitic capacitance or a parasitic resistance value of the layout pattern. Using a netlist that describes the circuit configuration of the integrated circuit while using a numerical value of a parasitic element value described by a function in the netlist, and performing the simulation using the quantified parasitic element value. Circuit simulation for realizing functions on a computer A recording medium on which a computer program is recorded. 6. A recording medium on which the circuit simulation program according to claim 5 is recorded, wherein the circuit simulation program comprises: a first step of setting a variation width for each of the variables; A second step of calculating each of the parasitic element values from the function using either the maximum value or the minimum value of the variable as a representative value of the variable, and the parasitic element value calculated in the second step And a third step of performing the simulation by using the following. Repeating the second and third steps for all combinations of the representative values for each of the variables, and executing the simulation for each combination of the representative values As a result, a circuit characteristic value of the integrated circuit is obtained, thereby obtaining a variation width of the circuit characteristic value. Realizing functions referred to in the computer, a recording medium, characterized in that. 7. A recording medium on which the circuit simulation program according to claim 5 is recorded, wherein the circuit simulation program comprises: a first step of setting a predetermined distribution for each of the variables; and setting for each of the variables. A second step of setting a representative value of the variable based on the distribution obtained, and a third step of calculating each of the parasitic element values from the function based on the representative value of the variable set in the second step.
And a fourth step of performing the simulation using the parasitic element values calculated in the third step. The second, third and fourth steps are performed for all combinations of the representative values for each of the variables. Repeating the steps to obtain a circuit characteristic value of the integrated circuit as a result of the simulation for each combination of the representative values, thereby realizing a function of obtaining a distribution of the circuit characteristic value. Recording medium. 8. A recording medium on which the circuit simulation program according to claim 7 is recorded, wherein in the first step, a Gaussian distribution is set as the predetermined distribution. 9. A circuit simulation apparatus for simulating an operation of an integrated circuit whose circuit configuration is specified by a netlist, wherein a constant which is a parameter indicating a geometric shape of a layout pattern of the integrated circuit and an integrated circuit are manufactured. Circuit configuration of the integrated circuit using a function expressed by a variable that is an electrical characteristic value determined by a process for indicating a parasitic element value including a value of a parasitic capacitance or a parasitic resistance of the layout pattern. A circuit simulation apparatus, comprising: using a netlist describing the above, digitizing a parasitic element value described by a function in the netlist, and performing the simulation using the digitized parasitic element value. 10. The circuit simulation apparatus according to claim 9, wherein: setting means for setting a variation width for each of the variables; and a maximum value or a minimum value of the variables within the range of the variation width. Element value calculation means for calculating each of the parasitic element values from the function using the above as a representative value of the variable, and simulation execution means for performing the simulation using the parasitic element value calculated by the element value calculation means And for each combination of the representative values for each of the variables, repeatedly performing the calculation of the parasitic element value by the element value calculation means and the simulation by the simulation execution means, and performing the simulation for each combination of the representative values. Obtaining a circuit characteristic value of the integrated circuit as a result of Circuit simulation apparatus comprising: an analyzing means for determining the variation range of sexual value. 11. The circuit simulation apparatus according to claim 9, wherein: a first setting unit that sets a predetermined distribution for each of the variables; and a setting of the variable based on the distribution set for each of the variables. Second setting means for setting a representative value; calculating means for calculating each of the parasitic element values from the function based on the representative value of the variable set by the second setting means; Simulation execution means for performing the simulation using the parasitic element value; setting of the representative value of the variable by the second setting means for all combinations of the representative value for each of the variables;
The calculation of each of the parasitic element values by the calculation unit and the simulation by the simulation execution unit are repeatedly executed to obtain a circuit characteristic value of the integrated circuit as a result of the simulation for each combination of the representative values. A circuit simulation apparatus, comprising: analysis means for obtaining a distribution of circuit characteristic values. 12. The circuit simulation apparatus according to claim 11, wherein said first setting means sets a Gaussian distribution as said predetermined distribution. 13. A circuit simulation method for simulating the operation of an integrated circuit whose circuit configuration is specified by a netlist, comprising: a constant which is a parameter indicating a geometric shape of a layout pattern of the integrated circuit; A function that is expressed by a variable that is an electrical characteristic value determined by a process for performing the operation, and that derives a function indicating a value of a parasitic capacitance or a parasitic resistance of the layout pattern.
A second step of obtaining a value of the variable corresponding to a process for manufacturing an integrated circuit to be simulated.
A first netlist representing the value of the parasitic capacitance or parasitic resistance based on the description of the function derived in the first step and the definition of the value of the variable obtained in the second step. A fourth step of generating a numerical value of a parasitic capacitance value or a parasitic resistance value described as a function in the first netlist generated in the third step; and a net generated in the third step. A fifth step of specifying the circuit configuration of the integrated circuit in a list and simulating the operation of the integrated circuit using the parasitic capacitance value or the parasitic resistance value quantified in the fourth step. Circuit simulation method. 14. The circuit simulation method according to claim 13, wherein, in the first step, a function indicating a value of the parasitic capacitance is derived using a capacitance value per unit area or unit length of the layout pattern as the variable. A circuit simulation method. 15. The circuit simulation method according to claim 13, wherein, in the first step, a function indicating a value of the parasitic resistance using a resistance value or a sheet resistance value per unit length of the layout pattern as the variable is used. A circuit simulation method characterized in that it is derived. 16. The circuit simulation method according to claim 13, wherein the layout pattern has a resistance value per unit length, a sheet resistance value, a capacitance value per unit area, and a unit length. A sixth step of designating an electric characteristic value to be used as the variable from among the electric characteristic values including a capacitance value per unit; and in the first step, the electric characteristic designated in the sixth step A circuit simulation method, wherein the function is derived only for a parasitic capacitance and a parasitic resistance calculated using values. 17. The circuit simulation method according to claim 13, wherein the circuit is connected in parallel in a circuit configuration described by the first netlist generated in the third step. A seventh step of generating a second netlist in which the number of elements is reduced by synthesizing parasitic capacitances. In the fourth step, instead of the first netlist generated in the third step, In the second netlist generated in the seventh step, the parasitic capacitance value or the parasitic resistance value described as a function in the second netlist is quantified. In the fifth step, the first netlist generated in the third step is replaced with the first netlist. The circuit configuration of the integrated circuit is specified by the second netlist generated in the seventh step, and the parasitic capacitance value quantified in the fourth step is obtained. Or simulating the operation of the integrated circuit using a parasitic resistance value. 18. The circuit simulation method according to claim 13, wherein a parasitic capacitance or a parasitic capacitance is included in a circuit configuration described by the first netlist generated in the third step. An eighth step of generating a third netlist with a reduced number of nodes by performing resistance synthesis is provided. In the fourth step, instead of the first netlist generated in the third step, In the third netlist generated in the eighth step, the parasitic capacitance value or the parasitic resistance value described by the function is converted into a numerical value. In the fifth step, the first netlist generated in the third step is replaced with the first netlist. The third netlist generated in the eighth step specifies the circuit configuration of the integrated circuit, and the parasitic capacitance quantified in the fourth step A method of simulating the operation of the integrated circuit using a value or a parasitic resistance value. 19. The circuit simulation method according to claim 13, wherein a value of the variable obtained in the second step is substituted for the function derived in the first step. By doing
A ninth step of generating a fourth netlist in which the values of the parasitic capacitance or the parasitic resistance in the first to third netlists are quantified is provided. 20. A recording medium on which a circuit simulation program for causing a computer to execute an operation of an integrated circuit whose circuit configuration is specified by a netlist is recorded, the recording medium showing a geometric shape of a layout pattern of the integrated circuit. A function represented by a constant that is a parameter and a variable that is an electrical characteristic value determined by a process for manufacturing an integrated circuit, and derives a function indicating a value of a parasitic capacitance or a parasitic resistance of the layout pattern. First
A second step of obtaining a value of the variable corresponding to a process for manufacturing an integrated circuit to be simulated.
A first netlist representing the value of the parasitic capacitance or parasitic resistance based on the description of the function derived in the first step and the definition of the value of the variable obtained in the second step. A fourth step of generating a numerical value of a parasitic capacitance value or a parasitic resistance value described as a function in the first netlist generated in the third step; and a net generated in the third step. A fifth step of specifying the circuit configuration of the integrated circuit in a list and simulating the operation of the integrated circuit using the parasitic capacitance value or the parasitic resistance value quantified in the fourth step. A recording medium on which a simulation program is recorded. 21. A circuit simulation apparatus for simulating the operation of an integrated circuit whose circuit configuration is specified by a netlist, comprising: a constant which is a parameter indicating a geometric shape of a layout pattern of the integrated circuit; A function deriving means for deriving a function represented by a variable that is an electrical characteristic value determined by a process for performing the simulation, the function indicating a value of a parasitic capacitance or a parasitic resistance of the layout pattern; Value obtaining means for obtaining the value of the variable corresponding to the process for manufacturing the integrated circuit, and a description of the function derived by the function deriving means and a definition of the value of the variable obtained by the value obtaining means. The netlist representing the value of the parasitic capacitance or the parasitic resistance is generated as a first netlist. List generating means, numerical value converting means for numerically expressing a parasitic capacitance value or a parasitic resistance value described by a function in the first netlist, and a circuit configuration of the integrated circuit specified by the first netlist. And a simulation executing means for performing the simulation using the parasitic capacitance value or the parasitic resistance value quantified by the quantifying means.