CN100474311C - IC design for optimizing manufacturability - Google Patents
IC design for optimizing manufacturability Download PDFInfo
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- CN100474311C CN100474311C CNB038270803A CN03827080A CN100474311C CN 100474311 C CN100474311 C CN 100474311C CN B038270803 A CNB038270803 A CN B038270803A CN 03827080 A CN03827080 A CN 03827080A CN 100474311 C CN100474311 C CN 100474311C
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- G06F2119/18—Manufacturability analysis or optimisation for manufacturability
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Abstract
Library design elements (102) are analyzed for manufacturability to be used in designing an IC chip to be manufactured using a particular manufacturing process. The library design elements from a library are obtained. Manufacturability attributes (104) of the library design elements are determined for the particular manufacturing process, where manufacturability attributes include yield-related attributes. Library views (106) with manufacturability attributes for the library design elements are then generated, which are utilizing by an electronic design automation (EDA) tool.
Description
Technical field
The present invention relates to integrated circuit (IC) design, and more particularly, relate to the integrated circuit (IC) design of optimizing manufacturability.
Background technology
The design of integrated circuit (IC) chip is made up of discrete design element all size and complicacy, that be also referred to as intelligent attributes (IP) element (intellectual property element) (discrete design element).Smallest elements is commonly referred to standard block.The bigger assembly of element can be commonly referred to as piece by interconnection to produce complete function.A plurality of by the IC chip of interconnection with the generation made.
For design IC chip, to the manufacture process of appointment, be necessary to produce this unit consistent or the assembly of piece with particular manufacturing process, provide the various functional and performance that allows deviser's design and optimize assigned I C chip to select simultaneously.Be these unit that particular manufacturing process produces and the assembly of piece, be commonly referred to as the storehouse together with the detailed description of characteristic to them.For allowing design system, the design element in the storehouse of certain fabrication techniques generation/parts produce IC chip efficient and optimization.Storehouse design element (unit and piece) is organized into the exclusive data that comprises the different characteristic relevant with their purposes in chip design to be represented.The particular data that comprises the storehouse design element of these features represents to be called view.
In the traditional design flow process of the attribute that produces and characterize the storehouse, design and processing test chip in manufacturing plant are so that provide the information that allows design and create the storehouse.Test chip comprises array and the interconnection geometries of representing representative device, its analysis so that generate the device model that is suitable for by level simulators such as SPICE use, is used so that produce the performance view of corresponding storehouse design element in the sign of storehouse design element.Also the analytical test chip is so that be created on the design rule that uses in the design of storehouse design element.Describe the layout of storehouse design element in the mode of storehouse view, for example, comprise area occupied (footprint) information of storehouse design.Also analytical test chip so that create is provided for designing the design tool of the user interface of ICs, and comprises SPICE model, design rule and the corresponding tool of the self-verifying that is used for conforming to these rules.
Yet the test chip that uses in conventional design systems does not comprise being used for that passive and active parts that storehouse and product I Cs make up is estimated or prediction manufacturability and comprehensive structure of designing.Therefore, about the prediction of its manufacturability, the storehouse design element that does not also have fully assessment to produce by existing design system.
The readable format that uses a computer, such as GDSII, each unit design that expression uses Design kit to create.Have a plurality of different expressions of each unit design in the storehouse, each expression is called cell view.Some cell view are derived by other cell view.For example, regularly characterize (library timing characterization), create the timing view of each unit by SPICE model and GDSII view by being called the storehouse.LEF is the example of describing by the storehouse view of the required characteristic of wired program (router), and comprises area occupied and port location information.
Typical storehouse comprises about 500 unit.Yet, in the assembly of library unit, exist a plurality of layouts that are used to specify logic function and represent.These " modification " provide the different performance feature that can select and optimize application-specific.For example, have low-density high-performance, high function or have highdensity low performance, the low-power that is used for the identity logic function, typically can obtain in the different modification in being included in the storehouse.Yet,, do not provide the selection of relevant specific manufacturability correlation factor by the modification of existing technology generation owing to there is not the storehouse view to comprise manufacturability attribute.And, use the existing business software of typical storehouse view can not extract or use the manufacturability feature for any design element in the storehouse.
In building-up process, the functional advanced hardware of IC described being mapped to basic binary operator and logic array (logical breakdown) so that produce the expression that is called free logic (uncommittedlogic).Use physical library cells or piece, free logic is mapped to the certain logic connection layout, be commonly referred to the gate leve net list.Piece is placed and the wiring step produces piece level layout, by connecting to form in selected standard block and the wiring layer that is connected all elements.With various forms, for example GDSII represents layout.Final verification step guarantees to satisfy all design limit.In other general present practices, by the two or more steps between a software application execution advanced hardware description and the piece level layout.Design cycle with this method is typically expressed as " physics is synthetic " flow process.
In these design cycles, optimize specification (metrics) by being constrained to, determine the selection of storehouse design element such as the particular design restriction of speed and power and area consideration.Unresolved substantial manufacturability specification, yet, be used to chip estimate cost indirectly based on some field of manufacturability models.
Summary of the invention
The storehouse design element is analyzed manufacturability, use for use in design in the IC chip of specific manufacturing process manufacturing.Acquisition is from the storehouse design element in storehouse.To specific manufacturing process, determine the manufacturability attribute of storehouse design element, wherein, manufacturability attribute comprises the attribute relevant with yield rate.Then, produce the storehouse view that is used for the storehouse design element, use by electric design automation (EDA) instrument with manufacturability attribute.
Description of drawings
By understanding the present invention better, wherein, adopt the similar parts of similar numeral with reference to following description in conjunction with the accompanying drawings:
Fig. 1 is the exemplary design flow process;
Fig. 2 is an example process of the storehouse design element being determined manufacturability attribute;
Fig. 3 describes the exemplary study curve;
Fig. 4 describes the example process of the storehouse view that generates the storehouse design element with manufacturability attribute;
Fig. 5 describes the example process that generates the Variant Design element;
Fig. 6 describes the exemplary design flow process; And
Fig. 7 describes another exemplary design flow process.
Embodiment
The many concrete structures of following description, parameter or the like.Yet, will be appreciated that these describe the restriction be not considered as scope of the present invention, on the contrary, as the description of exemplary embodiment is provided.
As mentioned above, library of design elements is commonly used to design the IC chip.The storehouse comprises all required views of storehouse design element, comprises the attribute relevant with performance of storehouse design element.Yet, conventional libraries do not provide have the number that for example can predict each wafer non-defective unit tube core (GDW), the storehouse view of the manufacturability attribute of the attribute relevant with yield rate.Will be appreciated that manufacturability also comprises various IC characteristics, such as defective, impressionability, reliability or the like.Manufacturability is finally determined the earning rate of design.
In one exemplary embodiment, analyze the manufacturability attribute that the storehouse design element is determined the storehouse design element.Then, the storehouse element is generated the storehouse view, except that attribute of performance, also comprise manufacturability attribute.These storehouse views with manufacturability attribute can be used in the ICs that with design given process is had the manufacturability of increase in the design cycle.
With reference to figure 1, exemplary design flow process 100 has been described.102, obtain the storehouse design element.104, determine to comprise the manufacturability attribute of the attribute relevant for the storehouse design element with yield rate.112, generate the modification of storehouse design element, wherein, modification has the different manufacturability attribute outside the design element of storehouse.106, the storehouse view of the manufacturability attribute of generation storehouse design element and the computer-readable format of modification.108, the manufacturability that generates layout is estimated.110, select to be used for the optimum design elements of IC design.
I. generate view with manufacturability attribute
In one exemplary embodiment, consider existing design rule and intended target manufacturability models, be designed for the test chip of specific production facility and/or manufacturing process.Test chip comprises the expression of the spatial layout feature that comprises in the design element of existing storehouse.The yield rate at random and the system's yield rate factor that comprise existing manufacturing process from the data of test chip extraction.More detailed description can be used for determining at random the test chip with system's yield rate, can be referring to U.S. patent No.6,449,749, title is " SYSTEM AND METHOD FOR PRODUCTYIELD PREDICTION ", September 10 in 2002 announces, and all comprises for your guidance at this.
With reference to figure 2, example process 200 is described so that determine the manufacturability attribute of storehouse design element.202, generate the mask set that is used for test chip.204, in will being used for making the manufacturing process of IC, use mask set.206, in manufacturing process, use mask set manufacturing test chip.208, the test chip that the operational analysis instrument is analyzed manufacturing is determined the manufacturability attribute of manufacture process, and the manufacturability attribute of storehouse design element.
Then, utilize the manufacturability attribute of determining by test chip to calibrate various simulation softward instruments, such as YRS, Optissimo or the like.The analog result of the manufacturability of storehouse design element comprises a plurality of manufacturability attribute, comprise layout limited yield rate (LY), make the quantitative description of risks and assumptions (MRF), process window and the relation between LY and MR.Sum up in the view of storehouse and make Simulation result, this result can be by the utilization of electric design automation (EDA) instrument.
In one exemplary embodiment, based on the historical production characteristic of specifying manufacturing process, current manufacturability attribute and/or the experience of learning rate (learning rate) aspect, for the technical maturity stage in various futures, estimate the manufacturability attribute of manufacturing process.Then, for the different time frame of estimating (projection) corresponding to the various process degree of ripeness, simulate the manufacturability of specified design element, and be also illustrated in the view of storehouse for corresponding time frame and specified bank design element.
For example, Fig. 3 describes the exemplary study curve.As shown in Figure 3, in a period of time, the ICs amount that produces in manufacturing process increases.Therefore, when low amount,, obtain to hang down yield rate corresponding to the point 304 in the learning curve 302 of the time period more more Zao than point 306.
In one exemplary embodiment, collection based on representative traditional die design and/or memory block/logical organization and corresponding manufacturability data, utilize the Statistic Design data, definition is used to specify the model of manufacturing process and method for designing, this model description be used for interconnecting manufacturability and the attribute of storehouse design element and relation between the logic connectivity of wiring of storehouse design element.This relation is included in the model, is also included within simultaneously in the view of storehouse.
The storehouse view is included in the computer readable matrix, wherein the various manufacturability attribute of different time frame specified bank design element collection is made form and is comprised various interconnection manufacturability models.
With reference to figure 4, example process 400 is described, generate the storehouse view of storehouse design element with manufacturability attribute.402, sign will be used for making the manufacturing process of IC design.For example, 404, use manufacturing process manufacturing test chip.406,408 and 410, the use test chip characterizes manufacturing process, so that produce design rule, design tool and SPICE model respectively.412, storehouse manufacturer uses design rule, design tool and SPICE model, generates the library of design elements that is used for manufacturing process, characterizes in 414.
416, based on design rule, design tool and SPICE model, the java standard library view of generation unit.For example, regularly view is described as the unit loads by carrying out a plurality of SPICE model constructions and the function of input voltage slope with the Performance Characteristics of unit in the storehouse.The layout abstract view is described the required characteristic of wired program, and comprises area occupied and port location information.Function view is described the binary logic function relevant with this unit.Other views are used for power consumption, signal integrity or the like the attribute of description unit.View be exclusively used in usually EDA manufacturer instrument-promptly, design tool reads by cell view so that determine and attribute by the relevant storehouse element of the operation of this instrument execution.Cell layout view is also described by the computer-readable format of for example GDSII.
418, the use test chip is determined the scope of manufacturability parameters, and many parameters are according to the various forms statement of the data relevant with yield rate.For example, in 420,, determine at random and system's yield rate based on the data that obtain from test chip.In addition, also, extract other manufacturability features, such as impressionability specification, process allowance and reliability characteristic by the analysis of test chip data.422, use relevant with yield rate and other manufacturability data, the calibrated analog Software tool is such as yield rate slope simulator (YRS), Optissimo or the like.
424, use the historical yield rate ramp data of various spatial layout features by YRS, thereby the temporal correlation of these features is calibrated to the function of given manufacturability volume.
426, use manufacturability simulator to analyze each design element in the storehouse so that describe its manufacturability attribute.Simulation result comprises limited layout yield rate (LY), manufacturability risks and assumptions (MRF), describes the process window that is used for this layout in the mode of relative quantification, and LY and MRF are to the time, and the relation between LY and MRFs (for example weight factor).428, generate the storehouse view of storehouse design element with manufacturability attribute.
II. generate modification
In one exemplary embodiment, for the manufacturability of the storehouse design element that allows to strengthen,,, create the modification of storehouse design element such as the minimum cost of area, performance or power usually with other design parameters.Be equivalent to original library design elements on these modification functions, can be but provide by effectively compromise, for example area and/or performance factor strengthen the specified design replacement scheme of the manufacturability attribute of storehouse design element.
With reference to figure 5, example process 500 is described so that generate different designs element (modification).406,408 and 410, generate the design rule, design tool and the SPICE model that are used for manufacturing process.502, adopt the cell library view of computer-readable format such as GSDII to generate the storehouse.Typical storehouse can comprise about 100 basic logic functions, and each of these basic functions is had a plurality of driving force modification, makes total unit number reach about 500.504, the change layout is so that change the manufacturability attribute of this layout.506, by in some specified limit, for strengthening the trade off design limit of permission of manufacturability, the manufacturability simulations of power, area for example characterizes the manufacturability attribute of design element by evaluation.508, generate the storehouse view of modification.510, characterize modification so that produce design tool and the required storehouse view of flow process.512, use manufacturability simulations, generate the manufacturing attribute of modification.514, generate the storehouse view of the modification of this manufacturing attribute.516, the storage modification.Describe to generate modification in more detail, can be referring to U.S. provisional application sequence number No.60/437,922, title be " YIELDIMPROVEMET ", submission on January 2nd, 2003, its content all comprises for your guidance at this.
III. the manufacturability that generates design is estimated
With reference to figure 6, exemplary design flow process 600 is described.602, obtain library of design elements.604, obtain the advanced specification of the desired function of circuit.This specification also comprises design constraints/rules, such as performance, power and area.606,, generate design instruction based on the specification and the library of design elements of desired function.In one exemplary embodiment, instructions is a net list, and its form is the tabulation that comprises standard block and other tectonic blocks, and defines all interelement connectivities.In addition, 614, generate the storehouse view of piece, such as simulation, storer, I/O or the like.608, press the piece level and create layout, comprise being connected in selected storehouse design element and the wiring layer, then, connect all storehouse design elements.610, place and be connected all pieces so that part is used the storehouse view of piece and created chip layout.612, the calibrating chip layout is for confirmation to be satisfied all design limit and not to violate design rule.
616, the instructions of input design.Instructions can be the net list in structural level description block or chip design, in other words, specializes according to the layout of the Register Transfer Level instructions of the tabulation, required of the interconnection basic element of character or chip functions or existing piece or chip.618, use the manufacturability analysis device, based on the manufacturability of the storehouse view analysis design of storehouse design element.622, the manufacturability that generates this design is estimated.It can be the function of manufacturing time frame that manufacturability is estimated, and decomposes by required design block.620, generate the manufacturability view for the design block in 614, if also do not create these views.Manufacturability in 622 is estimated as the possibility that the user provides the manufacturability properties of understanding assigned I C or IP piece.In addition, in one exemplary embodiment, can use manufacturability to estimate to estimate the temporal correlation of the manufacturability of design.
More particularly, to any design element, the characteristic of Virtual Learning curve (for example the yield rate that is obtained by historical data is to the correlativity of manufacture) can be input to simulator tool, in YRS.With reference to figure 3, suppose user's level of the technical maturity relevant with learning curve, can use by the formative historical data of YRS instrument and estimate the yield rate of specific layout features of IC design time relationship.These information provide extra criterion for selecting modification, allow in life of product the more accurate cost/earning rate of design to be estimated.In addition, by discerning the design element of minimum yield rate, suppose the level of technical maturity, this design system allows the prediction and the optimization of entire I C design finished product rate in time.When manufacturing process developed, the characteristic that relates to the manufacturability of library unit also changed, thereby can dynamically adjust the best mapping of chip piece with library unit.
IV. select optimum design elements
With reference to figure 7, exemplary design flow process 700 is described so that select optimum design elements.702, estimate and modification optimal design based on manufacturability from 516 design element.By the choice function of change synthetics based on manufacturability attribute and other design limit selected cell or pieces, can optimal design.In addition, the existing network table that can resolve design is kept necessary function simultaneously and is observed other design limit so that substitute variants.
704, whether complies with design constraints of this revised design is determined in the design of analyzing revision.If violate restriction, so, press the incremental compilation design so that satisfy restriction, or substitute by the lower production modification of the next one that substitutes of identical function.As described in Figure 7, repeat this process till satisfying restriction.When satisfying restriction, generate the design instruction of revision, as the net list of revision.
Although described exemplary embodiment, under the situation that does not deviate from spirit of the present invention and/or scope, can make various improvement.Therefore, the present invention should not be construed as be limited to shown in the figure and above-mentioned described particular form.
Claims (38)
1. a method of analyzing the manufacturability of storehouse design element is used to design the IC chip that uses particular manufacturing process to make, and described method comprises:
Obtain the storehouse design element from the storehouse;
Determine the manufacturability attribute of described storehouse design element for described particular manufacturing process, wherein, manufacturability attribute comprises the attribute relevant with yield rate; And
Before design IC chip, generate storehouse view, wherein, in design IC chip processes, use described storehouse view by electronic design automation tool with manufacturability attribute for described storehouse design element.
2. determine the method for claim 1, wherein that manufacturability attribute comprises:
Generation comprises the test chip design of described storehouse design element;
Use described test chip design and described particular manufacturing process manufacturing test chip; And
Analyze the test chip of made, to determine the manufacturability attribute of described storehouse design element.
3. method as claimed in claim 2, wherein, the test chip of analyzing made comprises:
The spatial layout feature of storehouse design element is compared with the spatial layout feature of making on described test chip; And
Based on described comparison, determine the manufacturability attribute of described storehouse design element.
4. method as claimed in claim 2, wherein, the test chip of analyzing made comprises:
Obtain data from described test chip, to generate yield rate and system's yield model at random.
5. method as claimed in claim 4 further comprises:
Determine impressionability, process allowance and reliability from described test chip.
6. the method for claim 1 further comprises:
Revise the manufacturability attribute of described storehouse design element by the feature of revising described storehouse design element, create the Variant Design element based on the storehouse design element.
7. method as claimed in claim 6 further comprises:
Determine the change that Variant Design circuit elements design attribute causes owing to the manufacturability attribute of being revised.
8. method as claimed in claim 7, wherein, described design attributes comprises performance, power, area and yield rate.
9. method as claimed in claim 6 further comprises:
Generate storehouse view with manufacturability attribute for the Variant Design element.
10. method as claimed in claim 9 further comprises:
Use has the storehouse design element of manufacturability attribute and the storehouse view of Variant Design element; And
Based on described storehouse view, analyze the manufacturability of IC design.
11. method as claimed in claim 10 further comprises:
By selecting the Variant Design element, revise the IC design.
12. method as claimed in claim 11 further comprises:
Determine whether the design of revising satisfies the restriction of user's appointment; And
When not satisfying the restriction of user's appointment,, revise the IC design by selecting another Variant Design element.
13. method as claimed in claim 12 wherein, is revised the IC design and is comprised:
The yield rate factor of employing and time correlation is selected the Variant Design element.
14. method as claimed in claim 13, wherein, described and yield rate factor time correlation is characterized in the variation of yield rate in a period of time.
15. the method for claim 1 further comprises:
Manufacturing process and method for designing for appointment, collection based on representative traditional die design, memory block or logical organization and corresponding manufacturability data, utilize the Statistic Design data, the model of the relation between the manufacturability of wiring of the described storehouse design element that is used to interconnect is described in definition.
16. the method for a designing integrated circuit, described method comprises:
Obtain the storehouse design element from the storehouse;
Determine the manufacturability attribute of described storehouse design element, wherein, manufacturability attribute comprises the attribute relevant with yield rate;
Based on described storehouse design element, generate the Variant Design element, wherein, described Variant Design element has the manufacturability attribute of modification;
Before designing integrated circuit, generate storehouse view with manufacturability attribute for described storehouse design element and described Variant Design element; And
In electronic design automation tool, use storehouse view, design described integrated circuit with the manufacturability attribute that is used for described storehouse design element and Variant Design element.
17. method as claimed in claim 16 wherein, determines that manufacturability attribute comprises:
Based on described storehouse design element, design test chip design;
Use described test chip design, make test chip; And
The test chip of analyzing made is to determine described manufacturability attribute.
18. method as claimed in claim 17, wherein, the test chip of analyzing made comprises:
Obtain data to generate yield rate and system's yield model at random from described test chip.
19. method as claimed in claim 18 further comprises:
Determine impressionability, process allowance and reliability from described test chip.
20. method as claimed in claim 16 further comprises:
The manufacturability attribute of the modification of the manufacturability attribute of described storehouse design element and described Variant Design element is described according to computer-readable format.
21. method as claimed in claim 20, wherein, described computer-readable format is the storehouse view that is used in the electronic design automation tool.
22. method as claimed in claim 21, wherein, designing integrated circuit comprises:
The storehouse view of the manufacturability attribute of the manufacturability attribute of use storehouse design element and the modification of described Variant Design element; And
Based on the storehouse view that is generated, analyze the manufacturability of the layout of described integrated circuit.
23. method as claimed in claim 22, wherein, designing integrated circuit comprises:
Adopt the restriction of user's appointment, select to be used for the best parts of the layout of described integrated circuit from described storehouse design element and Variant Design element.
24. method as claimed in claim 23 wherein, selects best parts to comprise:
Determine whether to satisfy the restriction of user's appointment; And
When not satisfying the restriction of described user's appointment,
The Variant Design element of manufacturability attribute of repeatedly selecting to have modification is up to full
Till the restriction of the described user's appointment of foot.
25. method as claimed in claim 16, wherein, designing integrated circuit comprises:
Adopt the yield rate factor with time correlation, select to be used for the best parts of the layout of described integrated circuit from described storehouse design element and Variant Design element.
26. method as claimed in claim 25, wherein, described and yield rate factor time correlation is characterized in the variation of yield rate in a period of time.
27. method as claimed in claim 25 further comprises:
Based on the parts of the minimum yield rate of described layout, predict the yield rate of time dependent layout.
28. method as claimed in claim 16 further comprises:
Manufacturing process and method for designing for appointment, collection based on representative traditional die design, memory block or logical organization and corresponding manufacturability data, utilize the Statistic Design data, the model of the relation between the manufacturability of wiring of the described storehouse design element that is used to interconnect is described in definition.
29. a system that analyzes the manufacturability of storehouse design element is used to design the IC chip that uses particular manufacturing process to make, described system comprises:
Storehouse with storehouse design element; And
Manufacturability simulator is configured to:
Determine the manufacturability attribute of described storehouse design element, wherein, described manufacturability attribute comprises the attribute relevant with yield rate; And
Before designing integrated circuit, generate storehouse view, and wherein, in the process of design IC chip, utilize described storehouse view by electronic design automation tool with manufacturability attribute for described storehouse design element.
30. system as claimed in claim 29 further comprises:
The test chip that uses particular manufacturing process to make, wherein said test chip comprises the feature corresponding to one or more described storehouses design element, and wherein said manufacturability simulator is analyzed described test chip to determine the manufacturability attribute of described storehouse design element.
31. system as claimed in claim 30, wherein, described test chip comprises determines to generate the feature of the data of yield rate and system's yield model at random.
32. system as claimed in claim 31, wherein, described test chip comprises the feature of definite impressionability, process allowance and reliability.
33. system as claimed in claim 29, wherein, described manufacturability simulator generates the Variant Design element corresponding to the storehouse design element by revising the manufacturability of described storehouse design element.
34. system as claimed in claim 33, wherein, described manufacturability simulator generates the storehouse view with manufacturability attribute for described Variant Design element.
35. system as claimed in claim 34 further comprises:
The manufacturability analysis device is configured to the storehouse view based on described storehouse design element, determines that the manufacturability of IC design is estimated.
36. system as claimed in claim 35 further comprises:
The manufacturability optimizer is configured to the restriction based on described manufacturability estimation, Variant Design element and user's appointment, optimizes the IC design.
37. system as claimed in claim 36, wherein, described manufacturability optimizer based on the yield rate factor of time correlation, optimize the IC design.
38. system as claimed in claim 29 further comprises:
Specify the model of manufacturing process and method for designing, this model description relation between the manufacturability of wiring of described storehouse design element that is used for interconnecting, wherein, collection based on representative traditional die design, memory block or logical organization and corresponding manufacturability data utilizes the Statistic Design data to limit this model.
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|---|---|---|---|
| PCT/US2003/029758 WO2005036422A1 (en) | 2003-09-16 | 2003-09-16 | Integrated circuit design to optimize manufacturability |
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| CN1839389A CN1839389A (en) | 2006-09-27 |
| CN100474311C true CN100474311C (en) | 2009-04-01 |
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| CN (1) | CN100474311C (en) |
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| AU2003291579A1 (en) | 2003-01-02 | 2004-07-29 | Pdf Solutions, Inc. | Yield improvement |
| US7902878B2 (en) * | 2008-04-29 | 2011-03-08 | Qualcomm Incorporated | Clock gating system and method |
| US8677292B2 (en) * | 2009-04-22 | 2014-03-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cell-context aware integrated circuit design |
| CN102016749B (en) | 2009-04-29 | 2014-04-23 | 高通股份有限公司 | Clock gating system and method |
| CN102542116B (en) * | 2012-01-06 | 2014-12-17 | 深圳市汉普电子技术开发有限公司 | Method and device of DFM (Design for Manufacturability) analysis automation |
| JP6370148B2 (en) * | 2014-07-30 | 2018-08-08 | 株式会社ディスコ | Holding jig generator |
| DE102019124928A1 (en) | 2018-09-28 | 2020-04-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | INTEGRATED CIRCUIT DESIGN USING FUZZY MACHINE LEARNERS |
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| US5539652A (en) * | 1995-02-07 | 1996-07-23 | Hewlett-Packard Company | Method for manufacturing test simulation in electronic circuit design |
| US5666288A (en) * | 1995-04-21 | 1997-09-09 | Motorola, Inc. | Method and apparatus for designing an integrated circuit |
| US5754826A (en) * | 1995-08-04 | 1998-05-19 | Synopsys, Inc. | CAD and simulation system for targeting IC designs to multiple fabrication processes |
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|---|---|---|---|---|
| JPH0981623A (en) * | 1995-09-19 | 1997-03-28 | Fujitsu Ltd | Cad system and lsi design method |
| US5956497A (en) * | 1997-02-26 | 1999-09-21 | Advanced Micro Devices, Inc. | Methodology for designing an integrated circuit using a reduced cell library for preliminary synthesis |
| JP2002076086A (en) * | 2000-08-29 | 2002-03-15 | Hitachi Ltd | System for estimating yield of electronic device |
-
2003
- 2003-09-16 WO PCT/US2003/029758 patent/WO2005036422A1/en active Application Filing
- 2003-09-16 CN CNB038270803A patent/CN100474311C/en not_active Expired - Fee Related
- 2003-09-16 JP JP2005509541A patent/JP2007529100A/en active Pending
- 2003-09-16 DE DE10394299T patent/DE10394299T5/en not_active Withdrawn
- 2003-09-16 AU AU2003272617A patent/AU2003272617A1/en not_active Abandoned
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5539652A (en) * | 1995-02-07 | 1996-07-23 | Hewlett-Packard Company | Method for manufacturing test simulation in electronic circuit design |
| US5666288A (en) * | 1995-04-21 | 1997-09-09 | Motorola, Inc. | Method and apparatus for designing an integrated circuit |
| US5754826A (en) * | 1995-08-04 | 1998-05-19 | Synopsys, Inc. | CAD and simulation system for targeting IC designs to multiple fabrication processes |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2005036422A1 (en) | 2005-04-21 |
| DE10394299T5 (en) | 2006-08-10 |
| CN1839389A (en) | 2006-09-27 |
| JP2007529100A (en) | 2007-10-18 |
| AU2003272617A1 (en) | 2005-04-27 |
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