WO2007105926A1 - Puce à circuits intégrés supportant une mémoire de grande taille et procédé correspondant - Google Patents

Puce à circuits intégrés supportant une mémoire de grande taille et procédé correspondant Download PDF

Info

Publication number
WO2007105926A1
WO2007105926A1 PCT/KR2007/001295 KR2007001295W WO2007105926A1 WO 2007105926 A1 WO2007105926 A1 WO 2007105926A1 KR 2007001295 W KR2007001295 W KR 2007001295W WO 2007105926 A1 WO2007105926 A1 WO 2007105926A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
memory
chip
command
apdu
Prior art date
Application number
PCT/KR2007/001295
Other languages
English (en)
Inventor
Kyoung-Tae Kim
Jun-Chae Na
Min-Jeong Kim
Original Assignee
Ktfreetel Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020060024337A external-priority patent/KR20070094108A/ko
Priority claimed from KR1020060026954A external-priority patent/KR100738032B1/ko
Application filed by Ktfreetel Co., Ltd. filed Critical Ktfreetel Co., Ltd.
Priority to JP2009500298A priority Critical patent/JP5022434B2/ja
Priority to CN2007800090222A priority patent/CN101401113B/zh
Publication of WO2007105926A1 publication Critical patent/WO2007105926A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/0772—Physical layout of the record carrier
    • G06K19/07732—Physical layout of the record carrier the record carrier having a housing or construction similar to well-known portable memory devices, such as SD cards, USB or memory sticks

Definitions

  • the present invention is related to an IC chip, more specifically to an IC chip
  • the conventional IC chip as illustrated in FIG. 1, includes an IC chip memory.
  • IC chip memory can include a ROM memory for storing a code, a RAM memory for
  • FIG. 1 is physically realized in one chip, and the IC chip and the large
  • a mobile communication terminal such as a global system for a mobile
  • GSM Global System for Mobile communications
  • W-CDMA wide code division multi access
  • SIM subscriber identity module
  • universal SIM subscriber identity module
  • USIM subscriber identity module
  • This IC chip includes a co-processor encoding security data, such as mobile
  • the conventional IC chip is unable to store a lot of
  • the terminal employs mainly the flash memories to store a variety of information.
  • the flash memory is large enough to store a lot of data as compared with the IC chip
  • the flash memory has a very quick speed of technology development for
  • the flash memory has the weak security of the
  • the flash memory also is not able to guarantee the compatibility of
  • the IC chip has good security but limited storage capacity
  • flash memory has large storage capacity but weak security of data. Also, the security
  • the present invention which is contrived to solve the aforementioned problems,
  • chip can have a high speed communication with a host 400.
  • the present invention provides a large capacity memory supporting IC chip
  • An aspect of the present invention features an IC chip supporting a large capacity
  • an IC chip memory can be any type of memory. According to an embodiment of the present invention, an IC chip memory can be any type of memory. According to an embodiment of the present invention, an IC chip memory can be any type of memory.
  • a command line transferring a command
  • a data line transferring a data token
  • a memory storing data
  • a processor exchanging data with the memory according to a
  • connection state a bus controller, outputting a command for requesting to set a
  • connection state of the memory to the command line by the control of the processor
  • an IC chip can include
  • first storing unit storing a security algorithm encoding and decoding the inputted or
  • Another aspect of the present invention features a mobile communication terminal
  • terminal encodes and stores data by using an IC chip and decodes and uses decoded data
  • the IC chip being able to include an input and output port, electrically connected to the mobile communication terminal; a first storing unit, storing a security algorithm
  • a processor receiving a data encoding request signal
  • Another aspect of the present invention features a method for changing a connection
  • connection state can include receiving a command through the command line in a
  • a data line and is connected to the memory and the processor; allowing the processor to
  • Another aspect of the present invention features a security method of data used in a
  • a mobile communication terminal used in a mobile communication terminal can include a first step, receiving a data encoding request signal from the mobile communication terminal; a second step,
  • FIG. 1 is a block diagram illustrating the conventional IC chip
  • FIG. 2 is an example briefly illustrating the present invention
  • FIG. 3 is a block diagram illustrating an IC chip in accordance to an embodiment of
  • FIG. 4 illustrates an operation of an APDU command in accordance with an
  • FIG. 5 illustrates an operation of a connection command in accordance with an
  • FIG. 6 illustrates an operation of an IC chip using an APDU command and a
  • connection command in accordance with an embodiment of the present invention
  • FIG. 7 illustrates an operation of an IC chip that transmits an R-APDU having a data
  • FIG. 8 illustrates an operation of an IC chip that transmits an R-APDU having a data
  • FIG. 9 illustrates the performance of a data security algorithm in accordance with an
  • FIG. 10 is a flow chart illustrating the operation of encoding data by a data security
  • FIG. 11 is a flow chart illustrating the operation of decoding data by a data security
  • FIG. 12 is a block diagram illustrating the data capable of being stored in the
  • FIG. 2 is an example briefly illustrating the present invention.
  • present invention performs a low speed communication with the terminal in accordance
  • the IC chip can additionally include a large capacity
  • memory such as a flash memory and perform a high speed communication with an
  • the IC chip can be any one of an IC chip for
  • identifying a mobile communication subscriber such as a subscriber identity module
  • SIM subscriber identity module
  • USIM universal subscriber identity module
  • UIM user identity module
  • R-UIM removable user identity module
  • the IC chip can also perform not only the high speed
  • the IC card can be any type of communication but also the low speed communication.
  • the IC card can be any type of communication but also the low speed communication.
  • the IC card can be any type of communication but also the low speed communication.
  • the IC card can be any type of communication but also the low speed communication.
  • the IC card can be any type of communication but also the low speed communication.
  • the IC card can be any type of communication but also the low speed communication.
  • the IC card can be any type of communication but also the low speed communication.
  • MMC multimedia card
  • a host 400 and the IC chip communicate with each other
  • CMD command line
  • DATA data line
  • the host 400 and the memory card controller 100, illustrated in FIG. 2, are identical to The host 400 and the memory card controller 100, illustrated in FIG. 2, are identical to The host 400 and the memory card controller 100, illustrated in FIG. 2, are identical to The host 400 and the memory card controller 100, illustrated in FIG. 2, are identical to The host 400 and the memory card controller 100, illustrated in FIG. 2, are identical to The host 400 and the memory card controller 100, illustrated in FIG. 2, are identical to The host 400 and the memory card controller 100, illustrated in FIG. 2, are identical to the host 400 and the memory card controller 100, illustrated in FIG. 2, illustrated in FIG. 2, are identical to the host 400 and the memory card controller 100, illustrated in FIG. 2, are identical to the host 400 and the memory card controller 100, illustrated in FIG. 2, are identical
  • the memory card controller 100 allows
  • an IC chip processor 200 to be connected to the host 400 or a memory 300 by changing
  • the memory card controller 100 maintains the connection state that the
  • memory card controller 100 can directly access the memory 300.
  • the memory card controller 100 can directly access the memory 300.
  • memory 300 is transmitted to the host 300 through the data line.
  • connection state inside of the memory card controller 100 must be changed in
  • the memory card controller 100 can write data
  • the second switch is turned on, and the first switch and the third switch are turned off,
  • the data line is connected to the IC chip processor 200.
  • connection state of the memory card controller 100 is changed by a command
  • the command is classified into three types as Table
  • NON APDU non application protocol data unit
  • response transmitted from the memory card controller to the host 400 includes a basic
  • the memory card controller 100 stores a data token, received through the data line, in the memory or transmits the data
  • An APDU command which is a command generated in the host 400 and transmitted
  • the APDU command is generated. At least one data token is transferred from
  • the data token transmitted by the APDU through the data line includes a command
  • C-APDU C-APDU
  • R-APDU response APDU
  • the C-APDU or the R-APDU having 48 bits or less, can be transferred through one
  • the C-APDU or the R-APDU having 48 bits or more, can be transferred
  • the memory card controller 100 transmits
  • the second switch to be turned on and the first and second switches to be turned off.
  • the data token must be decapsulated to the C-APDU through a decapsulation operation to transmit it to the IC chip processor 200.
  • the R-APDU can be encapsulated
  • a connection command which is a command generated in the IC chip processor
  • the memory card controller 100 allows the third
  • chip processor 200 can write data in the memory 300 and read the data written in the
  • a disconnection command which is a command generated in the IC chip processor
  • controller 100 returns to the connection state before the connection command is
  • the memory card In another embodiment, the memory card
  • controller 100 can return to the connection state before the connection command is
  • the memory card controller 100 can be designed
  • controller supporting the high speed protocol e.g. memory card controller 100
  • APDU the feature of the present invention, to the IC chip processor.
  • the IC chip processor 200 can store encoded data in the memory 300 by driving a
  • the IC chip processor 200 can include a co processor
  • the IC chip processor 200 performs the following steps:
  • FIG. 3 is a block diagram illustrating the IC chip in accordance to an embodiment of
  • Both the memory card controller 100 and the IC chip processor 200 are included in
  • the memory 300 can be included in
  • the memory 300 is not included in the IC chip.
  • the host 400 communicating data with the memory card controller 100 by the high
  • the terminal can be not only a mobile communication terminal such as a mobile
  • processing device such as a PDA and a laptop computer.
  • the IC chip can include
  • the memory 300 storing large capacity data
  • the memory card controller 100 relaying
  • the IC chip processor communicating with the IC chip host through
  • the memory card controller 100 which relays the communications between the
  • driver 110 a card interface controller 120, a switch 130, a register 140, a memory core
  • the interface driver 110 communicates a data token and a command with the host
  • a data line and a command line located in a side part of the IC chip, through a data line and a command line.
  • the command line is encapsulated to a data token and a command, respectively, to be
  • controller 120 is also decapsulated to the electrical signal of the physical level and
  • the card interface controller 120 performs an operation depending on a type of the
  • the card interface controller 120 in case it is necessary to change the connection state according to the command type, the card interface controller 120
  • the card interface controller 120 performs
  • card interface controller 120 can access the memory 300 by controlling the card interface controller 120
  • the memory 300 can classified into a memory card section, capable of being
  • the card interface controller 120 accesses by the NON APDU command is restricted to
  • the memory 300 can classified into a security memory section, storing security
  • system memory section storing information for managing a memory area. This will be
  • the card interface controller 120 controls the
  • the data token which will be received through the data line after the APDU
  • the card interface controller 120 removes a header and a tail from the data token
  • the outputted content is the C-APDU and is
  • the card In case that one C-APDU is transmitted through a plurality of data tokens, the card
  • interface controller 120 successively combines corresponding contents. If the
  • the card interface controller 120 can transfer the
  • C-APDU includes a command and is unable to be encapsulated to one token.
  • the C-APDU received through the data line is transferred to the IC chip
  • the IC processor 200 which has received the C-APDU, performs a corresponding operation.
  • the IC chip processor 200 transfers the
  • the card interface which has the R-APDU, transfers an APDU response to the host 400 through the command line.
  • the R-APDU does not include response data
  • the R-APDU can be included in the APDU response and transferred.
  • the R-APDU can be included in the APDU response and transferred.
  • the R-APDU includes the response data, a response data identifier, indicating that
  • the host 400 which is the response data, can be included in the APDU response.
  • the host 400 which is the response data, can be included in the APDU response.
  • controller 100 through a data reading command.
  • the card interface controller 120 can change
  • connection state of the switch 130 to receive a next command.
  • connection state of the switch 130 is changed in
  • the current connection state of the switch 130 can be maintained until the next
  • the switch 130 can change the current connection state to
  • connection state of the switch 130 returns to the connection state between the card
  • connection state of the switch 130 can return to the
  • connection state of the switch 130 in the case of setting the connection state according to the NON APDU command as the basic connection state, the connection state of the switch 130
  • the card interface controller 120 In case that the connection command is received, the card interface controller 120
  • connection command is generated by the bus controller 210 by the control
  • the generated connection command is transferred
  • the card interface controller 120 changes the connection state of the switch 130
  • the IC chip processor 200 can be connected to the memory 300.
  • processor 200 accesses a specific address of the memory 300, connected through the
  • switch 130 reads stored data or writes data.
  • the card interface controller 120 changes the connection state of the switch 130 by
  • the disconnection command to receive an R-APDU from the IC chip processor or to perform the processing by a next command.
  • interface controller 120 receives the R-APDU from the IC chip processor by controlling
  • the card interface controller 120 maintains the current
  • connection state or changes the current connection state to a predetermined connection
  • the data security can be embodied through the security
  • the host 400 or the memory card controller 100 can generate the
  • the special area of the memory 300 can be the memory card section that can
  • the IC processor which has received the C-APDU for performing the data security
  • processing outputs a connection command for accessing the pertinent area through the
  • bus controller 210 requests to change the connection state. Then, the IC chip
  • processor 200 can perform the data security processing of the special area. This will be described
  • a predetermined time e.g. one cycle
  • card interface controller 120 disconnects the connection between the IC chip process
  • the card interface controller 120 monitors the data
  • the switch 130 is controlled to allow the connection stat to
  • the switch 130 is connected to the card interface controller 120, the IC chip
  • the switch 130 makes it possible to
  • the switch 130 can be realized by use of various methods. Any person of ordinary
  • the method of changing the connection state of the switch 130 refers to FIG. 2 and Table 1.
  • the register 140 which consists of a mandatory register and an optional register
  • the register 140 includes a card identification number (CID) of 128 bits to be stored for
  • CSD card operation data
  • OCR operation condition register
  • the register 140 can further include a driver
  • stage register DSR of 16 bits selectively forming an output driver of the card.
  • the memory core interface 150 accesses a special address of the memory, requested
  • the card interface controller 120 or the IC chip processor 200 reads and writes
  • the power sensing unit 160 If the IC chip is inserted into a socket of the terminal, the power sensing unit 160
  • the IC chip processor 200 performs a basic operation of the IC chip, whereas a
  • module e.g. a code and an applet
  • data necessary to perform the basic operation
  • the IC chip processor 200 determines whether it is necessary to access the memory
  • the IC chip section of the memory 300 which is set such that the IC chip
  • process 200 can excessively access the IC chip section, stores the module and data.
  • the IC chip section is applied with the address system of the memory
  • the memory 300 can be freely
  • the IC chip processor 200 forms the operation result as the
  • R-APDU to transfer the R-APDU to the card interface controller 120.
  • the IC chip processor 200 does not
  • the IC chip processor 200 can acquire memory resources necessary to
  • the IC chip processor 200 can temporally store the instructions
  • the bus controller 210 which is coupled between the IC chip processor 200 and the
  • the memory 300 can be not only a solid memory device such as a flash memory
  • the memory 300 can divided into a memory card section and an IC chip section. Each of the sections can be exclusively used by the memory card controller 100 and the
  • the memory card section can store data transmitted from the host 400, and the IC
  • chip section can store a module necessary to perform the basic operation of the IC chip
  • the memory 300 can be also divided into a security memory section, storing
  • FIG. 4 is an example illustrating an operation of an APDU command in accordance
  • a C-APDU generated by the IC chip host consists of a header of 4 bytes and a body
  • the header consists of a class of instruction (CLA) of 1 byte, an
  • INS instruction code
  • Pl parameter 1
  • P2 parameter 2
  • the body consists of Lc of 1 byte, measuring an optional body or the length of
  • the data field including a command parameter of variable length or data
  • the IC chip processor 200 consists of a body of variable length and state words SWl and SW2.
  • the body consists of Le, measuring an optional body or the length of data
  • the host 400 couples an LB header measuring the length of the C-APDU to the
  • the plurality of encapsulated data tokens are transferred to the memory card
  • controller 100 through a physical layer formed between the host 400, supporting a high
  • card interface controller 120 decapsulates the plurality of received data tokens to the
  • command token are communicated through a command line and a data line,
  • a data reading/writing command (from the host 400 to the IC chip) and
  • reading/writing command is classified into a sequential command and a block-oriented
  • the sequential command transmits a successive data stream
  • the block-oriented command transmits a successive block (token)
  • CRC cyclic redundancy checking
  • the data is transmitted between the host 400 and the IC chip.
  • the command token has the overall length of 48 bits. A start bit and an end bit are
  • a transmitter bit next to the start bit, having 1, is a bit
  • a command content is next to the
  • a response token has the overall length of 48 bits or 136 bits.
  • a transmitter bit next to the start bit, having 0, is a
  • a response content is next to the
  • a start bit and an end bit are always 0 and 1
  • the APDU field includes a C-APDU or an R-APDU from the host 400 or the IC chip.
  • the APDU exceeding 510 bytes is divided into at least 2 block-oriented data tokens and
  • the APDU communication includes the following four cases.
  • the C-APDU can be any data field value of the C-APDU. In case that there is no data field value of the C-APDU, the C-APDU can be any data field value of the C-APDU.
  • an APDU command 410 included in an APDU command 410 or an APDU token 420 (first case and second case).
  • the C-APDU is included in the
  • the APDU token including the C-APDU is transmitted between
  • connection from the connection, between the memory card controller and the memory, 415 to the connection, between the memory card controller and the IC chip processor, 425.
  • the R-APDU is small enough in size, the R-APDU is included in the APDU response
  • the IC chip processor 200 transfers to the memory card controller 100 the
  • R-APDU itself, the memory address stored with the R-APDU or information indicating
  • the memory card controller 100 which has
  • the R-APDU reading identifier which is
  • the R-APDU reading identifier can be the memory address stored with the R-APDU or
  • the host 400 which has received
  • the APDU response 430 having the R-APDU reading identifier reads the R-APDU
  • the memory card controller 100 changes the connection
  • FIG. 4 illustrates that the memory card controller 100 changes the connection state
  • FIG. 5 is an example illustrating an operation of a connection command in
  • the IC chip processor 200 determines whether it is necessary to access
  • the memory 300 based on the C-APDU type and whether the C-APDU includes data.
  • connection command 500 is outputted to a data line through the bus controller 210.
  • the memory card controller 100 which has received the connection command 500
  • the IC chip processor 200 accesses a pre-allotted IC chip section of the
  • a disconnection command 520 is optionally provided. If
  • FIG. 5 illustrates that the memory card controller 100 changes the
  • connection state to the connection between the memory card controller and the memory.
  • FIG. 6 is an example illustrating an operation of an IC chip using an APDU
  • the host 400 which has received a C-APDU from the IC chip host, transmits the
  • the C-APDU is encapsulated to an APDU token and transmitted to the memory card
  • the memory card controller 100 is connected to a memory 300 (605).
  • controller 100 which has received the APDU command 600, changes the connection state such that the connection, between the memory card controller and the IC chip
  • processor, 615 can be performed. Then, if the APDU token 610 is received through a
  • the memory card controller 100 decapsulates the APDU token 610 to the
  • processor 200 which has received the C-APDU, determines whether it is necessary to
  • a connection command 620 is
  • the memory card controller 100 which has received the
  • connection command 620 changes the connection state to the connection, between the
  • the memory card processor 100 converts the R-APDU into an APDU
  • connection state of the memory card controller 100 is
  • FIG. 7 and FIG. 8 are examples illustrating operations of an IC chip that transmits
  • connection command in accordance with some embodiments of the present invention.
  • the memory card controller 100 receives an R-APDU or the corresponding
  • card controller 100 converts the R-APDU or the corresponding response to an APDU
  • controller 100 inserts an R-APDU reading identifier into the APDU response 730 and
  • connection state of the memory card controller 100 is maintained as
  • the host 400 which has received the APDU response 730 having the R-APDU
  • reading identifier reads the R-APDU from the IC chip through a reading command 740.
  • the memory card controller 100 which has received the reading command 740,
  • the R-APDU is encapsulated to a
  • the host 400 transmits a stop command 770 to the memory card controller
  • the memory card controller 100 transmits a stop response in response to the stop
  • command 840 which is a reading command, reads data from the IC chip processor 200.
  • the memory card controller 100 changes the connection state to the
  • IC chip processor 200 transmits the R-APDU, which is temporarily being stored due to
  • the memory card controller 100 controls the change of the connection state, to the memory card controller 100.
  • controller 100 encapsulates the R-APDU to a data token 850 to transmit the data token
  • FIG. 9 illustrates the performance of a security algorithm in accordance with an
  • the IC chip can include a data input and output port 910, the IC chip processor 200
  • the data input and output port 910 is the port for receiving or sending the data
  • the data input and output port is inputted outside of the terminal from or to the IC chip.
  • output port 910 can input and output data in various forms of the ISO 7816, RF, MMC,
  • the IC chip processor 200 exchanges data with the memory 300
  • the data is changed to security data, encoded by driving a
  • the IC chip processor 200 stores the encoded security data in the
  • a security processing operation refers to the operation, where data is changed to the
  • security data is changed to typical decoded data by the same security algorithm and is
  • the data is stored in the user memory
  • the data is transferred to the host 400 without undergoing the
  • This operation refers to a typical processing operation.
  • the security algorithm can employ an algorithm which is
  • the security algorithm can
  • the security algorithm is not executed for all data inputted and outputted through the data line.
  • the security algorithm can be executed for the data
  • the security algorithm can be executed by the control program installed in an IC
  • control program can control whether to encode the data inputted
  • control program can be also stored in the system memory section 320.
  • the control program can ask a user of the terminal whether to encode data through a
  • GUI graphic user interface
  • control program executes the security algorithm and encodes the pertinent data.
  • control program can store the encoded data in the memory 300 and store
  • control program does
  • control program stores information indicating that the data is not encoded and the
  • the GUI can be included in the control program as one module. Alternatively, the
  • GUI can be separately embodied in various applications executed in the terminal.
  • the memory 300 can be configured as an integrated IC chip consisting of an IC chip
  • the memory 300 can be configured in a form of being
  • the memory 300 is configured in a form of the integrated IC chip, an
  • the memory 300 is configured in a form independently of the IC chip
  • the data is exchanged between the IC chip and the memory 300 by any one method of
  • IC chip form has a quicker operation speed than the independently linked form.
  • the IC chip embodied in a form of an SIM card of a GSM method or an USIM card
  • the IC chip stores security information such as personal
  • the memory 300 can be any type of the present invention.
  • the security memory section 310 storing encoded data in the memory 300 by the security algorithm driven by the IC chip processor 200, the user memory section 320,
  • the IC chip memory 300 can include a co-processor
  • the memory 300 can store security data and typical data by pre-dividing a section
  • the memory 300 is pre-divided and set per area for efficient
  • the memory 300 can employ a flash memory capable of
  • the memory 300 can be realized
  • system memory section can be typically accessed.
  • an initializing applet is loaded and driven so as to initialize the memory area.
  • the security memory section can be assigned more than the user memory section.
  • the user memory and the security memory are set in the ratio of 50
  • the memory 300 can be divided into in the system memory section.
  • the memory area can be reset by applying the memory managing
  • a part capable of being accessed by the user can be also set through the
  • each section can have its own size.
  • each of the sections can have its own size.
  • FIG. 10 is a flow chart illustrating the operation of encoding data by a data security
  • a control program receives the
  • control program is inputted with a security key from the user and authorizes the security
  • a PIN or a password can be used as a authorizing method.
  • control program executes the security algorithm by the IC chip processor 200 to
  • S 1030 is not undergone, and a step represented by S 1040 is advanced.
  • control program stores the pertinent data in the
  • step represented by S 1040 is stored in the step represented by S 1040.
  • control program displays the storing result of the
  • FIG. 11 is a flow chart illustrating the operation of decoding data by a data security
  • control program receives
  • control program authorizes a security key of the user.
  • a PIN or a password can be used
  • control program decodes the searched data with the address of the memory by executing
  • step represented by S 1040 is not performed. Meanwhile, if the authorization of the
  • control program displays the decoded data or the
  • FIG. 12 is a block diagram illustrating the data capable of being stored in the
  • the data illustrated by in FIG. 12, is divided and structured with setting information
  • the structured data can be divided into items of 'personal
  • MY UI user interface
  • PIMS personal information management system
  • the personal user interface includes information set for the user to
  • the PIMS includes information such as a 'phone number', a 'schedule
  • the finance includes information such as an 'account number', a 'password', a
  • the application includes sub-items of ' messenger', 'telemetry', 'DMB', 'office' and
  • the messenger can include information, used for messenger chatting, such as a 'my
  • the telemetry can includes information necessary to receive directions service through the terminal, such as a 'bookmark', a 'my house', a 'setting information' and a
  • the DMB can include information necessary to receive broadcasting service
  • a 'channel list' such as a 'channel list', a 'program list' and a 'setting
  • the office can include information for accessing office groupware through the
  • a 'virtual private network' such as a 'virtual private network' and a 'setting information'.
  • the ID can include some information such as a 'key value' of the door of user's
  • the user of the terminal can more simply encode and store setting
  • previous information can be used as it is by putting the IC
  • the mobile communication terminal is missed or stolen, there is no risk that the personal information drains away.
  • the communication can be more quickly performed

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Storage Device Security (AREA)

Abstract

L'invention concerne une puce à circuits intégrés, notamment une puce à circuits intégrés supportant une mémoire de grande taille. Dans un mode de réalisation, l'invention concerne une puce à circuits intégrés comportant une ligne de commande transmettant une commande; une ligne de données transmettant un jeton de données; une mémoire stockant des données; un processeur échangeant des données avec la mémoire selon un état de connexion; un contrôleur de bus émettant une commande pour demander le réglage d'un état de connexion entre la ligne de commande et la mémoire, vers la ligne de commande, par la commande du processeur; et un contrôleur de carte mémoire changeant chaque connexion entre la ligne de données, la mémoire et le processeur selon la commande reçue par la ligne de commande.
PCT/KR2007/001295 2006-03-16 2007-03-16 Puce à circuits intégrés supportant une mémoire de grande taille et procédé correspondant WO2007105926A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009500298A JP5022434B2 (ja) 2006-03-16 2007-03-16 大容量メモリを支援するｉｃチップ及び支援方法
CN2007800090222A CN101401113B (zh) 2006-03-16 2007-03-16 支持大尺寸存储器的ic芯片及其方法

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2006-0024337 2006-03-16
KR1020060024337A KR20070094108A (ko) 2006-03-16 2006-03-16 데이터 보안 장치 및 이를 포함하는 이동 통신 단말기
KR1020060026954A KR100738032B1 (ko) 2006-03-24 2006-03-24 대용량 메모리 지원 스마트 카드 및 지원 방법
KR10-2006-0026954 2006-03-24

Publications (1)

Publication Number Publication Date
WO2007105926A1 true WO2007105926A1 (fr) 2007-09-20

Family

ID=38509707

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2007/001295 WO2007105926A1 (fr) 2006-03-16 2007-03-16 Puce à circuits intégrés supportant une mémoire de grande taille et procédé correspondant

Country Status (2)

Country Link
JP (1) JP5022434B2 (fr)
WO (1) WO2007105926A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8613087B2 (en) 2010-12-06 2013-12-17 Samsung Electronics Co., Ltd. Computing system
KR20190075363A (ko) 2017-12-21 2019-07-01 삼성전자주식회사 반도체 메모리 장치, 이를 포함하는 메모리 시스템 및 메모리 모듈

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001195553A (ja) * 2000-01-05 2001-07-19 Toshiba Corp 無線インタフェース機能内蔵ｉｃカード、アンテナモジュール、情報処理装置
JP2003016418A (ja) * 2001-06-27 2003-01-17 Sony Corp 携帯端末及びその制御方法、並びに、ｉｃカード
KR20040085793A (ko) * 2003-04-01 2004-10-08 이상은 응용프로그램 내장형 스마트 이동저장장치
KR20050003960A (ko) * 2003-07-04 2005-01-12 삼성전자주식회사 다중 호스트 인터페이스를 지원하는 스마트 카드 겸용이동형 저장 장치 및 이에 대한 인터페이스 방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6385955A (ja) * 1986-09-30 1988-04-16 Toshiba Corp ダイレクトメモリアクセス転送制御装置
JPH0749817A (ja) * 1993-08-06 1995-02-21 Hitachi Ltd Ｄｍａ転送制御装置
JP2000251035A (ja) * 1999-02-26 2000-09-14 Hitachi Ltd メモリカード
JP4185680B2 (ja) * 2001-07-09 2008-11-26 株式会社ルネサステクノロジ 記憶装置
JP2004104539A (ja) * 2002-09-11 2004-04-02 Renesas Technology Corp メモリカード
JP2004334471A (ja) * 2003-05-07 2004-11-25 Matsushita Electric Ind Co Ltd 情報カード
US7823209B2 (en) * 2003-11-06 2010-10-26 Panasonic Corporation Information recording medium, information recording medium accessing device, and area setting method
TW200604810A (en) * 2004-02-20 2006-02-01 Renesas Tech Corp Nonvolatile memory and data processing system
WO2005122070A1 (fr) * 2004-06-09 2005-12-22 Renesas Technology Corp. Module de carte ci

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001195553A (ja) * 2000-01-05 2001-07-19 Toshiba Corp 無線インタフェース機能内蔵ｉｃカード、アンテナモジュール、情報処理装置
JP2003016418A (ja) * 2001-06-27 2003-01-17 Sony Corp 携帯端末及びその制御方法、並びに、ｉｃカード
KR20040085793A (ko) * 2003-04-01 2004-10-08 이상은 응용프로그램 내장형 스마트 이동저장장치
KR20050003960A (ko) * 2003-07-04 2005-01-12 삼성전자주식회사 다중 호스트 인터페이스를 지원하는 스마트 카드 겸용이동형 저장 장치 및 이에 대한 인터페이스 방법

Also Published As

Publication number Publication date
JP2009529745A (ja) 2009-08-20
JP5022434B2 (ja) 2012-09-12

Similar Documents

Publication Publication Date Title
US7614566B2 (en) Smart cards and smart card systems supporting multiple interfaces
US9741027B2 (en) Memory card based contactless devices
US7641121B2 (en) Multi-protocol memory card
TWI435214B (zh) 用於記憶卡的隱藏命令協定之方法及物件
CN101689160B (zh) 具有用户识别模块功能的存储接口卡
US7815110B2 (en) Methods for controlling access to data stored in smart cards and related devices
WO2007094624A1 (fr) Carte à circuit intégré, terminal à carte à circuit intégré et procédé d'initialisation associé
US20080183942A1 (en) Sharing Memory Interface
SG179374A1 (en) Ic card, mobile electronic device and data processing method in ic card
CN101401113B (zh) 支持大尺寸存储器的ic芯片及其方法
JP2018152130A (ja) 通信デバイス及び通信システム
JP3863011B2 (ja) コンビネーション型ｉｃカード、及びその制御方法、並びにそのシステムプログラム
US20080075102A1 (en) Interface
JP2006236200A (ja) カード状記憶装置とそのホスト装置
KR101318594B1 (ko) 결합형 ｓｉｍ 및 대용량 저장 카드의 데이터 액세스를위한 방법 및 디바이스
WO2007105926A1 (fr) Puce à circuits intégrés supportant une mémoire de grande taille et procédé correspondant
KR200329847Y1 (ko) 스마트카드리드기 겸용 유에스비 드라이브 장치
KR100738032B1 (ko) 대용량 메모리 지원 스마트 카드 및 지원 방법
WO2006004966A2 (fr) Controleur ethernet a exces de memoire flash de bord servant d'interface avec un microcontroleur
US20100330911A1 (en) Telecommunication intelligent card and method for signaling interaction with external non-contact card
CN112613872A (zh) 作为协议接口的类型4nfc标记
KR200218544Y1 (ko) 보조 메모리수단을 내장하는 이동단말기용 어댑터
JP2005293362A (ja) データキャリア及びデータキャリアのプログラム
JP7444197B2 (ja) 電子情報記憶媒体、暗号演算方式選択方法、及びプログラム
CN106650352A (zh) 一种基于otp器件的身份认证芯片

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07745583

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 200780009022.2

Country of ref document: CN

Ref document number: 2009500298

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 07745583

Country of ref document: EP

Kind code of ref document: A1