WO2007105255A1

WO2007105255A1 - Decoder circuit

Info

Publication number: WO2007105255A1
Application number: PCT/JP2006/303435
Authority: WO
Inventors: Kenji Ijitsu
Original assignee: Fujitsu Limited
Priority date: 2006-02-24
Filing date: 2006-02-24
Publication date: 2007-09-20

Abstract

A decoder circuit wherein a high-speed, definite output can be achieved without increasing the entire size of a decoder body part, which comprises a plurality of decoder essential circuits, and also without increasing the size of a circuit, which drives the decoder body part, itself. The definite output operation and the cancellation output operation are separated from each other. During the cancellation output operation, a reset-dedicated PMOS transistor (13) is used to drive an inverter (9) in the last stage for performing a cancellation output. The waveform blunting of the cancellation output can be improved. During the definite output operation, an inverter (8), which drives the inverter (9) in the last stage, increases the size of an NMOS transistor, which contributes to the definite output, while, contrarily, reducing the size of a PMOS transistor that contributes to the cancellation output. The waveform blunting of the definite output is improved without changing the capability of an inverter (7) in the preceding stage, that is, without increasing the load for the decoder input, whereby the high-speed, definite output can be achieved.

Description

Specification

Decoder circuit

Technical field

[oooi] The present invention relates to a decoder circuit for obtaining a specific output (selected Z non-selected) from a plurality of inputs, and more particularly to a decoder circuit incorporated as a circuit module in a semiconductor integrated circuit device.

Background art

As a decoder circuit incorporated in a semiconductor integrated circuit device such as a semiconductor integrated memory device, for example, a plurality of decoder main circuits having a dynamic NAND configuration as shown in FIG. 4 are arranged in parallel. Things are known. Hereinafter, in order to facilitate understanding of the present invention, a conventional decoder circuit will be briefly described with reference to FIG.

FIG. 4 is a circuit diagram showing a configuration example of a main part of a conventional decoder circuit. Figure 4 shows an example of a circuit using a 3-input dynamic NAND. In the decoder main circuit 40 shown in FIG. 4, the reset pulse signal rst and the three selection pulse signals adO, adl, ad2 are input, and one decoded output indicating selection Z non-selection is obtained at the output terminal out. Can do. The main part of the 3-input Y-output decoder circuit has a configuration in which Y pieces of the decoder main circuit 40 shown in FIG. 4 are arranged in parallel.

That is, the decoder main circuit 40 shown in FIG. 4 includes, as an input processing circuit, a PMOS transistor 42 having a source electrode connected to a power supply 41, a drain electrode of the PMOS transistor 42, and a ground potential (ground). And NMOS transistors 43, 44, 4 5 arranged in series.

The negative reset pulse signal rst is applied to the gate electrode of the PMOS transistor 42 in the reset cycle. The three positive selection pulse signals adO, adl, and ad2 are applied to the corresponding gate electrodes of the NMOS transistors 43, 44, and 45 in the selection cycle.

[0006] The decoder main circuit 40 shown in FIG. 4 includes, as an output processing circuit, a connection terminal N and an output terminal ou between the drain electrode of the PMOS transistor 42 and the drain electrode of the NMOS transistor 43. An odd number of inverters (three inverters 46, 47 and 48 in the illustrated example) arranged in series with t and an inverter 49 connected in reverse parallel to the inverter 46 are provided. Inverters 46, 47, and 48 function as buffers. The inverter 49 functions as a keeper circuit.

FIG. 5 is a circuit diagram showing a specific configuration of the inverter shown in FIG. As shown in FIG. 5, each of the inverters 46 to 49 shown in FIG. 4 includes a PMOS transistor 52 whose source electrode is connected to the power source 51 and an NMOS transistor 53 whose source electrode is connected to the ground potential (ground). This is a CMOS inverter composed of The gate electrodes of the PMOS transistor 52 and the NMOS transistor 53 are connected in common to form an input end, and the drain electrodes are connected in common to form an output end. The capability of each of the PMOS transistor 52 and the NMOS transistor 53 is defined by the ratio (WZL) of the gate width W and the gate length L representing the size.

According to the configuration shown in FIG. 5, when the input signal a is at a high level (hereinafter referred to as “H level”), the PMOS transistor 52 performs an off operation and the NMOS transistor 53 performs an on operation. Since the output terminal is pulled to the ground potential (ground), the output signal X becomes low level (hereinafter referred to as “L level”). When the input signal a is at the L level, the NMOS transistor 53 performs the off operation, and the PMOS transistor 52 performs the on operation to draw the output terminal to the power supply potential, so that the output signal X becomes the H level.

In the above configuration, in the decoder main circuit 40 shown in FIG. 4, the reset pulse signal rst and the selection pulse signals adO, adl, ad2 are alternately input. In the selection cycle in which the reset pulse signal rst is not input and the signal line is in the H level state and the PMOS transistor 42 is in the OFF operation state, all of the input selection pulse signals adO, adl, and ad2 are positive. All of the NMOS transistors 43, 44, and 45 are turned on during the period of the pulse width of the selection pulse signals adO, a dl, and ad2, and the connection terminal N is pulled to the ground potential (ground) and becomes the L level. . Then, the output of the inverter 46 is maintained at the H level by the holding operation by the inverter 49. As a result, the output of the inverter 48 becomes the H level, and the output terminal out becomes the H level, that is, the selected “determined state”.

[0010] In the subsequent reset cycle, the reset pulse signal rst is input and the PMOS transistor When the star 42 is turned on during the pulse width of the reset pulse signal rst, the connection terminal N is pulled to the power supply potential and becomes H level. Then, the output of the inverter 46 is maintained at the L level by the holding operation by the inverter 49. As a result, the output of the inverter 48 becomes the L level, and the output end out force level, that is, the “released state”.

On the other hand, in the selection cycle in which the reset pulse signal rst is not input and the signal line is in the H level state and the PMOS transistor 42 is in the OFF operation state, the input selection signals adO, adl, If all or part of ad2 is negative, all or part of the NMOS transistors 43, 44, 45 are turned off. In this case, the output of the inverter 46 is maintained at the L level operated in the immediately preceding reset cycle by the holding operation by the inverter 49. As a result, the output power level of the inverter 48 is reached, and the output terminal out is at the L level, that is, the non-selected “determined state”.

Patent Document 1: Japanese Patent Laid-Open No. 62-239398 (semiconductor memory)

Disclosure of the invention

Problems to be solved by the invention

[0013] By the way, in this type of decoder circuit, in order to achieve high-speed deterministic output, that is, in the example of the decoder main circuit 40 described above, the final-stage inverter 48 sets the output level to the L level force H. When increasing the speed to rise to the level, the inverter 47 drives the inverter 48 in the final stage in both the deterministic output and the release output, so conventionally, if the drive capacity of the inverter 47 is increased and it is still insufficient It is necessary to increase the drive capacity of each inverter that constitutes the output processing circuit, such as increasing the drive capacity of the inverter 46 in the previous stage. Furthermore, it is necessary to increase the driving capability of the NMOS transistors arranged in series in the input processing circuit. These can be dealt with by increasing the size (mainly gate width W) of each MOS transistor. As a result, it may be necessary to increase the capacity of a circuit that drives a plurality of decoder essential circuits arranged in parallel.

In other words, in the conventional decoder circuit in which the decoder main part circuits having the dynamic NAND configuration as shown in FIG. The size of the entire decoder main unit or the size of the circuit itself that drives the decoder main unit increases, which hinders the high integration of the integrated circuit device. Will occur.

In the CMOS inverter shown in FIG. 5, normally, the driving capability of the PMOS transistor 51 is less than about half that of the NMOS transistor 52. To increase the driving capability of the inverter, the PMOS transistor 51 and the NMOS transistor Since it is necessary to increase the size while maintaining the ratio of the drain current coefficient of 52 (so-called PN ratio), it becomes very complicated.

As an example of manipulating the driving capability of a CMOS inverter, for example, in Patent Document 1 described above, when generating a chip selection signal power internal circuit control signal and an output transistor control signal in a semiconductor memory, the chip Two CMOS inverters (CMOS inverter 1 generating internal circuit control signal and CMOS inverter 2 generating output transistor control signal) are arranged in parallel at the output stage of the CMOS inverter to which the selection signal is input. In the CMOS inverter 2, the size ratio of the PMOS transistor and the NMOS transistor is set to 1:10 so that the internal circuit control signal is activated quickly when the chip selection signal is activated (for example, 0 V). Outputs when the chip selection signal is inactive (for example, 3V) with the size ratio of the transistor reversed to 10 to 1.Transistor control signal Techniques have been proposed to ensure that they become inactive quickly.

[0017] The present invention has been made in view of the above, and does not increase the size of the entire decoder main body composed of a plurality of decoder main circuits or the size of the circuit itself that drives the decoder main body. The purpose is to obtain a decoder circuit capable of achieving a high-speed deterministic output.

Means for solving the problem

[0018] In order to achieve the above-described object, the present invention provides a decoder circuit in which a plurality of decoder main circuits that perform one specific output from a plurality of inputs are provided in parallel. A first reset pulse signal is applied, and one signal electrode is connected in series to a first PMOS transistor, and the other signal electrode of the first PMOS transistor and a ground potential are arranged in series. A plurality of NMOS transistors to which a selection pulse signal is applied to each gate electrode, and a connection terminal and an output terminal of the other circuit electrode of the first PMOS transistor and a series circuit of the plurality of NMOS transistors. The second reset pulse signal is applied to the gate electrode directly or via the even number of inverters, and one signal electrode is connected to the power supply and the other signal A second PMOS transistor having an electrode connected to an input terminal of the last-stage inverter among the odd-number inverters, and the inverter that directly drives the last-stage inverter in the odd-number inverters, It consists of a small size PMOS transistor and a large size! / NMOS transistor!

According to the present invention, the deterministic output operation and its release output operation are separated, and in the release output operation, the second stage PMOS transistor drives the final-stage inverter of the odd number of inverters to release the release output. Therefore, the waveform dullness of the release output can be improved. In the definite output operation, the inverter that drives the final stage inverter increases the size of the NMOS transistor that contributes to the deterministic output, and conversely reduces the size of the PMOS transistor that contributes to the release output. Without changing the capacity of the inverter in the previous stage, that is, without increasing the load on the decoder input, the waveform dullness of the deterministic output can be improved and the deterministic output speed can be increased.

The invention's effect

[0020] According to the present invention, the size of the entire decoder main body composed of a plurality of decoder main circuits is increased without increasing the size of the circuit itself that drives the decoder main body, that is, in the semiconductor integrated circuit device. There is an effect that it is possible to achieve a fast output of a deterministic output without hindering the high integration key.

Brief Description of Drawings

FIG. 1 is a circuit diagram showing a configuration of a main circuit of a decoder circuit according to an embodiment of the present invention.

2 is a circuit diagram showing a configuration example of a decoder circuit using the main circuit shown in FIG.

FIG. 3 is a time chart for explaining the operation of the decoder circuit shown in FIG.

FIG. 4 is a circuit diagram showing a configuration of a main circuit of a conventional decoder circuit.

FIG. 5 is a circuit diagram showing a specific configuration of the inverter shown in FIG. 4. Explanation of symbols

[0022] 1 decoder main circuit

2, 14, 27, 35 Power supply

3 PMOS transistor (first PMOS transistor)

4, 5, 6, 29, 32 NMOS transistor

7, 8, 9 Inverter

10 Inverter (keeper circuit)

11, 12 Inverter

13 PMOS transistor (second PMOS transistor)

16 Pulse circuit

17, 19 NAND circuit

18 Inverter

20, 21 Inverter

25 Reset control circuit

26, 35 PMOS transistor

31, 33 Delay circuit

BEST MODE FOR CARRYING OUT THE INVENTION

[0023] Hereinafter, a preferred embodiment of a decoder circuit according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration of a main circuit of a decoder circuit according to one embodiment of the present invention. In Fig. 1, as in the conventional example (Fig. 4), a circuit example using a 3-input dynamic NAND is shown. In this embodiment, the reset pulse signal power is different from the conventional example. It consists of two pulses: a pulse signal r—a and a second reset pulse signal r—b. In addition to the “input processing circuit” and “output processing circuit” shown in the conventional example, a “reset processing circuit” Is provided.

That is, the decoder main circuit 1 shown in FIG. 1 includes, as an input processing circuit, a PMOS transistor 3 having a source electrode connected to a power supply 2, a drain electrode of the PMOS transistor 3, and a ground potential (ground). With NMOS transistors 4, 5, 6 arranged in series between ing.

The negative first reset pulse signal r—a is applied to the gate electrode of the PMOS transistor 3 in the reset cycle. The three positive selection pulse signals adO, adl, ad2 are applied to the corresponding gate electrodes of the NMOS transistors 4, 5, 6 in the selection cycle. The configuration of the above input processing circuit is the same as that of the conventional example although the reference numerals are different.

Further, the decoder main circuit 1 shown in FIG. 1 is arranged in series between the connection end N and the output end out of the drain electrode of the PMOS transistor 3 and the drain electrode of the NMOS transistor 4 as an output processing circuit. Odd number of inverters (in the example shown, three inverters 7, 8, 9) and an inverter 10 connected in reverse parallel to the inverter 7. Inverters 7, 8, and 9 each function as a buffer. The inverter 10 functions as a keeper circuit. In the configuration of the output processing circuit described above, the inverter 9 at the final stage and the inverter 8 that drives the inverter 9 have different abilities from the conventional example. The remaining inverters have different signs. The force is the same as the conventional example.

[0028] The differences are as follows. Since the object of the present invention is the fast output of the deterministic output, the capacity of the inverter 9 at the final stage may be equal to that of the conventional example. Also good. On the other hand, the inverter 8 that drives the inverter 9 in the final stage is devoted to driving the output decision, so in the CMOS inverter shown in FIG. The gate width W) is increased, and conversely, the size of the PMOS transistor 51 (mainly the gate width W) contributing to the release output is reduced to / J.

[0029] The decoder main circuit 1 shown in FIG. 1 serves as an even number of inverters (inverter in the illustrated example) that sequentially drive and transmit the second negative reset pulse signal r-b as a reset processing circuit. 11 and 12) and a PMOS transistor 13 in which the output of the final inverter 12 is applied to the gate electrode. In the PMOS transistor 13, the source electrode is connected to the power supply 14, and the drain electrode force S is connected to the output terminal of the inverter 8, and drives the inverter 9 in the final stage in cooperation with the inverter 8 in the reset cycle. And

[0030] The two reset pulse signals have the following relationship. In other words, the second reset pulse signal rb is in the generation period of the first reset pulse signal ra. It occurs with a certain time interval between the leading edge and trailing edge. In other words, both reset pulse signals are generated after the leading edge of the first reset pulse signal r—a falls and then the leading edge of the second reset pulse signal r—b falls, and the second reset pulse signal r— This occurs because the trailing edge of the first reset pulse signal r—a rises after the trailing edge of b rises.

[0031] According to this configuration, in the selection cycle, when all of the input selection pulse signals adO, ad1, ad2 are positive, all of the NMOS transistors 4, 5, 6 are selected pulse signal adO. , adl, ad2 are turned on during the pulse width, and the connection terminal N is pulled to the ground potential (ground) and becomes L level. Then, the output of the inverter 7 is maintained at the H level by the holding operation by the inverter 10.

At this time, since the size of the NMOS transistor 52 that contributes to the definite output in the CMOS inverter shown in FIG. 5 is increased in the inverter 8, when the inverter 7 in the previous stage sets the output to the H level, the output is rapidly increased. Pull to L level. As a result, the dullness of the waveform at which the inverter 9 raises the output to the H level is improved, and the time for the output terminal out to rise to the H level, that is, the time for the selection to be “determined” is shortened.

[0033] In the subsequent reset cycle, first, the first reset pulse signal r-a is input, and then the second reset pulse signal r-b is input with a small delay time. Even if the second reset pulse signal r−b disappears, the first reset pulse signal r−a does not disappear and continues for a certain period of time.

When the first reset pulse signal r—a is input, the PMOS transistor 3 is turned on, and the connection terminal N is pulled to the power supply potential and becomes the H level. This continues for the duration of the pulse width of the first reset pulse signal r−a. When the connection terminal N becomes H level, the output of the inverter 7 is maintained at the L level by the holding operation by the inverter 10, so in the inverter 8, the PMOS transistor 51 having a small capacity is turned on and the input terminal of the inverter 9 is connected to the H The inverter 9 is driven with a weak driving force at a low level. As a result, the output of the inverter 9 becomes L level, and the output end out force level, that is, the “released state”.

Next, when the second reset pulse signal r−b is input, the PMOS transistor 13 is turned on to set the input terminal of the inverter 9 to the H level, stronger than the inverter 8, and driven by the drive power. Data 9. This improves the waveform dullness of the L level release output. Since the first reset pulse signal r-a exists for a certain period even after the second reset pulse signal r-b disappears, the L level release output is maintained until the end of the reset cycle. It is.

At this time, at the timing when the PMOS transistor 13 is turned on, the NMOS transistor 52 in the inverter 8 is turned off, so that the power supply 14 → the PMOS transistor 13 → the NMOS transistor 52 in the inverter 8 → the ground potential. There will be no leak path leading to (Ground).

As described above, according to this embodiment, in the conventional example (FIG. 4), the inverter 47 that drives the inverter 48 in the final stage is involved in both the definite output and the release output thereof. Focusing on the fact that it affects the output timing and waveform dullness, separate the deterministic output operation and its cancellation output operation, and in the release output operation, the final stage inverter 9 is connected by the PMOS transistor 13 dedicated to reset. Since the release output is driven by driving, the waveform dullness of the release output can be improved.

[0038] In the definite output operation, the inverter 8 that drives the inverter 9 in the final stage is the size of the NMOS transistor 52 (mainly the gate) that contributes to the definite output in the CMOS inverter shown in FIG. Since the width (mainly gate width W) of the PMOS transistor 51 contributing to the release output is reduced by increasing the width (W), the capacity of the inverter 7 in the previous stage is not changed, that is, the decoder input (ad0 It is possible to improve the waveform dullness of the deterministic output and increase the deterministic output speed without increasing the load on ~ ad2).

Accordingly, it is possible to suppress the influence on the size of the circuit that drives the decoder main body composed of a plurality of decoder main circuits, and to prevent the high integration of the integrated circuit device in which the decoder circuit is incorporated. Therefore, it becomes possible to achieve a fast output of the deterministic output of the decoder circuit. In addition, the operation to change the size while maintaining the PN ratio can be done with only the drive inverter for the deterministic output. I can plan.

[0040] Next, referring to FIG. 2 and FIG. 3, a circuit for driving a decoder main body composed of a plurality of decoder main circuits, that is, selection pulse signals adO, adl, ad2 and first and second resets. Pal A specific example of a circuit that generates the source signals r_a and r_b will be described. FIG. 2 is a circuit diagram showing a configuration example of a decoder circuit using the main circuit shown in FIG. Figure 2 shows an example of a decoder circuit configuration that obtains 8 outputs from 3 inputs. FIG. 3 is a time chart for explaining the operation of the decoder circuit shown in FIG.

[0041] The decoder circuit shown in FIG. 2 includes eight decoder main circuit circuits 1-0 to 1-7 arranged in parallel as the decoder main unit, and 3-bit input that is externally input in the selected cycle. Reset control with three pulse generators 16a, 16b, 16c arranged in parallel corresponding to signal address [0: 2] and reset pulse signal Zwl-rst with negative external force in reset cycle Circuit 25 is provided.

[0042] The three pulsing circuits 16a, 16b, and 16c have the same configuration, and as shown in the pulsing circuit 16c, when the logical value of the 1-bit input signal address is '1', The NAND circuit 17 synchronizes with the clock elk to generate a pulse signal having the pulse width of the clock elk, and outputs a positive selection pulse signal via the inverter 20. Also, a 1-bit input signal When the logical value of address is "0", the logical value is inverted by the inverter 18 and then synchronized with the clock elk by the NAND circuit 19 to generate a pulse signal having the pulse width of the clock elk. A positive selection pulse signal is output via the inverter 21.

That is, in the pulsing circuit 16a, when the logical value of the input signal address [0] is "1", the positive selection pulse signal aO—pulse is output, and the logical value of the input signal address [0] When is 0, the positive selection pulse signal aOx—pulse is output.

[0044] In addition, when the logic value of the input signal address [l] is '1', the pulsing circuit 16b outputs the positive polarity selection pulse signal al—pulse and the logic value of the input signal address [1]. When is 0, the positive selection pulse signal alx-pulse is output.

[0045] In addition, in the pulsing circuit 16c, when the logical value of the input signal address [2] is '1', the positive polarity selection pulse signal a2—pulse is output, and the logical value of the input signal address [2] is output. When is 0, the positive selection pulse signal a2x—pulse is output.

[0046] The input terminals of the selection pulse signals adO, adl, ad2 in the eight decoder main circuits 1-0 to 1-7 correspond to the two output lines of the three pulse conversion circuits 16a, 16b, 16c, respectively. While Connected to the output line.

[0047] In the example shown in FIG. 2, selection pulse signals adO, adl, ad2 for performing deterministic output of the decoder main circuit 1-0 “select” are logical values of the 3-bit input signal address [0; 2]. When “000” is “aOx _ pulse, alx _ pulse, a2x one pulse”.

[0048] Decoder main part circuits 1-6 select pulse signal adO, adl, ad that performs definite output of "selection"

2 is “a0—pulse, al_pulse, a2x_puise” when the logical value of the 3-bit input signal address [0; 2] is “110”.

[0049] Selection pulse signal adO, adl, ad for which decoder main circuit 1-7 performs definite output of "selection"

2 is “a0-pulse, al-pulse, a2-pulse” when the logical value of the 3-bit input signal address [0; 2] is “111”.

Thus, in the eight decoder main circuit 1-0 to 1-7, one decoder main circuit circuit corresponding to the logical value of the 3-bit input signal addr ess [0; 2] By performing the “select” definite output, 8 outputs from Select [0] to Select [7] are performed.

[0051] Next, in the reset control circuit 25, the gate electrode of the PMOS transistor 26 and the gate electrode of the NMOS transistor 29 are connected to the input terminal to which the reset signal line to which the negative reset pulse signal Zwl-rst is sent is connected. And are connected.

[0052] The source electrode of the PMOS transistor 26 is connected to the power source 27, and during the period in which the negative reset pulse signal Zwl—rst is generated and the input terminal force level continues, the drain electrode is connected to the power source 27. Set the potential to H level. The drain electrode of the PMOS transistor 26 is connected to the input terminal of the inverter 28, the input terminal of the delay circuit 33, and the drain electrode of the NMOS transistor 32! RU

[0053] On the other hand, the source electrode of the NMOS transistor 29 is connected to the ground potential (ground), and when the input terminal becomes H level after the generation period of the negative reset pulse signal Zwl-rst has passed, the drain electrode is turned on. To the L level, which is the ground potential. The drain electrode of the NMOS transistor 29 is connected to the input terminal of the inverter 30, the input terminal of the delay circuit 31, and the drain electrode of the PMOS transistor 34.

[0054] Each of the delay circuits 31, 33 serves as a series circuit power of an odd number of inverters (three in the illustrated example). The output terminal of the delay circuit 33 is connected to the gate electrode of the PMOS transistor 34. P The source electrode of the MOS transistor 34 is connected to the power source 35. The output terminal of the delay circuit 31 is connected to the gate electrode of the NMOS transistor 32 !. The source electrode of the NMOS transistor 32 is connected to the ground potential (ground)!

[0055] According to this configuration, the inverter 28 outputs the negative reset pulse signal Zrst-a within a period when the PMOS transistor 26 is turned on! /, And within a predetermined period during the subsequent off operation. To do. The output terminal of the inverter 28 is connected in parallel to the input terminals of the first reset pulse signals r−a in the eight decoder main circuit 1_0 to 1-7.

Further, the inverter 30 outputs the negative reset pulse signal Zrst-b during the period in which the inverter 28 outputs the negative reset pulse signal Zrst-a. The output terminal of the inverter 30 is connected in parallel with the input terminals of the second reset pulse signals r_a in the eight decoder main circuit 1-0 to 1-7.

Next, the operation will be described with reference to FIG. In FIG. 3, when the input signal addr ess [0: 2] to the pulse circuit 16a, 16b, 16c is validated by the clock CLK generated in the selected cycle, the pulse circuit 16a, 16b, 16c to 8 One of the decoder main circuit 1—0 to 1—7! One of the valid selection pulse signals ad0 to ad2 is generated within the period of the pulse width of the clock CLK. In any one of the eight decoder main circuits 1—0 to 1—7, the output is set to H level in synchronization with the rising timing of the selection pulse signals ad0 to ad2, and the selected selection output Select [7: 0] Start and keep it until the end of the selection cycle.

[0058] Then, when the negative reset pulse signal Zwl-rst is generated in the next reset cycle and reaches the gate potential power level of the PMOS transistor 26, the inverter 28 sets the output to the L level. Starts output of negative reset pulse signal Zrst-a. In this case, the NMOS transistor 29 is in an off operation state. Then, after a predetermined delay time in the delay circuit 33, the PMOS transistor 34 is turned on and the drain electrode becomes H level. Therefore, the inverter 30 sets the output to L level and outputs the negative reset pulse signal Zrst-b. Start. The generation of these reset pulse signals Zrst-a and Zrst-b cancels the selected definite output Sele _C t [7: 0]. This release operation is performed in the same manner in all of the eight decoder main circuits 10 to 17. [0059] After that, when the negative polarity reset pulse signal Zwl-rst disappears and the gate potential of the NMOS transistor 29 becomes H level, the inverter 30 sets the output to H level and outputs the negative polarity reset pulse signal Zrst-b. Cancel and extinguish. In this case, since the PMOS transistor 26 is in a floating state in which the gate potential becomes the H level and is turned off, the input level of the inverter 28 is maintained at the immediately preceding H level. That is, the inverter 28 continuously outputs the L level. Then, after a predetermined delay time in the delay circuit 31, the NMOS transistor 32 is turned on and the input level of the inverter 28 is set to L level. Therefore, the inverter 28 sets the output to H level and the negative reset pulse signal Zrst-a Cancel the output and make it disappear.

[0060] Thus, in the reset cycle, the reset control circuit 25 does not generate the reset pulse signal Zrst-a and the reset pulse signal Zrst-b at the same timing, that is, does not set the L level and resets. Since the generation of the reset pulse signal Zrs t-a is controlled to be at the L level before the pulse signal Zrst-b is at the L level, as described above, at the timing when the PMOS transistor 13 is turned on. The NMOS transistor in the inverter 8 can be turned off and the occurrence of a leak path is suppressed.

Industrial applicability

[0061] As described above, the decoder circuit according to the present invention does not increase the size of the entire decoder main body composed of a plurality of decoder main circuits or the size of the circuit itself that drives the decoder main body. It is suitable for achieving high-speed output of a definite output without hindering the high integration of the semiconductor integrated circuit device.

Claims

The scope of the claims

[1] Multiple input powers In a decoder circuit that has multiple decoder main circuits that perform one specific output in parallel,

The decoder main circuit is:

A first PMOS transistor in which a first reset pulse signal is applied to a gate electrode and one signal electrode is connected to a power source;

A plurality of NMOS transistors arranged in series between the other signal electrode of the first PMOS transistor and a ground potential, and a selection pulse signal is applied to each gate electrode;

An odd number of inverters arranged in series between a connection end and an output end of the other signal electrode of the first PMOS transistor and the series circuit of the plurality of NMOS transistors; and a second reset pulse on the gate electrode A signal is applied directly or via an even number of inverters, one of the signal electrodes is connected to the power supply, and the other signal electrode is connected to the input terminal of the last stage of the odd number of inverters. 2 PMOS transistors,

In the odd number of inverters, the inverter that directly drives the final stage inverter is composed of a small-sized PMOS transistor and a large-sized NMOS transistor.

A decoder circuit characterized by the above.

[2] In a reset cycle for releasing the definite output of the decoder main circuit, first, the first reset pulse signal is generated, and after the predetermined time has elapsed, the second reset pulse signal is generated, and the second reset pulse signal is generated. 2. The decoder circuit according to claim 1, further comprising reset control means for extinguishing the first reset pulse signal after a lapse of a predetermined time after extinction of the two reset pulse signals.