WO2007102218A1 - Circuit reconfigurable - Google Patents

Circuit reconfigurable Download PDF

Info

Publication number
WO2007102218A1
WO2007102218A1 PCT/JP2006/304551 JP2006304551W WO2007102218A1 WO 2007102218 A1 WO2007102218 A1 WO 2007102218A1 JP 2006304551 W JP2006304551 W JP 2006304551W WO 2007102218 A1 WO2007102218 A1 WO 2007102218A1
Authority
WO
WIPO (PCT)
Prior art keywords
state
configuration
data
unit
configuration memory
Prior art date
Application number
PCT/JP2006/304551
Other languages
English (en)
Japanese (ja)
Inventor
Hisanori Fujisawa
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2006/304551 priority Critical patent/WO2007102218A1/fr
Priority to JP2008503714A priority patent/JP4410297B2/ja
Publication of WO2007102218A1 publication Critical patent/WO2007102218A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Definitions

  • the present invention relates to a technology for controlling state transition of a reconfigurable circuit.
  • each arithmetic unit element hereinafter referred to as a processing element PE
  • the connection information between the PEs are defined as configuration data on a memory, thereby performing desired processing. Is realized. It is possible to change the processing to be implemented by changing the configuration data. Therefore, by treating configuration data as one state and providing a state management unit that manages transitions between states, it is possible to implement processing while dynamically switching between multiple states.
  • FIG. 9 shows a configuration of a conventional reconfigurable circuit.
  • the reconfigurable circuit includes a state management unit 91, a plurality of processing elements 92, and a configuration memory 93.
  • the state management unit 91 manages four states.
  • the four states are: 1) A—cl, B—cl states, 2) A—c2, B—cl states, 3) A—cl, B—c2 states, 4) A—c2, B—c2 It is a state.
  • the elements corresponding to 1) to 4) are stored as configuration data in the configuration memory 93 provided in each PE92 (PE-A, PE- ⁇ ⁇ ⁇ - ⁇ , PE-F). Stored.
  • the contents stored in each configuration memory 93 are different for each ⁇ 92. In this way, large-scale data processing is executed by the ⁇ 92 that realizes processing while dynamically switching between a plurality of states.
  • Patent Documents 1 to 3 on the configuration memory As a method to reduce the number of states to be stored and effectively use the memory, multiple state management units are introduced, and each state management unit synchronizes the state management units and manages the state of the processing elements under management. A management method has been proposed.
  • Patent Document 4 discloses that in a SIMD array processor, a fixed decoder logic circuit and an LUT method are provided in a PE to locally correct selected bits of a global instruction using an LUT method. Propose to improve processing capacity.
  • Patent Document 5 uses the LUT method in an array processor that processes image data at high speed.
  • Patent Document 6 attempts to improve the efficiency of the array processor by allocating a series of externally input processing data to a large number of bits and a fractional bit and performing parallel processing for each PE.
  • Patent Documents 1 to 3 the computing element under the jurisdiction of one state management unit holds the configuration data at the memory address corresponding to the state managed by the state management unit. is doing. For this reason, there are many PEs performing the same processing when viewed in PE units even in different states. In such a case, the same function must be duplicated in different addresses, and memory is used redundantly. In addition, since configuration memory space for the number of states of the entire PE group is required, there is a problem that there is more redundant memory space than the number of states in each PE. Patent Documents 4 to 6 describe the LUT method in the PE, but are different from the present invention.
  • Patent Document 1 Japanese Patent Laid-Open No. 2001-0312481
  • Patent Document 2 Japanese Patent Laid-Open No. 2004-0133780
  • Patent Document 3 Japanese Unexamined Patent Application Publication No. 2004-0133781
  • Patent Document 4 Japanese Patent Laid-Open No. 01-0114982
  • Patent Document 5 Japanese Patent Laid-Open No. 06-0110852
  • Patent Document 6 Japanese Patent Laid-Open No. 2003-0076668
  • the present invention has been made in view of the above circumstances, and an object thereof is to provide a dynamic reconfigurable circuit using configuration memory efficiently.
  • a plurality of processing elements and configuration which are one aspect of the present invention Reconfigurable circuit that is configured
  • a state management unit that generates management information for managing the state transition of the configuration of the processing element; and the configuration information that is received from the state management unit and that corresponds to the processing element based on the management information
  • a state decoding unit that reads configuration data corresponding to the state transition state from the memory and generates state transition information for the processing element to perform state transition.
  • the state decoding unit may be provided for each processing element.
  • the state decoding unit may be provided for a plurality of the processing elements.
  • the configuration memory includes a first configuration memory that transfers configuration data to the processing element
  • It may be composed of a second configuration memory for transferring the configuration data to the first configuration memory.
  • the configuration data required from the second configuration memory is stored. Transfer and store in the first configuration memory, and transfer control signal for instructing transfer control for reading the configuration data required on the configuration memory of the processing element in the state A signal received from the management unit and instructing the transfer control is generated based on the transfer control signal, and each of the first configuration memory, the second configuration memory, and the state decoding unit is generated. Configure to notify It is good also as a structure provided with a motion load part.
  • the state management unit recognizes the state of the processing element and the configuration data of the first configuration memory corresponding to the processing element, and determines the recognition result.
  • the transfer control signal may be generated based on!
  • the state decoding unit includes a RAM that stores an address of the configuration data in the configuration memory of the processing element, and is based on the management information managed by the state management unit! The above-mentioned address generated in this way may be input to the RAM and the state transition information may be output.
  • the state decoding unit includes a look-up table circuit that holds addresses of the configuration data in the configuration memory of the processing element in a plurality of registers, and is managed by the state management unit
  • the above-described address generated based on the management information is input to the lookup table circuit, and the state transition information is generated and output by selecting the corresponding register.
  • the state management unit includes a state storage unit that stores state data indicating a state, a state determination unit that determines a next state based on the state data, and the configuration A download flag section indicating that data is being downloaded.
  • the status determination section refers to the download start flag V, which contains the necessary configuration data in the status data, and the download start flag is valid. In this case, it may be configured such that the download flag part is written as valid and the configuration loading part is instructed to execute configuration loading.
  • the status data should be interrupted with reference to the download start flag indicating when the configuration data should be downloaded and the download flag portion indicating that the download is in progress. It may be configured to include a download check flag indicating whether or not it is successful and indicating execution.
  • Each processing element is provided with a state decoding unit.
  • the state decoding unit receives the state of the entire PE group from the state management unit, analyzes the state of its own PE, and outputs the state of the PE. Based on the output PE status, the configuration data corresponding to the status is loaded from the configuration memory and mounted on the functional circuit.
  • the memory can be used efficiently without duplicating the same function to different addresses. It also requires configuration memory space for the number of states in the entire PE group, and more redundant memory space than the number of states in each PE. Disappear.
  • FIG. 1 is a diagram showing a configuration data management mechanism using state decoding.
  • FIG. 2A is a diagram showing a LUT system as an implementation example of a state decoding unit.
  • FIG. 2B is a diagram showing a RAM system as an implementation example of a state decoding unit.
  • FIG. 3 is a diagram showing an example of implementation of a state decoding unit using a method using an LUT and a method using a RAM.
  • FIG. 4A is a diagram showing a time chart of the operation of the LUT method.
  • FIG. 4B is a diagram showing a time chart of the operation of the RAM method.
  • FIG. 5 A diagram showing an implementation example in which one state decoding unit corresponds to a plurality of processing elements.
  • FIG. 6 A diagram showing a mechanism for dynamically downloading configuration data to memory during execution.
  • FIG. 7 is a diagram showing a configuration of a state management unit.
  • FIG. 8 is a diagram showing a time chart of dynamic configuration at the time of execution.
  • FIG. 9 is a diagram showing a configuration data management mechanism in a conventional method. BEST MODE FOR CARRYING OUT THE INVENTION
  • the reconfigurable circuit shown in the first embodiment is a circuit diagram including a state management unit 1, a processing element 2 (PE), a configuration memory 3, and a state decoding unit 4.
  • a state management unit 1 with a function added to the conventional reconfigurable circuit and a state decoding unit 4 are provided.
  • the state management unit 1 generates management information for managing the state transition of the configuration of PE2.
  • the state decoding unit 4 receives management information from the state management unit 1. Based on the received management information, it generates state transition information for PE2 to make a state transition. Then, a configuration corresponding to a state transition from the configuration memory 3 corresponding to each PE2 is obtained. Read the figure data.
  • FIG. 2A is a diagram showing a configuration of the LUT method.
  • the memory address where PE2 configuration data 3 is recorded is stored on the LUT corresponding to the ID number (management information) of the state managed by the state management unit 1.
  • the ID number of the state is received as the input of the LUT, and the memory address of the corresponding PE is output from the LUT.
  • FIG. 3 shows the operation of the state decoding unit 4.
  • the state management unit 1 has four states as described in FIG. 9, and generates an ID number for each of the four states.
  • the four ID numbers are: 1) ID data indicating the status of A—cl, B—cl ID1, 2) ID data indicating the status of A—c2, B—cl ID2, 3) A—cl, B — Status data indicating the status of c2 is indicated by ID3, 4) A— c2, B— Status data indicating the status of c2 is indicated by management information ID4.
  • State management unit 1 issues an ID number to each state decoding unit 4 provided to correspond to PE2 as ID2.
  • ID2 is transferred to the state decode unit 4 of PE-A and PE-B with “2” (b X OOlO) force.
  • the decoding unit 4 of P E—A receives “2”, it is decoded to 2, and the configuration data corresponding to A—c2 is selected from address 2 of the configuration memory 3.
  • the decoding unit 4 of PE-B receives “2”, it is decoded to 1, and configuration data corresponding to B—c 1 is selected from address 1 of the configuration memory 3.
  • each configuration data currently required by each PE2 is output from the configuration memory 3 to PE-A and PE-B.
  • the other PE2 outputs the configuration data currently required.
  • FIG. 4A is a time chart showing the operation of the LUT method. From the top: 1) Clock signal, 2) State management unit output, 3) State decoding unit output (PE—A), 4) State decoding unit output (PE—B), 5) Configuration memory unit output (PE—A) 6) Configuration memory section output (PE—B), management information (X), state transition information (Y—A, YB) and configuration Show the operation of the urasion data (Z-A, Z-B)!
  • each state decoding unit 4 performs processing without synchronizing with the clock signal indicated by the clock.
  • Each state decoding unit 4 outputs LUT processing result state transition information (Y—A, Y—B).
  • the configuration memory unit 3 selects and outputs the configuration data (Z-A, Z-B).
  • FIG. 2B is an example in which the state decoding unit 4 is configured in a RAM system.
  • the memory address where the configuration data of PE2 is recorded is stored in the memory using the ID number (management information) of the state managed by the state management unit 1 as an address. By inputting the ID number corresponding to the status as an address signal, the status of PE2 is output.
  • the state decoding unit 4 acquires the management information (X) at the rising edge of the clock signal indicated by the state management units 1 to 1) clock. Each state decoding unit 4 outputs state transition information (Y—A, Y—B), which is the result of RAM processing. In synchronization with the clock signal, the configuration memory unit 3 acquires the state transition information (Y—A, Y—B) as the processing result. Thereafter, configuration data (Z-A, Z-B) is selected by the configuration memory unit 3 and PE2 is output.
  • one state decoding unit 4 corresponds to one PE2.
  • one state decoder is used for multiple PEs 2 as shown in Fig. 5. Corresponding to the fifth part.
  • the state decoding unit 5 has the same configuration as the state decoding unit 4, but controls PE2 for each block.
  • the state decoding unit 5 controls a group consisting of PE-A, ⁇ - ⁇ ⁇ 'and a group consisting of PE-E, PE-F- ⁇ ' for each group.
  • the management information indicating all the states of PE-A and PE- ⁇ ... is sent to all ⁇ 2 in the same group.
  • the state decoding unit 5 that has received the management information generates state transition information and transmits it to each configuration memory 3. Based on the state transition information, select the configuration data required by step 2 and output it.
  • Fig. 6 shows a configuration in which the configuration data stored in the state manager is dynamically rewritten when the application is executed.
  • the configuration circuit shown in FIG. 6 includes a state management unit 61, a processing element 62 (PE), a configuration memory 63 (first configuration memory), a state decoding unit 64, a configuration load unit 65, a main memory 66 (first memory). (2 configuration memory) is also a block diagram configured.
  • configuration data that cannot be stored in the configuration memory 63 is stored in the main memory 66.
  • the state management unit 61 stores the contents of analyzing the current state of each PE 62 and the contents of the configuration data downloaded to the configuration memory 63.
  • the state management unit 61 sends an instruction to download the necessary configuration data to the configuration load unit 65.
  • the state management unit 61 analyzes the state of the PE 62 and each configuration data of the configuration memory 63 corresponding to the PE 62, and necessary configuration data information (transfer control signal) based on the analysis result. Is generated.
  • the configuration port unit 65 generates a signal instructing transfer control based on the transfer control signal, and notifies the configuration memory 63, the main memory 66, and the state decoding unit 64.
  • Decoding information is loaded from the main memory 66 into the state decoding unit 64, and configuration data is loaded into the configuration memory 63.
  • the PE 62 reads necessary configuration data from the configuration memory 63.
  • FIG. 7 shows a block diagram of the state management unit 61 and the configuration load unit 65 for realizing dynamic configuration data reading.
  • the state management unit 61 includes a state storage unit 72 that stores state data and a state determination unit 73 that determines the next state based on the state data. Further, the state determination unit 73 refers to the download start flag included in the state data, and when the flag is ON (valid), writes that it is ON (valid) in the download flag unit 71. Then, the configuration load unit 65 is instructed to execute configuration loading (transfer control signal).
  • the configuration load unit 65 includes a configuration memory control unit 74 that receives an instruction from the state management unit 61 and downloads configuration data from the main memory 66. Also, information on where to transfer the configuration data in the configuration memory 63, 66 (download A download data storage unit 75 storing information).
  • the download information can also be downloaded from an external configuration memory 66 (general-purpose memory) without having the download storage unit 75.
  • Figure 8 explains the flow of processing using a time chart.
  • the state management unit 61 when the state determination unit 73 receives the state data from the state storage unit 72, the download start flag is checked together with determining the next state (Tl). If the download start flag is ON (valid), write that it is ON (valid) to the download flag 71 (T2). Also, a download start signal is sent to the configuration load unit 74 (Tl). The configuration load unit 74 receives the download start signal and executes the download ( ⁇ 2).
  • information necessary for downloading includes the area of the configuration memory 66 storing the configuration data to be downloaded and the area of the configuration memory 63 to be downloaded, etc. Stored in the download storage unit 75. Then, the data is read from the download data storage unit 75 in response to the reception of the download start signal.
  • the download information may be stored in the configuration memory 66, and may be configured to eliminate the download data storage unit 75 by calling from the configuration memory 66 as necessary.
  • the configuration memory control unit 74 instructs a data transfer process from the configuration memory 66 to the configuration memory 63 based on the download information.
  • the state determination unit 73 continues the state transition process even during the download execution. This makes it possible to rewrite the configuration data without interrupting the processing in the reconfigurable circuit.
  • a download check flag is attached to the status data. If this flag is not set (valid), whether or not the download is executed If this flag is set, the download flag 71 is referred to, a stall signal is generated during the download execution, and the process inside the reconfigurable circuit is temporarily suspended.
  • the configuration load unit 65 When the configuration load unit 65 completes downloading the predetermined configuration, the configuration load unit 65 transmits a download process completion signal to the state determination unit 73 (T3). In response to the download processing completion signal, the state determination unit 73 turns the download flag OFF (invalid) (T4). If a stall signal is generated and processing in the reconfigurable circuit is suspended, release the stall signal ( ⁇ 4).
  • the configuration memory can be efficiently used by analyzing the state of each box and storing the necessary configuration data in the configuration memory with the above configuration.
  • the configuration memory can be efficiently used because the state of each box is analyzed and the configuration data is stored in the configuration memory.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stored Programmes (AREA)
  • Logic Circuits (AREA)

Abstract

L'invention concerne un circuit reconfigurable dynamiquement utilisant effectivement une mémoire de configuration. Le circuit reconfigurable est formé d'une pluralité d'éléments de traitement et de mémoires de configuration. Le circuit reconfigurable inclut : une unité de gestion d'états permettant de générer des informations de gestion destinées à gérer une transition d'état de configuration des éléments de traitement, ainsi qu'une unité de décodage d'état permettant de recevoir des informations de gestion provenant de l'unité de gestion d'états, de lire les données de configuration correspondant à l'état de transition d'état à partir de la mémoire de configuration correspondant à l'élément de traitement en fonction des informations de gestion, et de générer des informations de transmission d'état afin d'effectuer une transition d'état de l'élément en progression.
PCT/JP2006/304551 2006-03-09 2006-03-09 Circuit reconfigurable WO2007102218A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/JP2006/304551 WO2007102218A1 (fr) 2006-03-09 2006-03-09 Circuit reconfigurable
JP2008503714A JP4410297B2 (ja) 2006-03-09 2006-03-09 リコンフィギャラブル回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2006/304551 WO2007102218A1 (fr) 2006-03-09 2006-03-09 Circuit reconfigurable

Publications (1)

Publication Number Publication Date
WO2007102218A1 true WO2007102218A1 (fr) 2007-09-13

Family

ID=38474665

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2006/304551 WO2007102218A1 (fr) 2006-03-09 2006-03-09 Circuit reconfigurable

Country Status (2)

Country Link
JP (1) JP4410297B2 (fr)
WO (1) WO2007102218A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000089963A (ja) * 1998-09-11 2000-03-31 Canon Inc データ処理装置及びその処理方法
WO2001016711A1 (fr) * 1999-08-30 2001-03-08 Ip Flex Inc. Progiciel et processeur de donnees
JP2004185239A (ja) * 2002-12-02 2004-07-02 Nec Commun Syst Ltd コンフィグレーション制御装置、記録媒体、およびｆｐｇａコンフィグレーション方法
JP2006018515A (ja) * 2004-06-30 2006-01-19 Fujitsu Ltd 演算装置及び演算装置の制御方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000089963A (ja) * 1998-09-11 2000-03-31 Canon Inc データ処理装置及びその処理方法
WO2001016711A1 (fr) * 1999-08-30 2001-03-08 Ip Flex Inc. Progiciel et processeur de donnees
JP2004185239A (ja) * 2002-12-02 2004-07-02 Nec Commun Syst Ltd コンフィグレーション制御装置、記録媒体、およびｆｐｇａコンフィグレーション方法
JP2006018515A (ja) * 2004-06-30 2006-01-19 Fujitsu Ltd 演算装置及び演算装置の制御方法

Also Published As

Publication number Publication date
JPWO2007102218A1 (ja) 2009-07-23
JP4410297B2 (ja) 2010-02-03

Similar Documents

Publication Publication Date Title
US7451293B2 (en) Array of Boolean logic controlled processing elements with concurrent I/O processing and instruction sequencing
US8181003B2 (en) Instruction set design, control and communication in programmable microprocessor cores and the like
JP3101560B2 (ja) プロセッサ
EP1267256A2 (fr) Exécution conditionnelle d'instructions à destinations multiples
JP2007133456A (ja) 半導体装置
JP2000305781A (ja) Ｖｌｉｗ方式プロセッサ、コード圧縮装置、コード圧縮方法およびコード圧縮プログラムを記録した媒体
US20040268088A1 (en) Controlling memory access devices in a data driven architecture mesh array
US20080133899A1 (en) Context switching method, medium, and system for reconfigurable processors
US8495345B2 (en) Computing apparatus and method of handling interrupt
US20090089551A1 (en) Apparatus and method of avoiding bank conflict in single-port multi-bank memory system
JP5096923B2 (ja) 動的再構成論理回路を有するマルチスレッドプロセッサ
JP4779010B2 (ja) バッファリング装置およびバッファリング方法
WO2007102218A1 (fr) Circuit reconfigurable
JP2023533795A (ja) レジスタデータの消去
JP3924577B2 (ja) 制御ワード巻き上げ
JP2003005954A (ja) データ処理装置およびその制御方法
JP2007329760A (ja) プログラマブル論理デバイス、回路情報入力制御装置および半導体装置
JP2005537580A (ja) スタックタイプのスナップショットバッファがネスト化されたインタラプトを処理すること
US8677099B2 (en) Reconfigurable processor with predicate signal activated operation configuration memory and separate routing configuration memory
US9021234B2 (en) Indirect designation of physical configuration number as logical configuration number based on correlation information, within parallel computing
JP2008129851A (ja) 演算処理装置
JP4580879B2 (ja) リコンフィグラブル回路
JP4413905B2 (ja) Ｓｉｍｄ型プロセッサ
JP2004520650A (ja) 固定幅命令エンコード内のプロセッサ操作の拡張された機能性
JP2007323491A (ja) ダイレクトメモリアクセス制御装置および制御方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
ENP Entry into the national phase

Ref document number: 2008503714

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 06715423

Country of ref document: EP

Kind code of ref document: A1