WO2007098024A3 - Affectation de ressources dans un reseau d'ordinateurs - Google Patents

Affectation de ressources dans un reseau d'ordinateurs Download PDF

Info

Publication number
WO2007098024A3
WO2007098024A3 PCT/US2007/004081 US2007004081W WO2007098024A3 WO 2007098024 A3 WO2007098024 A3 WO 2007098024A3 US 2007004081 W US2007004081 W US 2007004081W WO 2007098024 A3 WO2007098024 A3 WO 2007098024A3
Authority
WO
WIPO (PCT)
Prior art keywords
computers
instructions
array
allocation
resources
Prior art date
Application number
PCT/US2007/004081
Other languages
English (en)
Other versions
WO2007098024A2 (fr
Inventor
Charles H Moore
Original Assignee
Vns Portfolio Llc
Charles H Moore
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/355,495 external-priority patent/US7904615B2/en
Priority claimed from US11/355,513 external-priority patent/US7904695B2/en
Priority claimed from US11/441,812 external-priority patent/US7913069B2/en
Priority claimed from US11/441,784 external-priority patent/US7752422B2/en
Priority claimed from US11/441,818 external-priority patent/US7934075B2/en
Application filed by Vns Portfolio Llc, Charles H Moore filed Critical Vns Portfolio Llc
Priority to EP07750884A priority Critical patent/EP1984836A4/fr
Priority to JP2008555370A priority patent/JP2009527814A/ja
Publication of WO2007098024A2 publication Critical patent/WO2007098024A2/fr
Publication of WO2007098024A3 publication Critical patent/WO2007098024A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/321—Program or instruction counter, e.g. incrementing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Multi Processors (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

On décrit un réseau d'ordinateurs (10) réunissant plusieurs ordinateurs (12). Les ordinateurs (12) communiquent directement avec les ordinateurs adjacents et indirectement avec les autres ordinateurs du réseau. Les ordinateurs transmettent des mots de données comprenant des données et/ou des instructions. Jusqu'à quatre instructions peuvent être incluses dans un mot de données de18 bits. Puisque quatre instructions sont communiquées simultanément, il est possible de communiquer une micro-boucle complète constituée de quatre instructions. Les ordinateurs de l'invention peuvent exécuter une instruction directement depuis leurs registres d'entrée.
PCT/US2007/004081 2006-02-16 2007-02-16 Affectation de ressources dans un reseau d'ordinateurs WO2007098024A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP07750884A EP1984836A4 (fr) 2006-02-16 2007-02-16 Affectation de ressources dans un reseau d'ordinateurs
JP2008555370A JP2009527814A (ja) 2006-02-16 2007-02-16 コンピュータのアレイ間でのリソースの割り当て

Applications Claiming Priority (12)

Application Number Priority Date Filing Date Title
US11/355,495 US7904615B2 (en) 2006-02-16 2006-02-16 Asynchronous computer communication
US11/355,495 2006-02-16
US11/355,513 2006-02-16
US11/355,513 US7904695B2 (en) 2006-02-16 2006-02-16 Asynchronous power saving computer
US78826506P 2006-03-31 2006-03-31
US60/788,265 2006-03-31
US11/441,812 US7913069B2 (en) 2006-02-16 2006-05-26 Processor and method for executing a program loop within an instruction word
US11/441,812 2006-05-26
US11/441,784 US7752422B2 (en) 2006-02-16 2006-05-26 Execution of instructions directly from input source
US11/441,818 US7934075B2 (en) 2006-02-16 2006-05-26 Method and apparatus for monitoring inputs to an asyncrhonous, homogenous, reconfigurable computer array
US11/441,818 2006-05-26
US11/441,784 2006-05-26

Publications (2)

Publication Number Publication Date
WO2007098024A2 WO2007098024A2 (fr) 2007-08-30
WO2007098024A3 true WO2007098024A3 (fr) 2008-12-31

Family

ID=38437887

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/004081 WO2007098024A2 (fr) 2006-02-16 2007-02-16 Affectation de ressources dans un reseau d'ordinateurs

Country Status (4)

Country Link
EP (1) EP1984836A4 (fr)
JP (1) JP2009527814A (fr)
KR (1) KR20090003217A (fr)
WO (1) WO2007098024A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115586972B (zh) * 2022-11-25 2023-02-28 成都登临科技有限公司 命令生成方法、装置、ai芯片、电子设备及存储介质

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5673423A (en) * 1988-02-02 1997-09-30 Tm Patents, L.P. Method and apparatus for aligning the operation of a plurality of processors
US20040030859A1 (en) * 2002-06-26 2004-02-12 Doerr Michael B. Processing system with interspersed processors and communication elements

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5440749A (en) * 1989-08-03 1995-08-08 Nanotronics Corporation High performance, low cost microprocessor architecture
DE4019040A1 (de) 1990-06-14 1991-12-19 Philips Patentverwaltung Multirechnersystem
SE514785C2 (sv) 1999-01-18 2001-04-23 Axis Ab Processor och metod för att exekvera instruktioner från flera instruktionskällor
US7937557B2 (en) 2004-03-16 2011-05-03 Vns Portfolio Llc System and method for intercommunication between computers in an array

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5673423A (en) * 1988-02-02 1997-09-30 Tm Patents, L.P. Method and apparatus for aligning the operation of a plurality of processors
US20040030859A1 (en) * 2002-06-26 2004-02-12 Doerr Michael B. Processing system with interspersed processors and communication elements

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1984836A4 *

Also Published As

Publication number Publication date
KR20090003217A (ko) 2009-01-09
WO2007098024A2 (fr) 2007-08-30
JP2009527814A (ja) 2009-07-30
EP1984836A4 (fr) 2009-08-26
EP1984836A2 (fr) 2008-10-29

Similar Documents

Publication Publication Date Title
WO2007137034A3 (fr) Gestion de ressources informatiques pour des calculs à base de graphes
WO2007146731A3 (fr) Support informatique en grappe pour logiciels d'application
JP2006320014A5 (fr)
WO2007130998A3 (fr) Système basé sur page web pour la conception d'applications web pilotées par base de données
WO2007121452A3 (fr) Branchement et partitionnement comportemental pour un processeur a mot d'instruction tres long (processeur vliw)
WO2007067275A3 (fr) Système d'accélération vliw utilisant une logique multi-état
WO2007053766A3 (fr) Refroidissement d'elements d'un continuum
WO2009028889A3 (fr) Procédé d'interface d'entrée de clés
WO2008127610A3 (fr) Interface d'applications sur plusieurs processeurs
WO2010043401A3 (fr) Dispositif de traitement de données
TW200607290A (en) Facilitating access to input/output resources via an I/O partition shared by multiple consumer partitions
WO2005008410A3 (fr) Processeur programmable et procede a operations etendues
WO2011044398A3 (fr) Ordinateur pour des algorithmes compatibles-amdahl de type inversion de matrice
FR2926375B1 (fr) Procede d'execution d'une application informatique, kit et aeronef associes
WO2006012070A3 (fr) Instruction conditionnelle pour un moteur d'execution simple instruction/donnees multiples
WO2007100422A8 (fr) Définition d'un document informatisé basée sur une instance edi
WO2005091847A3 (fr) Batterie d'ordinateurs
WO2007114891A3 (fr) Distribution d'opérations parallèles
WO2010093657A3 (fr) Microcontrôleur à mémoire linéaire dans une mémoire à blocs
WO2008133980A3 (fr) Système et procédé pour des opérations de lecture et d'écriture multiports
TW200727139A (en) Computer system and memory bridge thereof
WO2007098024A3 (fr) Affectation de ressources dans un reseau d'ordinateurs
WO2007057828A3 (fr) Systeme et procede de traitement pour executer des instructions
TW200746170A (en) Memory circuit
DE602007011841D1 (de) Ausführung von Anweisungen direkt von der Eingabequelle aus

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2007750884

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 6935/DELNP/2008

Country of ref document: IN

WWE Wipo information: entry into national phase

Ref document number: 200780005652.2

Country of ref document: CN

Ref document number: 2008555370

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 1020087022319

Country of ref document: KR