WO2007098024A2 - Affectation de ressources dans un reseau d'ordinateurs - Google Patents

Affectation de ressources dans un reseau d'ordinateurs Download PDF

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Publication number
WO2007098024A2
WO2007098024A2 PCT/US2007/004081 US2007004081W WO2007098024A2 WO 2007098024 A2 WO2007098024 A2 WO 2007098024A2 US 2007004081 W US2007004081 W US 2007004081W WO 2007098024 A2 WO2007098024 A2 WO 2007098024A2
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WO
WIPO (PCT)
Prior art keywords
computer
computers
instruction
array
instructions
Prior art date
Application number
PCT/US2007/004081
Other languages
English (en)
Other versions
WO2007098024A3 (fr
Inventor
Charles H. Moore
Original Assignee
Vns Portfolio Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/355,495 external-priority patent/US7904615B2/en
Priority claimed from US11/355,513 external-priority patent/US7904695B2/en
Priority claimed from US11/441,784 external-priority patent/US7752422B2/en
Priority claimed from US11/441,818 external-priority patent/US7934075B2/en
Priority claimed from US11/441,812 external-priority patent/US7913069B2/en
Application filed by Vns Portfolio Llc filed Critical Vns Portfolio Llc
Priority to EP07750884A priority Critical patent/EP1984836A4/fr
Priority to JP2008555370A priority patent/JP2009527814A/ja
Publication of WO2007098024A2 publication Critical patent/WO2007098024A2/fr
Publication of WO2007098024A3 publication Critical patent/WO2007098024A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/321—Program or instruction counter, e.g. incrementing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]

Definitions

  • the present invention relates to the field of computers and computer processors, and more particularly to a method and means for a unique type of interaction between computers.
  • the predominant current usage of the present inventive computer array is in the combination of multiple computers on a single microchip.
  • a known embodiment of the present invention is an array of computers, each computer having its own memory and being capable of independent computational functions.
  • the computers In order to accomplish tasks cooperatively, the computers must pass data and/or instructions from one to another.
  • the computers have connecting data paths between orthogonally adjacent computers such that each computer can communicate directly with as many as four "neighbors". If it is desired for a computer to communicate with another that is not an immediate neighbor, then communications will be channeled through other computers to the desired destination.
  • each data word can consist of a min-program, which will be referred to herein as micro-loops.
  • micro-loops While a computer might need to borrow processing power, or the like, from a neighbor another likely possibility is that it may need to borrow some memory from a neighbor, using it in a manner somewhat similar to its own internal memory. By passing a micro-loop to a neighbor instructing it to read or write a series of data, such memory borrowing can be readily accomplished.
  • Such a micro loop might contain, for example, an instruction to write from a particular internal memory location, increment that location, and then repeat for a given number of iterations.
  • Formlets are presently implemented in the Forth computer language - although the application of the invention is not limited strictly to use with Forth.
  • a Forthlet is a mini-program that can be transmitted directly to a computer for execution.
  • an instruction must be read and stored before execution but, as will be seen in light of the detailed description herein, that is not necessary according to the present invention. Indeed, it is anticipated that an important aspect of the invention will be that a computer can generate a Forthlet and pass it off to another computer for execution. Forthlets can be "pre-written" by a programmer and stored for use.
  • Forthlets can be accumulated into a "library” for use as needed.
  • Forthlets can be generated, according to pre-programmed criteria, within a computer.
  • I/O registers are treated as memory addresses which means that the same (or similar) instructions that read and write memory can also perform I/O operations.
  • multi-core chips there is a powerful ramification of this choice for I/O structure.
  • the core processor read and execute instructions from its local ROM and RAM, it can also read and execute instructions presented to it on I/O ports or registers. Now the concept of tight loops transferring data becomes incredibly powerful.
  • each instruction fetch brings a plurality (four in the presently described embodiment) of instructions into the core processor.
  • this sort of built-in "cache" is certainly small, it is extremely effective when the instructions themselves take advantage of it. For instance, micro for — next loops can be constructed that are contained entirely within the bounds of a single 18-bit instruction word.
  • These types of constructs are ideal when combined with the automatic status signaling built into the I/O registers because that means large blocks of data can be transferred with only a single instruction fetch.
  • the concept of executing instructions being presented on a shared I/O register from a neighboring processor core takes on new power because now each word appearing in that register represents not one, but four instructions.
  • Fig. 1 is a diagrammatic view of a computer array, according to the present invention.
  • Fig. 2 is a detailed diagram showing a subset of the computers of Fig. 1 and a more detailed view of the interconnecting data buses of Fig. 1;
  • Fig. 3 is a block diagram depicting a general layout of one of the computers of Figs. 1 and 2;
  • Fig. 4 is a diagrammatic representation of an instruction word according to the present inventive application;
  • Fig. 5 is a schematic representation of the slot sequencer 42 of Fig. 3.
  • a known mode for carrying out the invention is an array of individual computers.
  • the inventive computer array is depicted in a diagrammatic view in Fig. 1 and is designated therein by the general reference character 10.
  • the computer array 10 has a plurality (twenty four in the example shown) of computers 12 (sometimes also referred to as "cores" or “nodes” in the example of an array). In the example shown, all of the computers 12 are located on a single die 14. According to the present invention, each of the computers 12 is a generally independently functioning computer, as will be discussed in more detail hereinafter.
  • the computers 12 are interconnected by a plurality (the quantities of which will be discussed in more detail hereinafter) of interconnecting data buses 16.
  • the data buses 16 are bidirectional asynchronous high speed parallel data buses, although it is within the scope of the invention that other interconnecting means might be employed for the purpose.
  • the individual computers 12 In the present embodiment of the array 10, not only is data communication between the computers 12 asynchronous, the individual computers 12 also operate in an internally asynchronous mode. This has been found by the inventor to provide important advantages. For example, since a clock signal does not have to be distributed throughout the computer array 10, a great deal of power is saved. Furthermore, not having to distribute a clock signal eliminates many timing problems that could limit the size of the array 10 or cause other known difficulties.
  • Such additional components include power buses, external connection pads, and other such common aspects of a microprocessor chip.
  • Computer 12e is an example of one of the computers 12 that is not on the periphery of the array 10. That is, computer 12e has four orthogonally adjacent computers 12a, 12b, 12c and 12d. This grouping of computers 12a through 12e will be used hereinafter in relation to a more detailed discussion of the communications between the computers 12 of the array 10. As can be seen in the view of Fig. 1, interior computers such as computer 12e will have four other computers 12 with which they can directly communicate via the buses 16. In the following discussion, the principles discussed will apply to all of the computers 12 except that the computers 12 on the periphery of the array 10 will be in direct communication with only three or, in the case of the corner computers 12, only two other of the computers 12.
  • Fig. 2 is a more detailed view of a portion of Fig. 1 showing only some of the computers 12 and, in particular, computers 12a through 12e, inclusive.
  • the view of Fig. 2 also reveals that the data buses 16 each have a read line 18, a write line 20 and a plurality (eighteen, in this example) of data lines 22.
  • the data lines 22 are capable of transferring all the bits of one eighteen-bit instruction word generally simultaneously in parallel.
  • some of the computers 12 are mirror images of adjacent computers. However, whether the computers 12 are all oriented identically or as mirror images of adjacent computers is not an aspect of this presently described invention. Therefore, in order to better describe this invention, this potential complication will not be discussed further herein.
  • a computer 12, such as the computer 12e can set one, two, three or all four of its read lines 18 such that it is prepared to receive data from the respective one, two, three or all four adjacent computers 12.
  • a computer 12 can set one, two, three or all four of its write lines 20 high.
  • computer 12e was described as setting one or more of its read lines 18 high before an adjacent computer (selected from one or more of the computers 12a, 12b, 12c or 12d) has set its write line 20 high.
  • this process can certainly occur in the opposite order. For example, if the computer 12e were attempting to write to the computer 12a, then computer 12e would set the write line 20 between computer 12e and computer 12a to high. If the read line 18 between computer 12e and computer 12a has then not already been set to high by computer 12a, then computer 12e will simply wait until computer 12a does set that read line 20 high.
  • the receiving computer 12 sets both the read line 18 and the write line 20 between the two computers (12e and 12a in this example) to low as soon as the sending computer 12e releases it.
  • the computers 12 there may be several potential means and/or methods to cause the computers 12 to function as described above.
  • the computers 12 so behave simply because they are operating generally asynchronously internally (in addition to transferring data there-between in the asynchronous manner described). That is, instructions are completed sequentially. When either a write or read instruction occurs, there can be no further action until that instruction is completed (or, perhaps alternatively, until it is aborted, as by a "reset” or the like). There is no regular clock pulse, in the prior art sense.
  • FIG. 3 is a block diagram depicting the general layout of an example of one of the computers 12 of Figs. 1 and 2. As can be seen in the view of Fig. 3, each of the computers 12 is a generally self contained computer having its own RAM 24 and ROM 26. As mentioned previously, the computers 12 are also sometimes referred to as individual "cores", given that they are, in the present example, combined on a single chip.
  • a return stack 28 Other basic components of the computer 12 are a return stack 28, an instruction area 30, an arithmetic logic unit (“ALU") 32, a data stack 34 . and a decode logic section 36 for decoding instructions.
  • ALU arithmetic logic unit
  • the computers 12 are dual stack computers having the data stack 34 and separate return stack 28.
  • the computer 12 has four communication ports 38 for communicating with adjacent computers 12.
  • the communication ports 38 are tri-state drivers, having an off status, a receive status (for driving signals into the computer 12) and a send status (for driving signals out of the computer 12)
  • the particular computer 12 is not on the interior of the array (Fig. 1) such as the example of computer 12e, then one or more of the communication ports will not be used in that particular computer, at least for the purposes described herein.
  • the instruction area 30 includes a number of registers 40 including, in this example, an A register 40a, a B register 40b and . a P register 40c.
  • the A register 40a is a full eighteen-bit register, while the B register 40b and the P register 40c are nine-bit registers.
  • the present computer 12 is implemented to execute native Forth language instructions. As one familiar with the Forth computer language will appreciate, complicated Forth instructions, known as Forth "words" are constructed from the native processor instructions designed into the computer. The collection of Forth words is known as a "dictionary”. In other languages, this might be known as a "library”. As will be described in greater detail hereinafter, the computer 12 reads eighteen bits at a time from RAM 24, ROM 26 or directly from one of the data buses 16 (Fig. 2).
  • Fig. 3 is a slot sequencer 42.
  • the top two registers in the data stack 34 are a T register 44 and an S register 46.
  • Fig. 4 is a diagrammatic representation of an instruction word 48. (It should be noted that the instruction word 48 can actually contain instructions, data, or some combination thereof.)
  • the instruction word 48 consists of eighteen bits 50.
  • each of the bits 50 will be a '1' or a 'O 1 .
  • the eighteen-bit wide instruction word 48 can contain up to four instructions 52 in four slots 54 called slot zero 54a, slot one 54b, slot two 54c and slot three 54d.
  • the eighteen-bit instruction words 48 are always read as a whole. Therefore, since there is always a potential of having up to four instructions in the instruction word 48, a no-op (no operation) instruction is included in the instruction set of the computer 12 to provide for instances when using all of the available slots 54 might be unnecessary or even undesirable.
  • Fig. 5 is a schematic representation of the slot sequencer 42 of Fig. 3.
  • the slot sequencer 42 has a plurality (fourteen in this example) of inverters 56 and one NAND gate 58 arranged in a ring, such that a signal is inverted an odd number of times as it travels through the fourteen inverters 56 and the NAND gate 58.
  • a signal is initiated in the slot sequencer 42 when either of the two inputs to an OR gate 60 goes high.
  • a first OR gate input 62 is derived from a bit i4 66 (Fig. 4) of the instruction 52 being executed. If bit i4 is high then that particular instruction 52 is an ALL) instruction, and the i4 bit 66 is '1'. When the i4 bit is '1', then the first OR gate input 62 is high, and the slot sequencer 42 is triggered to initiate a pulse that will cause the execution of the next instruction 52.
  • a signal will travel around the slot sequencer 42 twice, producing an output at a slot sequencer output 68 each time.
  • the relatively wide output from the slot sequencer output 68 is provided to a pulse generator 70 (shown in block diagrammatic form) that produces a narrow timing pulse as an output.
  • a pulse generator 70 shown in block diagrammatic form
  • the i4 bit 66 is '0' (low) and the first OR gate input 62 is, therefore, also low.
  • the slot sequencer 42 will not be triggered - assuming that the second OR gate input 66, which will be' discussed hereinafter, is not high.
  • the i4 bit 66 of each instruction 52 is set according to whether or not that instruction is a read or write type of instruction.
  • the remaining bits 50 in the instruction 52 provide the remainder of the particular opcode for that instruction.
  • one or more of the bits may be used to indicate where data is to be read from or written to in that particular computer 12.
  • data to be written always comes from the T register 44 (the top of the data stack 34), however data can be selectively read into either the T register 44 or else the instruction area 30 from where it can be executed. That is because, in this particular embodiment of the invention, either data or instructions can be communicated in the manner described herein and instructions can, therefore, be executed directly from the data bus 16, although this is not a necessary aspect of this present invention.
  • one or more of the bits 50 will be used to indicate which of the ports 38, if any, is to be set to read or write. This later operation is optionally accomplished by using one or more bits to designate a register 40, such as the A register 40a, the B register, or the like.
  • the designated register 40 will be preloaded with data having a bit corresponding to each of the ports 38 (and, also, any other potential entity with which the computer 12 may be attempting to communicate, such as memory, an external communications port, or the like.)
  • each of four bits in the particular register 40 can correspond to each of the up port 38a, the right port 38b, the left port 38c or the down port 38d. In such case, where there is a '1' at any of those bit locations, communication will be set to proceed through the corresponding port 38.
  • a read opcode might set more than one port 38 for communication in a single instruction while, although it is possible, it is not anticipated that a write opcode will set more than one port 38 for communication in a single instruction.
  • the opcode of the instruction 52 will have a '0' at bit position i4 66, and so the first OR gate input 62 of the OR gate 60 is low, and so the slot sequencer 42 is not triggered to generate an enabling pulse.
  • both the read line 18 and the corresponding write line 20 between computers 12e and 12c are high, then both lines 18 and 20 will be released by each of the respective computers 12 that is holding it high.
  • the sending computer 12e will be holding the write line 18 high while the receiving computer 12c will be holding the read line 20 high).
  • the receiving computer 12c will pull both lines 18 and 20 low.
  • the receiving computer 12c may attempt to pull the lines 18 and 20 low before the sending computer 12e has released the write line 18.
  • acknowledge line 72 provides the second OR gate input 64. Since an input to either of the OR gate 60 inputs 62 or 64 will cause the output of the OR gate 60 to go high, this will initiate operation of the slot sequencer 42 in the manner previously described herein, such that the instruction 52 in the next slot 54 of the instruction word 48 will be executed.
  • the acknowledge line 72 stays high until the next instruction 52 is decoded, in order to prevent spurious addresses from reaching the address bus.
  • the computer 12 will fetch the next awaiting eighteen-bit instruction word 48 unless, of course, bit i4 66 is a 1 O'.
  • the present inventive mechanism includes a method and apparatus for "prefetching" instructions such that the fetch can begin before the end of the execution of all instructions 52 in the instruction word 48.
  • this also is not a necessary aspect of the present inventive method and apparatus for asynchronous data communications.
  • the inventor believes that a key feature for enabling efficient asynchronous communications between devices is some sort of acknowledge signal or condition.
  • acknowledge signal or condition In the prior art, most communication between devices has been clocked and there is no direct way for a sending device to know that the receiving device has properly received the data. Methods such as checksum operations may have been used to attempt to insure that data is correctly received, but the sending device has no direct indication that the operation is completed.
  • the present inventive method provides the necessary acknowledge condition that allows, or at least makes practical, asynchronous communications between the devices. Furthermore, the acknowledge condition also makes it possible for one or more of the devices to "go to sleep" until the acknowledge condition occurs.
  • an acknowledge condition could be communicated between the computers 12 by a separate signal being sent between the computers 12 (either over the interconnecting data bus 16 or over a separate signal line), and such an acknowledge signal would be within the scope of this aspect of the present invention.
  • the method for acknowledgement does not require any additional signal, clock cycle, timing pulse, or any such resource beyond that described, to actually affect the communication.
  • inventive computer array 10, computers 12 and associated method 74 are intende ; d to be widely used in a great variety of computer applications. It is expected that it they will be particularly useful in applications where significant computing power is required, and yet power consumption and heat production are important considerations.
  • the applicability of the present invention is such that many types of inter-device computer communications can be improved thereby. It is anticipated that the inventive method, wherein some computers can be allowed to "go to sleep" when not in use, will be used to reduce power consumption, reduce heat production, and improve the efficiency of communication between computers and computerized devices in a great variety of applications and implementations. Since the computer array 10, computer 12 and method 74 of the present invention may be readily produced and integrated with existing tasks, input/output devices, and the like, and since the advantages as described herein are provided, it is expected that they will be readily accepted in the industry. For these and other reasons, it is expected that the utility and industrial applicability of the invention will be both significant in scope and long-lasting in duration.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Multi Processors (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)

Abstract

On décrit un réseau d'ordinateurs (10) réunissant plusieurs ordinateurs (12). Les ordinateurs (12) communiquent directement avec les ordinateurs adjacents et indirectement avec les autres ordinateurs du réseau. Les ordinateurs transmettent des mots de données comprenant des données et/ou des instructions. Jusqu'à quatre instructions peuvent être incluses dans un mot de données de18 bits. Puisque quatre instructions sont communiquées simultanément, il est possible de communiquer une micro-boucle complète constituée de quatre instructions. Les ordinateurs de l'invention peuvent exécuter une instruction directement depuis leurs registres d'entrée.
PCT/US2007/004081 2006-02-16 2007-02-16 Affectation de ressources dans un reseau d'ordinateurs WO2007098024A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP07750884A EP1984836A4 (fr) 2006-02-16 2007-02-16 Affectation de ressources dans un reseau d'ordinateurs
JP2008555370A JP2009527814A (ja) 2006-02-16 2007-02-16 コンピュータのアレイ間でのリソースの割り当て

Applications Claiming Priority (12)

Application Number Priority Date Filing Date Title
US11/355,513 2006-02-16
US11/355,495 US7904615B2 (en) 2006-02-16 2006-02-16 Asynchronous computer communication
US11/355,513 US7904695B2 (en) 2006-02-16 2006-02-16 Asynchronous power saving computer
US11/355,495 2006-02-16
US78826506P 2006-03-31 2006-03-31
US60/788,265 2006-03-31
US11/441,812 2006-05-26
US11/441,784 US7752422B2 (en) 2006-02-16 2006-05-26 Execution of instructions directly from input source
US11/441,784 2006-05-26
US11/441,818 US7934075B2 (en) 2006-02-16 2006-05-26 Method and apparatus for monitoring inputs to an asyncrhonous, homogenous, reconfigurable computer array
US11/441,812 US7913069B2 (en) 2006-02-16 2006-05-26 Processor and method for executing a program loop within an instruction word
US11/441,818 2006-05-26

Publications (2)

Publication Number Publication Date
WO2007098024A2 true WO2007098024A2 (fr) 2007-08-30
WO2007098024A3 WO2007098024A3 (fr) 2008-12-31

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EP (1) EP1984836A4 (fr)
JP (1) JP2009527814A (fr)
KR (1) KR20090003217A (fr)
WO (1) WO2007098024A2 (fr)

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CN115586972A (zh) * 2022-11-25 2023-01-10 成都登临科技有限公司 命令生成方法、装置、ai芯片、电子设备及存储介质
CN115586972B (zh) * 2022-11-25 2023-02-28 成都登临科技有限公司 命令生成方法、装置、ai芯片、电子设备及存储介质

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KR20090003217A (ko) 2009-01-09
JP2009527814A (ja) 2009-07-30

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