EP1984836A2 - Affectation de ressources dans un reseau d'ordinateurs - Google Patents

Affectation de ressources dans un reseau d'ordinateurs

Info

Publication number
EP1984836A2
EP1984836A2 EP07750884A EP07750884A EP1984836A2 EP 1984836 A2 EP1984836 A2 EP 1984836A2 EP 07750884 A EP07750884 A EP 07750884A EP 07750884 A EP07750884 A EP 07750884A EP 1984836 A2 EP1984836 A2 EP 1984836A2
Authority
EP
European Patent Office
Prior art keywords
computer
computers
instruction
array
instructions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP07750884A
Other languages
German (de)
English (en)
Other versions
EP1984836A4 (fr
Inventor
Charles H. Moore
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
VNS Portfolio LLC
Original Assignee
VNS Portfolio LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/355,495 external-priority patent/US7904615B2/en
Priority claimed from US11/355,513 external-priority patent/US7904695B2/en
Priority claimed from US11/441,812 external-priority patent/US7913069B2/en
Priority claimed from US11/441,784 external-priority patent/US7752422B2/en
Priority claimed from US11/441,818 external-priority patent/US7934075B2/en
Application filed by VNS Portfolio LLC filed Critical VNS Portfolio LLC
Publication of EP1984836A2 publication Critical patent/EP1984836A2/fr
Publication of EP1984836A4 publication Critical patent/EP1984836A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/321—Program or instruction counter, e.g. incrementing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Multi Processors (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

On décrit un réseau d'ordinateurs (10) réunissant plusieurs ordinateurs (12). Les ordinateurs (12) communiquent directement avec les ordinateurs adjacents et indirectement avec les autres ordinateurs du réseau. Les ordinateurs transmettent des mots de données comprenant des données et/ou des instructions. Jusqu'à quatre instructions peuvent être incluses dans un mot de données de18 bits. Puisque quatre instructions sont communiquées simultanément, il est possible de communiquer une micro-boucle complète constituée de quatre instructions. Les ordinateurs de l'invention peuvent exécuter une instruction directement depuis leurs registres d'entrée.
EP07750884A 2006-02-16 2007-02-16 Affectation de ressources dans un reseau d'ordinateurs Withdrawn EP1984836A4 (fr)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US11/355,495 US7904615B2 (en) 2006-02-16 2006-02-16 Asynchronous computer communication
US11/355,513 US7904695B2 (en) 2006-02-16 2006-02-16 Asynchronous power saving computer
US78826506P 2006-03-31 2006-03-31
US11/441,812 US7913069B2 (en) 2006-02-16 2006-05-26 Processor and method for executing a program loop within an instruction word
US11/441,784 US7752422B2 (en) 2006-02-16 2006-05-26 Execution of instructions directly from input source
US11/441,818 US7934075B2 (en) 2006-02-16 2006-05-26 Method and apparatus for monitoring inputs to an asyncrhonous, homogenous, reconfigurable computer array
PCT/US2007/004081 WO2007098024A2 (fr) 2006-02-16 2007-02-16 Affectation de ressources dans un reseau d'ordinateurs

Publications (2)

Publication Number Publication Date
EP1984836A2 true EP1984836A2 (fr) 2008-10-29
EP1984836A4 EP1984836A4 (fr) 2009-08-26

Family

ID=38437887

Family Applications (1)

Application Number Title Priority Date Filing Date
EP07750884A Withdrawn EP1984836A4 (fr) 2006-02-16 2007-02-16 Affectation de ressources dans un reseau d'ordinateurs

Country Status (4)

Country Link
EP (1) EP1984836A4 (fr)
JP (1) JP2009527814A (fr)
KR (1) KR20090003217A (fr)
WO (1) WO2007098024A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115586972B (zh) * 2022-11-25 2023-02-28 成都登临科技有限公司 命令生成方法、装置、ai芯片、电子设备及存储介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0461724A2 (fr) * 1990-06-14 1991-12-18 Philips Patentverwaltung GmbH Système multiordinateur
WO2000042506A1 (fr) * 1999-01-18 2000-07-20 Axis Ab Processeur et procede permettant l'execution d'instructions provenant de plusieurs sources d'instructions
US6598148B1 (en) * 1989-08-03 2003-07-22 Patriot Scientific Corporation High performance microprocessor having variable speed system clock
WO2005091847A2 (fr) * 2004-03-16 2005-10-06 Technology Properties, Ltd. Batterie d'ordinateurs

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5222237A (en) * 1988-02-02 1993-06-22 Thinking Machines Corporation Apparatus for aligning the operation of a plurality of processors
US7415594B2 (en) * 2002-06-26 2008-08-19 Coherent Logix, Incorporated Processing system with interspersed stall propagating processors and communication elements

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6598148B1 (en) * 1989-08-03 2003-07-22 Patriot Scientific Corporation High performance microprocessor having variable speed system clock
EP0461724A2 (fr) * 1990-06-14 1991-12-18 Philips Patentverwaltung GmbH Système multiordinateur
WO2000042506A1 (fr) * 1999-01-18 2000-07-20 Axis Ab Processeur et procede permettant l'execution d'instructions provenant de plusieurs sources d'instructions
WO2005091847A2 (fr) * 2004-03-16 2005-10-06 Technology Properties, Ltd. Batterie d'ordinateurs

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
GIRAU B ET AL: "Evolvable platform for array processing: a one-chip approach" MICROELECTRONICS FOR NEURAL, FUZZY AND BIO-INSPIRED SYSTEMS, 1999. MIC RONEURO '99. PROCEEDINGS OF THE SEVENTH INTERNATIONAL CONFERENCE ON GRANADA, SPAIN 7-9 APRIL 1999, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 7 April 1999 (1999-04-07) , pages 187-193, XP010329509 ISBN: 978-0-7695-0043-0 *
MAJURSKI W ET AL: "Flits: pervasive computing for processor and memory constrained systems" PARALLEL PROCESSING, 2000. PROCEEDINGS. 2000 INTERNATIONAL WORKSHOPS O N 21-24 AUGUST 2000, PISCATAWAY, NJ, USA,IEEE, 21 August 2000 (2000-08-21), pages 31-38, XP010511930 ISBN: 978-0-7695-0771-2 *
See also references of WO2007098024A2 *
ZHIYI YU ET AL: "An asynchronous array of simple processors for dsp applications" SOLID-STATE CIRCUITS, 2006 IEEE INTERNATIONAL CONFERENCE DIGEST OF TEC HNICAL PAPERS FEB. 6-9, 2006, PISCATAWAY, NJ, USA,IEEE, 6 February 2006 (2006-02-06) , pages 1696-1705, XP010940569 ISBN: 978-1-4244-0079-9 *

Also Published As

Publication number Publication date
WO2007098024A3 (fr) 2008-12-31
EP1984836A4 (fr) 2009-08-26
JP2009527814A (ja) 2009-07-30
WO2007098024A2 (fr) 2007-08-30
KR20090003217A (ko) 2009-01-09

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