WO2007076576A1

WO2007076576A1 - Method and structure for a high performance semiconductor device

Info

Publication number: WO2007076576A1
Application number: PCT/AU2006/001976
Authority: WO
Inventors: Shaun Joseph Cunningham
Original assignee: Epitactix Pty Ltd
Priority date: 2005-12-30
Filing date: 2006-12-29
Publication date: 2007-07-12

Abstract

The present invention relates generally to integrated circuit devices. In one form, the invention provides a manufacturing method and resulting structure for a compound semiconductor heterojunction bipolar transistor (HBT) which provides scalable device feature size and reduced manufacturing complexity. A preferred embodiment of the present invention provides for the fabrication of an integrated circuit device comprising: converting at least one portion of a layered arrangement of semiconductor materials to an insulating state to form an isolation region and at least one isolated device bounded by the isolation region; subsequently providing at least one layer of material operatively associated with the isolated device and which extends across an isolation region boundary to form at least one region of overlap within the isolation region. Consequently, embodiments of the present invention provide for improved precision of device alignment, reduced emitter widths for improved performance and enlarged metal interconnects for circuit connectivity and heat dissipation.

Description

Method and Structure for a High Performance Semiconductor Device RELATED APPLICATIONS

This application claims priority to Australian Provisional Patent Application No. 2005907335 in the name of EpiTactix Pty Ltd, which was filed on 30 December 2005, entitled "Method and Structure for a High Performance Scalable Heterojunction Bipolar Transistor", the specification of which is incorporated herein by reference in its entirety and for all purposes. FfELD OF INVENTION

The present invention relates generally to integrated circuit devices, in one form, the invention provides a manufacturing method and resulting structure for a compound semiconductor heterojunction bipolar transistor (HBT) which provides scalable device feature size and reduced manufacturing complexity. It will be appreciated, however, that there can be many variations, modifications, and alternatives. It will be convenient to hereinafter describe the invention in relation to a Scalable Heterojunction Bipolar Transistor (SHBT) comprising a GaAs substrate, however it should be appreciated that the present invention is not limited to that use only. BACKGROUND ART

The inventor has identified the following background and related art. Compound semiconductor material systems based on gallium arsenide

(GaAs), indium phosphide (InP) and other elemental compounds nave been widely used in the manufacture of high performance HBTs. In this regard, epitaxial layers may be grown on wafers made from these materials at the beginning of the manufacturing process and then patterned to form individual HBT devices. The choice of materials for these epitaxial layers is often taken into account such that the resulting device performance is optimised.

On gallium arsenide wafers for example, conventional HBTs may be made using layers of materials such as indium gallium phosphide (InGaP), indium gallium arsenide (InGaAs), aluminium gallium arsenide (AlGaAs) and aluminium arsenide (AIAs). On indium phosphide wafers, HBTs may be made using indium galfium arsenide material. In each case the materials are chosen to achieve desired electrical properties of the transistors and desired chemical properties for the fabrication process. Although there have been significant improvements in conventional fabrication processes, many limitations stilf exist and additional improvement is desired.

Figure 1 shows a typical layer structure used to form npn GaAs HBTs.

Typically, layer structures are devised which not only achieve desired electronic properties of a transistor but which also offer wafer processing advantages such as selective etching. Selective etching techniques allow one layer to be removed in certain areas of the wafer without affecting underlying or surrounding layers.

This may be particularly important in controlling etching processes which need to stop abruptly on the boundaries of layers which might be very thin (e.g. 100 - 500 angstroms).

Transistor performance is not only determined by the choice of layer material but also layer thickness. Selection of layer thickness may sometimes involve a compromise between certain transistor parameters. For example, in conventional devices, high speed devices often need thin layers to shorten electron transit times while high power devices generally need thick layers to withstand high voltages. Therefore, in general, it is not considered possible to completely optimise a conventional transistor for both high speed and high operating voltage. Typical layer thicknesses for npn GaAs / InGaP HBT devices are also shown in Figure 1. Transistor performance may also be affected by device geometry. For example it is advantageous to make devices as small as possible in order to maximise their operating frequency. As devices become smaller, their maximum operating frequency increases because both junction capacitance and spreading resistance are reduced by making the device smaller. Spreading resistance is the resistance encountered between the lateral base contacts and the central, active area of the device due to the resistivity of typical semiconductor materials and the physical displacement of the contacts.

Figure 2 provides an example of a certain conventional device structure. The emitter mesa structure 200 of figure 2 is comprised of four semiconductor layers:

• layer 204 forms the emitter side of the emitter/base heterojunction and is made of a material which has different etching characteristics than the adjacent layers, • layer 203 is a buffer / spacer layer,

• layer 202 is a graded structure which varies from .the crystal lattice spacing of GaAs at the interface to layer 203 to the lattice spacing of InGaAs (50% Ga) at the interface to layer 201 , and • layer 201 which allows a non-alloyed ohmic contact to be made to the emitter structure.

The emitter mesa 200 may be formed. by firstly depositing and patterning emitter contact iayer 205 on the surface of a wafer which has a layer structure as shown in Figure 1. Next, emitter layers 201 , 202 and 203 are etched away except where protected by the emitter contact 205. Etching stops at layer 204 because it is unaffected by the etchant used to remove layers 201 - 203. However etching continues horizontally and helps to produce undercut sidewalls of the emitter mesa structure.

Layer 204 may then be selectively removed using an etchant which does_ not affect the underlying base layer 207. In this way, the emitter mesa can be formed without degrading the very thin base layer 207.

The base contact layer 206b may be deposited over the entire base and emitter area using a directional deposition process. Since the sidewalls of the emitter mesa structure are under-cut, the emitter contact layer 205 creates a shadow which allows the base contact layer 206b to be deposited in close proximity to the emitter without touching it, except harmlessly on top of the emitter ohmic, 206a. In this fashion, conventional devices may achieve self alignment of base emitter junction connections thereby enhancing device performance by minimising base spreading resistance. A problem may be often encountered in the above process, however. The etching profile of the emitter mesa is determined by the crystalline structure of the emitter layers. This can cause the emitter to be etched differently in X and Y dimensions as shown in Figure 3.

The side view of the emitter mesa looking along the Y axis 301 shows etching profile 303. caused by the crystal orientation in this dimension. The emitter mesa is undercut on these sides with respect to the emitter contact. This creates a shadow during base contact 302 deposition which ensures separation 304 from the emitter mesa.

The side view of the same emitter mesa looking along the X axis 311 shows a different etching profile 313 caused by the crystal orientation. If the emitter contact bonds to the top surface well, it can prevent the mesa from being etched along the crystal plane originating from this point. This means that the sidewalls of the emitter mesa can protrude outside the perimeter of the emitter contact such that the base contact 312 comes into contact with the emitter mesa causing unwanted parasitic junctions 314 to form. These parasitic junctions may be a significant problem which limits device and circuit yields in the conventional

HBT fabrication.

Manufacturers of conventional HBTs may also experience problems in making connections to emitter contacts because they are vertically displaced from the insulating plane on which metal interconnects are deposited on the wafer, as shown in Figure 4.

In order to electrically isolate devices from each other on the above mentioned wafer, epitaxial layers are sometimes etched to form mesa structures on the underlying semi-insulating substrate which are physicaliy isolated from each other. This results in a structure similar to that shown in Figure 4a. Emitter mesa 401 rests on base-collector mesa 402 which in turn rests on semi-insulating substrate 403. Connections to the emitter ohmic contact 409 are made by metal deposited in the form of an arch 404. This arch structure may be formed as either an "air bridge" or as a similar structure supported by an underlying polymer (not shown). The arch is positioned to achieve a horizontal displacement from the wall of the transistor mesas to provide electrical isolation while spanning the vertical displacement from the emitter ohmic to the surface of the semi-insulating substrate. These connections can be partially unsupported 407 and fragile which may limit device fabrication yields.

Implantation may also be used to isolate transistors as shown in Figure 4b. Instead of etching away unwanted base-collector mesa layers, certain elements are implanted into redundant portions of the base and collector layers 418 to make them insulating. This reduces the vertical profile of the transistors and lessens the problems described above, but does not overcome them. Because the emitter interconnect metal 404 / 414 tends to be thick (e.g. 2- 3 microns) to strengthen the resulting structure, it is difficult to pattern this layer to form sub-micron-sized connections to the emitter ohmic 409 / 419. The emitter ohmic 409 / 419 also needs to be larger than the foot of the interconnect arch 404 / 414 to allow for possible alignment errors during fabrication. The emitter arch structure therefore sets a limit below which the emitter dimensions cannot be decreased. This limits device scaling to around 1 micron emitter widths and prevents improvement of transistor high frequency performance by making devices smaller. The complexity of the processes required to form the device mesas and surrounding ohmic and interconnect structures may be costly and may significantly compromise device and circuit fabrication yield. For example, circuits containing thousands of HBTs typically have less than 50% yield.

The performance of HBTs formed on GaAs substrates may also tend to be compromised by the relatively poor thermal conductivity of the substrate material, particularly in high power applications. Because of the poor thermal conductivity, device junction temperatures may rise and degrade parametric performance and reduce mean time to failure. It is therefore desirable to improve the thermal characteristics of HBT devices so that junction temperatures are lowered. Any discussion of documents, devices,, acts or knowledge in this specification is included to explain the context of the invention. It should not be taken as an admission that any of the material forms a part of the prior art base or the common general knowledge in the relevant art in Australia or elsewhere on or before the priority date of the disclosure and claims herein. SUMMARY OF INVENTION

An object of the present invention is to provide an improved integrated circuit device and manufacturing process.

A further object of the present invention is to alleviate at least one disadvantage associated with related art. According to the present invention, improved integrated circuits are provided.

In one aspect of the embodiments herein there is provided a method of fabricating a bipolar transistor for an integrated circuit comprising the steps of: providing a semiconductor substrate having a layered arrangement of semiconductor materials comprising, at least one subcollector region overlying one surface of the substrate, at least one collector layer overlying the subcollector region, at least one base layer overlying the collector layer and at least one emitter layer overlying the base layer; converting at feast one portion of the layered arrangement to an insulating state so as to form at least one isolated device region of the substrate; subsequently providing an emitter by selectively removing layers from the substrate to form a mesa structure extending from an active region of the device into the at least one converted portion; providing an ohmic contact for the emitter; connecting the emitter ohmic contact to at least one interconnecting metal layer disposed only in the at least one converted portion.

In another aspect of the embodiments herein there is provided a method of fabricating a bipolar transistor for an integrated circuit comprising the steps of: providing a semiconductor substrate having a layered arrangement of semiconductor materials comprising, at least one subcollector region overlying one surface of the substrate, at least one collector layer overlying the subcollector region, at least one base layer overlying the coflector layer and at least one emitter layer overlying the base layer; converting at least one portion of the layered arrangement to an insulating state so as to form at least one isolated device region of the substrate; subsequently providing an emitter by selectively removing layers from the substrate to form a mesa structure extending from an active region of the device into the at least one converted portion; annealing the at least one converted portion and a collector ohmic contact before an emitter ohmic contact is deposited.

In a further aspect of the embodiments herein there is provided a method of fabricating a bipolar transistor for an integrated circuit comprising the steps of: providing a semiconductor substrate having a layered arrangement of semiconductor materials comprising, at least one subcollector region overlying one surface of the substrate, at least one collector layer overlying the subcollector region, at least one base layer overlying the collector layer and at least one emitter layer overlying the base layer; forming at least one alignment mark for subsequent fabrication process steps for the bipolar transistor using ohmic contact metal, converting at least one portion of the layered arrangement to an insulating state so as to form at least one isolated device region of the substrate; annealing the at least one converted portion and the ohmic contact metal in a single heating operation.

In yet another aspect of the embodiments herein there is provided a method of fabricating a bipolar transistor for an integrated circuit comprising the steps of: providing a semiconductor substrate having a layered arrangement of semiconductor materials comprising, at least one subcollector region overlying one surface of the substrate, at least one collector layer overlying the subcollector region, at least one base layer overlying the collector layer and at least one emitter layer overlying the base layer; forming at least one alignment mark for subsequent fabrication process steps for the bipolar transistor using ohmic contact metal, converting at least one portion of the layered arrangement to an insulating state so as to form at least one isolated device region of the substrate; subsequently providing an emitter by selectively removing layers from the substrate to form a mesa structure extending from an active region of the device into the at least one converted portion.

In a further aspect of embodiments herein there is provided a method of fabricating an integrated circuit device comprising the steps of: converting at least one portion of a layered arrangement of semiconductor materials to an insulating state to form an isolation region and at least one isolated device bounded by the isolation region; subsequently providing at least one layer of material operatively associated with the isolated device and which extends across an isolation region boundary to form at least one region of overlap within the isolation; forming interconnect material over a portion of the at least one region of overlap to provide an electrical contact with the layer of material extending across the isolation boundary region wherein the layer of material forms part of an emitter mesa overlapped by the electrical contact within the isolation region such that the emitter mesa has a width substantially narrower than a corresponding width of the electrical contact; forming the interconnect material relatively thick compared to the height of at least the emitter mesa to form a substantially planar electrical contact. in still another aspect of embodiments herein there is provided a method of fabricating an integrated circuit device, the method comprising the steps of: forming a first alignment mark in a layered arrangement of semiconductor materials; converting, with reference to the first alignment mark, at least one portion of the layered arrangement of semiconductor materials to an insulating state to form an isolation region and at least one isolated device region bounded by the isolation region; forming a first layer of material with reference to the first alignment mark to provide a first device element and a second alignment mark spaced apart from the first .device element; forming a second layer of material with reference to the second alignment mark to provide a second device element. In another aspect of embodiments herein there is provided a method of fabricating an integrated circuit device comprising the steps of: converting at least one portion of a layered arrangement of semiconductor materials to an insulating state to form an isolation region and at least one isolated device region bounded by the isolation region; dissipating heat from the at least one isolated device region by forming interconnect material over at least a portion of the isolation region adjacent the isolated device region.

In a further aspect of embodiments herein there is provided a bipolar transistor device structure for an integrated circuit comprising: a semiconductor substrate having a layered arrangement of semiconductor material comprising, a subcoilector region overlying one surface of the substrate, at least one collector layer overlying the subcoilector region, at least one base layer overlying the collector layer and at least one emitter layer overlying the base layer; an active region of the device defined by a surrounding electrically isolating portion of the layered arrangement; the at least one emitter layer comprising an emitter having an emitter mesa structure which extends outside of the active region and into the isolating portion, and; an emitter ohmic contact metal connected to at least one interconnecting metal layer disposed only in the isolating portion. . In still another aspect of embodiments herein there is provided an integrated circuit device structure comprising: at least one portion of a layered arrangement of semiconductor materials converted to an insulating state to form an isolation region and at least one isolated device bounded by the isolation region; at least one layer of material operatively associated with the isolated device and which extends across an isolation region boundary to form at least one region of overlap within the isolation region; interconnect material formed over a portion of the at least one region of overlap to provide an electrical contact with the layer of material extending across the isolation boundary, wherein the iayer of material forms part of an emitter mesa overlapped by the electrical contact within the isolation region such that the emitter mesa has a width substantially narrower than a corresponding width of the electrical contact; wherein the interconnect material is formed relatively thick compared to the height of at least the emitter mesa to form a substantially planar electrical contact. In yet a further aspect of embodiments herein there is provided an integrated circuit device, comprising: a first alignment mark in a layered arrangement of semiconductor materials; at least one portion of the layered arrangement of semiconductor materials converted, with reference to the first alignment mark, to an insulating state to form an isolation region and at least one isolated device region bounded by the isolation region; a first layer of material formed with reference to the first alignment mark to provide a first device element and a second alignment mark spaced apart from the first device element; a second layer of material formed with reference to the second alignment mark to provide a second device element.

In yet another aspect of embodiments herein there is provided an integrated circuit device comprising: at least one portion of a layered arrangement of semiconductor materials converted to an insulating state to form an isolation region and at least one isolated device region bounded by the isolation region; at least one heat spreader for dissipating heat from the at least one isolated device region comprising interconnect material formed over at least a portion of the isolation region adjacent the isolated device region,

In particular aspects of embodiments herein there is provided apparatus adapted for manufacturing semiconductor devices, said apparatus comprising: processor means adapted to operate in accordance with a predetermined instruction set, said apparatus, in conjunction with said instruction set, being adapted to perform the method steps as described herein. It is also envisaged that embodiments of the present invention reside in a computer program product comprising: a computer useable medium having computer readable program code and computer readable system code embodied on said medium, for manufacturing semiconductor devices, within a data processing system, said computer program product comprising: computer readable code within said computer usable medium for performing the method steps as described herein.

In essence the present invention stems from the realisation that modifications to initial fabrication process steps lead to embodiments of the present invention providing for improved precision of device alignment, reduced emitter widths for improved performance and enlarged metal interconnects for circuit connectivity and heat dissipation. Other aspects and preferred aspects are disclosed in the specification and/or defined in the appended claims, forming a part of the description of the invention.

Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments, of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

Further disclosure, objects, advantages and aspects of the present invention may be better understood by those skilled in the relevant art by reference to the following description of preferred embodiments taken in conjunction with the accompanying drawings, which are given by way of illustration only, and thus are not limitative of the present invention, and in which: Figure 1 is a simplified diagram of a related art HBT device structure; Figure 2 is a simplified diagram of a npn GaAs/lnGaP related art HBT device;

Figure 3 is a simplified diagram of a related art emitter mesa etching profile;

Figures 4a and 4b are simplified diagrams of related art HBT structures with implant isolation;

Figure 5 is a comparison of an example related art isolation implanted HBTs and one embodiment of the present invention; Figure 6 shows a preferred connection between an emitter mesa and an interconnect meta! in accordance with an embodiment of the present invention;

Figure 7 shows a side view of a preferred connection between an emitter mesa and an interconnect metal in accordance with an embodiment of the present invention; Figure 8 shows a plan view of the preferred patterning of base ohmic metal around an emitter mesa in accordance with an embodiment of the present invention; Figure 9 shows a simplified lithographic alignment mark in accordance with a preferred embodiment of the present invention;

Figures 10a through 1Oe show a preferred fabrication method in accordance with embodiments of the present invention; Figure 11 shows exemplary collector metalisation used for heat spreading in accordance with a preferred embodiment of the present invention. DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that structural, material and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.

According to a preferred embodiment of the present invention, improved integrated circuits are provided. More particularly, the invention provides a method and structure for a high performance heterojunction bipolar transistor which is suited to compound semiconductor material systems such as gallium arsenide and which preferably utilises ion implantation at the beginning of the fabrication sequence to define the perimeter of the device thereby electrically isolating the HBT from surrounding semiconductor structures on the wafer.

Further details of the present invention can be found throughout the present specification and more particularly below.

The present invention preferably uses compound semiconductor wafers with emitter, base, collector and sub-collector layers, similar to those as shown in Figure 1. However the present invention differs, in at least one preferred aspect, from related art in the way these layers are patterned. In conventional devices as shown in Figure 2, the emitter layer structure is patterned first to form an emitter mesa structure 200. This patterning is performed using either standard gaseous dry etching or aqueous wet etching techniques. The size of the emitter mesa is determined by a material which is impervious to the etching process and which is deposited on the surface of the wafer and patterned by photofithography. This material may be photoresist or a composite metal layer 205 that forms the emitter ohmic contact of the device.

In conventional HBTs that are isolated by etching away all active device layers, the base, collector and subcollector are patterned in a similar fashion.

In conventional devices that are isolated using ion implantation, the base and collector layers are not etched away. Instead they are rendered insulating by exposure to high energy ions such as oxygen, hydrogen or helium.

Figure 5a shows the plan view of a related art ion implant isolated HBT. The emitter region 501 is patterned so it is smaller than the base region 502 which is smaller than the subcoilector region 503 which is surrounded by implanted regions 504 forming an isolation implant boundary 505.

Figure 5b shows equivalent emitter 511, base 512, subcollector 513 implanted regions 514 and implant boundary 515 of a preferred embodiment of the present invention. However, in embodiments of the present invention, the feature which forms the emitter mesa 511 is deposited after isolation implantation has taken place and extends outside the isolation implant boundary 515 forming regions of overlap 516. An advantage of the present invention is that metal which is used to connect the emitter to other circuit elements can be deposited on the ends of the emitter ohmic contact in the implanted areas.

Figure 6 shows a plan view of a substrate where emitter ohmic metal 611 extends into implant isolated regions of the device 616. In this area, interconnect metal 618 is deposited over the emitter ohmic metal 611 and creates an electrical contact region 617. Figure 7 shows a side view of this same area. Emitter ohmic 711 extends into the implant isolated region 717 where interconnect metal 718 is deposited on top of it. An important advantage of the present invention is that the emitter width (i.e. the narrower dimension of the emitter) can be made very small which increases the operating frequency of the transistor. The inventor has recognised that, in conventional transistors, the contact area between interconnect metal and emitter ohmic needs to be located within the area of the emitter ohmic and this prevents the emitter width being narrowed. In a preferred embodiment of the present invention, the interconnect metal can overlap the emitter ohmic without restriction, because it rests on insulating semiconductor material. By this means, emitter widths of the present invention can be readily reduced below about 1 micron, whereas conventional transistors are normally restricted to emitter widths of about 1 micron or more.

In accordance with a further embodiment, the present invention also includes a means of depositing base ohmic metal on the transistor in a self aligned manner. In conventional transistors, the emitter mesa is formed first in the fabrication sequence. It is intentionally- aligned with the crystal axis of the wafer which produces an undercut shape 303 during etching as shown in Figure 3. This allows base ohmjc metal to be deposited over both the base and emitter regions to form a self aligned base contact. The overhang of the emitter mesa caused by undercut etching creates a shadow during the base ohmic deposition so that it does not form a continuous metallic layer. Such a layer may introduce a short circuit between the base and emitter and render the device inoperative. Accordingly, there is potentially a problem with the self aligned base ohmic contact in related art. Although the emitter produces undercut sidewalls during etching along one crystal axis of the wafer, it produces the opposite "overcut" etch profile 313 along the orthogonal axis, as again shown in Figure 3. When base ohmic metal is deposited over the emitter to form a self aligned contact, there is a significant risk of base-emitter short circuits 314 at this point. A preferred embodiment of the present invention provides a means of avoiding this problem by patterning the base ohmic iayer so that it is separated from the overcut ends of the emitter mesa. Figure 8 shows one possible design of the base ohmic layer which achieves self alignment along the side edges 832 of the emitter mesa 811 and comprises a region 831 where the base ohmic is separated from the ends of the emitter mesa 811 lithographically. As portions of the semiconductor device layers have been rendered insulating by the implant process, a relatively large area 834 can be used to form these base and emitter contact features using lithographic processes without creating parasitic semiconductor junctions underneath that would significantly degrade device performance. This couid not be achieved in conventional processes where isolation implant is performed after the emitter ohmic layer is deposited.

Another advantage of this embodiment of the present invention is that the vertical topology of the surface of the wafer is reduced providing a substantially- planar surface on which interconnect metal is deposited. This results in very high fabrication yield because the possibility of interconnect metal or ohmic metal creating short circuits or parasitic junctions is significantly minimised. Typically this substantially-planar surface would be the plane 730 corresponding to the surface of the base layer as shown in Figure 7. Provided interconnect metal 718 is relatively thick compared to the height of the emitter mesa 711 a substantially planar connection is achieved. This interconnect metal corresponds to 818 in Figure 8. Because there are no restrictions on the width of interconnect metal 718 / 818 it can be made relatively wide and hence relatively thick by common lithographic techniques.

In a similar fashion, base interconnect metal 836 can be made relatively wide and thick without degrading device yield or performance. Preferably a single interconnect metal is used for both emitter interconnect 818 and base interconnect 836. This may typically be the first layer of interconnect metal deposited on the wafer which is known as "first metal".

In semiconductor manufacturing processes, there is a need for alignment marks which serve as a reference point for each photolithography exposure step. These alignment marks 901 in Figure 9 are created during the first process step and in a conventional process might be formed by deposition of the emitter ohmic metai. Alternatively, the. alignment mark might be formed from another feature which has no other function except to serve as an alignment mark. However it is attractive to combine the process step of alignment mark creation with another process step in order to reduce process complexity and cost.

After creation of the alignment marks, which may sometimes be referred to as fiducial marks, subsequent photolithography steps use features on the respective mask plate 902 to align the mask to the alignment mark 901. The alignment mark shown in Figure 9 is simplistic for descriptive purposes and is typically more complex in conventional processes. In accordance with a preferred embodiment, the present invention utilises ion implantation prior to formation of the emitter feature of the device. Hence, there is a need to align the emitter to regions which have not been implanted. In general, implantation does not leave clearly visible indication which differentiates implanted regions from non- implanted regions. Hence in accordance with a preferred embodiment there is provided a means of providing an alignment reference that both the implant process and emitter process are aligned to. In order to simplify the process and reduce cost, this alignment mark is combined with another feature of the resulting transistor- the collector ohmic contact 840 as shown in Figure 8. An overall manufacturing sequence in accordance with a preferred embodiment of the present invention is shown in Figure 10;

Firstly, photoresist is deposited onto the wafer surface and exposed using the collector ohmic mask to open windows 1040 and 1050, as shown in figure 10a. Then the semiconductor layers are etched down to the surface of the subcollector layer in these windows. Then with the photoresist still in place, collector ohmic metaf is deposited over the entire surface of the wafer. The photoresist is then dissolved and lifts-off excess collector ohmic metal, leaving metal only in regions 1040 and 1050. Region 1050 is intended as an alignment feature for the following implant step. Then, photoresist is deposited over the wafer surface and exposed using the implant mask whfch is aligned to feature 1050. As shown in figure 10b, photoresist is then developed to remove photoresist everywhere except in region 1015. Then the wafer is exposed to high energy ions which deliberately damage the exposed crystal lattice and render it insulating. The photoresist in region 1015 protects the semiconductor layers from implantation. The implanted ions are preferably helium, hydrogen or oxygen but can be any element that may render it insulating.

Then, the wafer is heated to activate the collector ohmic contact so that it forms a low resistance ohmic contact to the subcollector layer. This process is known as alloying or annealing and would be understood by the person skilled in the art. Annealing temperatures are typically between 200 and 400 degrees Celsius. During this same heating step, the isolation implant is annealed to maximise crystal damage in implanted areas, thereby increasing resistivity to a maximum value and optimising its performance as an insulating medium. in a preferred embodiment of the present invention, it is advantageous to perform this heating early in the process sequence so that heat stress is minimised on device features that do not require alloying or annealing. As noted, most preferably, annealing the isolation implant {or converted portion) and the ohmic contact metal is performed in a single heating operation at this stage. Then, preferably only after annealing, the wafer is coated with another layer of photoresist and exposed using the emitter mask. With reference to figure 10c, this mask is again positioned relative to alignment mark 1050. The photoresist is developed so it is removed from regions 1011 and 1051. Region 1011 is the emitter feature of the transistor and 1051 is a new alignment mark that may be used for subsequent mask exposures. Although alignment mark

1050 is adequate for alignment of large scale features such as collector contact 1040 and implant region 1014, in general it is not optima! for mask exposure of the base layer which may require sub-micron alignment accuracy. The reason for this is because it is positioned at the bottom of an etch feature creating depth of field issues during lithography and the metaf is relatively thick which means it has relatively poor accuracy with respect to the X/Y plane. In addressing this, feature

1051 is created with a high precision process which is capable of producing an accurate alignment reference for the base layer lithography. Then emitter metal is deposited over the wafer surface and lifted off to leave the emitter ohmic contact in region 1011 and alignment mark 1051. This metal layer, as would be recognised by the person skilled in the art, may typically comprise Ti / Pt / Au and is resistant to etchants used to form the emitter layer.

Thereafter the emitter layers are etched away from the surface of the wafer in regions not protected by the emitter ohmic contact or the alignment mark. This etch is normally an aqueous "wet" etch process that involves selective removal of emitter layers such that the etch stops precisely at the surface of the base layer of , the device. This etching process would be known and recognised by the person skilled in the art and produces an undercut profile on the sides of the emitter mesa. The emitter ohmic contact extends beyond the boundary of the implanted region into regions which have been implanted. For example the emitter may extend 5 microns into this region.

With reference to figure 10d the wafer is then coated with more photoresist and patterned with the base ohmic contact mask. This mask is preferably aligned to the emitter alignment mark made in the previous step. The photoresist is then developed to open holes where base ohmic 1030 is to be deposited onto the wafer and the excess is lifted off. As would be recognised by the person skilled in the art, there are many different base όhmic contacts comprising for example Pt / Ti / Pt / Au. The base ohmic 1030 may be deposited over both base and emitter 1033 areas to form a self aligned base-emitter junction. In this case the base ohmic 1030 covers the emitter area 1033 and is self aligned to the edges of the emitter 1032. Alternatively, the base ohmic 1030 can be separated from the emitter by separating the deposition areas laterally from the edges of the emitter and leaving the emitter area 1033 covered with photoresist.

In accordance with a preferred embodiment of the present invention, when base ohmic metal is deposited in a self aligned manner, it is specifically not deposited in the region surrounding the end of the emitter ohmic 1011. This creates areas where base ohmic metal is separated from the edges of the emitter mesa 1031 where there is a chance that it might short to the ends of the emitter mesa which may have an "overcut" profile as previously described.

Next with reference to figure 10e, the wafer is covered with photoresist and patterned with the first interconnect metal mask to open windows in the photoresist corresponding to areas 1018, 1036 and 1060. This mask is preferably aligned to the emitter alignment mark 1051. Interconnect metal is then deposited over the .wafer and lifted off to leave metal in regions 1018, 1036 and 1060. This metal is preferably one or a combination of Ti / Pt / Au and forms contacts to the emitter, base and collector in overlap regions 1017, 1035 and 1061 respectively. This interconnect metal is thicker than the height of the emitter mesa and, as such, forms a substantially-planar interconnect layer. The preferred thickness is in the range of about 0.5 to 1 micron.

Following this, fabrication process steps as applied in conventional processes may be used to form other circuit elements such as resistors, capacitors, or diodes, for example, and additional metal interconnect layers.

In another preferred embodiment, the present invention provides a transistor with improved heat dissipation characteristics. Typically collector ohmic metal and first interconnect metal are predominantly made from gold which is a relatively good thermal conductor. In accordance with a particularly preferred embodiment of the present invention, the collector ohmic contacts of the transistor can be increased in size to laterally spread heat generated in the central part of the transistor, thereby coupling and transferring this heat away from the transistor. In preferred embodiments, the collector ohmic metal and first interconnect metals, in combination, may form a heat spreading region for the device. Preferably, a combination comprising one, two, or more of the following materials may be used to form the heat spreading region: gold AU; nickel Ni; aluminium Ai; copper Cu. Other materials as would be recognised by the person skilled in the art may also be suitable to add to this combination contact. Figure 11 shows one possible implementation of the heat spreading concept where the collector ohmic contacts 1161 and collector interconnect metal 1160 are expanded to achieve heat spreading.

A person skilled in the art will recognise that embodiments of the invention described herein may be implemented using one or more computers. !n that case, the method steps disclosed herein may be embodied as instructions that comprise a computer program. The program may be stored on computer- readable media, such as floppy disks, optical discs (eg compact discs), or fixed disks (such as hard drives and the like), and may be resident in memory, such as, for example random access memory (RAM), read-only memory (ROM), firmware, or flash RAM memory. The program as software may then be executed on a computer or microprocessor device to implement the method. The program or portions of its execution, may also be distributed over multiple computers in a network having a topology corresponding to one or a combination of; a small area such as in a LAN (Local Area Network); a large campus or city area such as in a MAN (Metropolitan Area Network) or; a wide geographical area such as in a WAN (Wide Area Network). As an example, the present invention may be suitable for use with a computer network implementation of a manufacturing system within a semiconductor fabrication facility. While this invention has been described in connection with specific embodiments thereof, it will be understood that it is capable of further modification(s). This application is intended to cover any variations uses or adaptations of the invention following in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains and as may be applied to the essential features hereinbefore set forth.

As the present invention may be embodied in several forms without departing from the spirit of the essential characteristics of the invention, it should be understood that the above described embodiments are not to limit the present invention unless otherwise specified, but rather should be construed broadly within the spirit and scope of the invention as defined in the appended claims. Various modifications and equivalent arrangements are intended to be included within the spirit and scope of the invention and appended claims. Therefore, the specific embodiments are to be understood to be illustrative of the many ways in which the principles of the present invention may be practiced. In the following claims, means-pJus-function clauses are intended to cover structures as performing the defined function and not only structural equivalents, but also equivalent structures. For example, although a nail and a screw may not be structural equivalents in that a nail employs a cylindrical surface to secure wooden parts together, whereas a screw employs a helical surface to secure wooden parts together, in the environment of fastening wooden parts, a nail and a screw are equivalent structures. "Comprises/comprising" when used in this specification is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof." Thus, unless the context clearly requires otherwise, throughout the description and the claims, the words 'comprise', 'comprising', and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in the sense of "including, but not limited to".

Claims

1. A method of fabricating a bipolar transistor for an integrated circuit comprising the steps of: providing a semiconductor substrate having a layered arrangement of semiconductor materials comprising, at least one subcoliector region overlying one surface of the substrate, at least one collector layer overlying the subcoliector region, at least one base layer overlying the collector layer and at least one emitter layer overlying the base layer; converting at least one portion of the layered arrangement to an insulating state so as to form at least one isolated device region of the substrate; subsequently providing an emitter by selectively removing layers from the substrate to form a mesa structure extending from an active region of the device into the at least one converted portion; providing an ohmic contact for the emitter; connecting the emitter ohmic contact to at least one interconnecting metal layer disposed only in the at least one converted portion.

2. A method as claimed in claim 1 wherein the thickness of the at least one interconnecting metal layer is greater than the emitter mesa height.

3. A method of fabricating a bipolar transistor for an integrated circuit comprising the steps of: providing a semiconductor substrate having a layered arrangement of semiconductor materials comprising, at least one subcolfector region overlying one surface of the substrate, at least one collector layer overlying the subcoliector region, at ieast one base layer overiying the collector layer and at least one emitter layer overlying the base layer; converting at least one portion of the layered arrangement to an insulating state so as to form at least one isolated device region of the substrate; subsequently providing an emitter by selectively removing layers from the substrate to form a mesa structure extending from an active region of the device into the at least one converted portion; annealing the at least one converted portion and a collector ohmic contact before an emitter ohmic contact is deposited.

4. A method of fabricating a bipolar transistor for an integrated circuit comprising the steps of: providing a semiconductor substrate having a layered arrangement of semiconductor materials comprising, at least one subcollector region overlying one surface of the substrate, at least one collector layer overlying the subcollector region, at least one base layer overlying the collector layer and at least one emitter layer overlying the base layer; forming at least one alignment mark for subsequent fabrication process steps for the bipolar transistor using ohmic contact metal, converting at least one portion of the layered arrangement to an insulating state so as to form at least one isolated device region of the substrate; annealing the at least one converted portion and the ohmic contact metal in a single heating operation.

5. A method as claimed in claim 4 wherein the step of annealing is performed before any portion of an emitter of the transistor is formed.

6. A method of fabricating a bipolar transistor for an integrated circuit comprising the steps of: providing a semiconductor substrate having a layered arrangement of semiconductor materials comprising, at least one subcollector region overlying one surface of the substrate, at least one collector layer overlying the subcollector region, at least one base layer overlying the collector layer and at least one emitter layer overlying the base layer; forming at least one alignment mark for subsequent fabrication process steps for the bipolar transistor using ohmic contact metal, converting at least one portion of the layered arrangement to an insulating state so as to form at least one isolated device region of the substrate; subsequently providing an emitter by selectively removing layers from the substrate to form a mesa structure extending from an active region of the device into the at least one converted portion.

7. A method as claimed in claim 6 wherein the step of forming at least one alignment mark comprises using collector . oh mic metal to form at least one alignment mark for one or more of the following process steps: the step of converting as claimed in claim 4; emitter mesa formation by photolithography; emitter ohmic contact formation by photolithography.

8. A method as claimed in claim 6 or 7 further comprising the step of: using an emitter ohmic contact layer to form at least one alignment mark for subsequent fabrication process steps which comprise at least the step of forming a base ohmic contact.

9. A method as claimed in any one of the previous claims further comprising the step of: depositing collector ohmic metal and collector interconnect metal to form an overlapping region adjacent the isolated device region for dissipating heat in the substrate.

10. A method as claimed in claim 9 wherein the overlapping region is at least about 4 times the area of the transistor's subcollector area.

11. A method of fabricating an integrated circuit device comprising the steps of: converting at least one portion of a layered arrangement of semiconductor materials to an insulating state to form an isolation region and at least one isolated device bounded by the isolation region; subsequently providing at least one layer of material operatively associated with the isolated device and which extends across an isolation region boundary to form at least one region of overlap within the isolation; forming interconnect materia! over a portion of the at least one region of overfap to provide an electrical contact with the layer of material extending across the isolation boundary region wherein the layer of material forms^' part of an emitter mesa overlapped by the electrical contact within the isolation region such that the emitter mesa has a width substantially narrower than a corresponding width of the electrical contact; forming the interconnect material relatively thick compared to the height of at least the emitter mesa to form a substantially planar electrical contact.

ι 12. A method as claimed in claim 11 wherein the emitter mesa has a width of less than about 1 μm.

13. A method as claimed in claim 11 or 12 wherein the at least one layer of material operatively associated with the isolated device comprises one or a combination of: emitter ohmic materia!; base ohmic material.

14. A method as claimed in any one of claims 11 , 12 or 13 wherein the interconnect material comprises first metal.

15. A method of fabricating an integrated circuit device, the method comprising the steps of: forming a first alignment mark in a layered arrangement of semiconductor materials; converting, with reference to the first alignment mark, at (east one portion of the layered arrangement of semiconductor materials to an insulating state to form an isolation region and at feast one isolated device region bounded by the isolation region; forming a first layer of material with reference to the first alignment mark to provide a first device element and a second alignment mark spaced apart from the first device element; forming a second layer of material with reference to the second alignment mark to provide a second device element.

16. A method as claimed in claim 15 further comprising the step of forming the second alignment mark at reduced thickness in comparison to the first alignment mark to allow relatively precise positioning of the device elements.

17. A method as claimed in claim 15 or 16 wherein the first device element comprises at least part of an emitter structure.

18. A method as claimed in claim 15, 16 or 17 wherein the second device element comprises base ohmic material.

19. A method as claimed in any one of claims 15 to 18 further comprising the step of: forming interconnect material over at least one of the first and second device elements to provide at least one electrical contact within the isolation region.

20. A method as claimed in any one of claims 15 to 19 wherein the step of converting is followed by the step of: annealing the layered arrangement of semiconductor materials before the step of forming a first layer of material with reference to the first alignment mark.

21. A method of fabricating an integrated circuit device comprising the steps of: converting at least one portion of a layered arrangement of semiconductor materials to an insulating state to form an isolation region and at least one isolated device region bounded by the isolation region; dissipating heat from the at least one isolated device region by forming interconnect material over at least a portion of the isolation region adjacent the isolated device region.

22. A method as claimed in claim 21 wherein the Interconnect materia! forms a heat sink region sized to provide a relatively large surface area.

23. A method as claimed in any one of the previous claims wherein the step of converting comprises an ion implantation process.

24. A method as claimed in claim 23 wherein the ion implantation process utilizes ions comprising one or more of:

Helium; Hydrogen;

Oxygen.

24. A method as claimed in any one of the previous claims wherein the step of converting comprises increasing the resistivity of the at least one portion of the layered arrangement by a factor of at least about 100 compared to the resistivity prior to the step of converting.

26. A method as claimed in any one of claims 1 to 14 wherein the step of subsequently forming an emitter structure comprises one or more of: a photolithography process; a etch process.

27. A method as claimed in any one of claims 1 to 26 further comprising the step of depositing collector ohmic contact metal on the layered arrangement before the step of converting.

28. A method as claimed in any one of the previous claims wherein the semiconductor materials of the layered arrangement comprise one or more compound semiconductor materials.

29. A method as claimed in any one of the previous claims wherein the emitter layer comprises one or more compound semiconductor materials.

30. A method as claimed in claim 28 or 29 wherein the compound semiconductor materials comprise one or a combination of:

GaAs;

InGaAs; InGaP;

AIGaAs;

InP;

AIAs.

31. A method as claimed in any one of the previous claims wherein one or more fabrication steps comprise a photolithography process.

32. A method as claimed in any one of claims 1 to 31 wherein the device comprises one or a combination of: a heterojunction bipolar transistor; a resistor; a capacitor; a diode.

33. A method as claimed in any one of claims 1 , 2, 9 to 14 or 19 to 32 wherein the interconnect material comprises one or a combination of: gold; nickel; aluminium; copper;

34. A bipolar transistor device structure for an integrated circuit comprising: a semiconductor substrate having a layered arrangement of semiconductor material comprising, a subcollector region overlying one surface of the substrate, at least one coilector layer overlying the subcollector region, at least one base layer overlying the collector layer and at least one emitter layer overlying the base

^■ layer; an active region of the device defined by a surrounding electrically isolating portion of the layered arrangement; the at least one emitter layer comprising an emitter having an emitter mesa structure which extends outside of the active region and into the isolating portion, and; an emitter ohmic contact metal connected to at least one interconnecting meta! layer disposed only in the isolating portion.

35. A structure as claimed in claim 34 wherein the resistivity of the at least one electrically isolating portion is increased by a factor of at least about 100 compared to the resistivity of the active region.

36. A structure as claimed in claim 34 or 35 wherein the thickness of the at least one interconnecting metal layer is greater than the emitter mesa height.

37. A structure as claimed in claim 34, 35 or 36 wherein a width of the emitter in the plane of the layered arrangement is substantially less than about 1 μm.

38. A structure as claimed in any one of claims 34 to 37 further comprising a collector ohmic metal and collector interconnect metal overlapping adjacent the active region of the device and adapted to form a heat spreading region.

39. A integrated circuit device structure comprising: at least one portion of a layered arrangement of semiconductor materials converted to an insulating state to form an isolation region and at least one isolated device bounded by the isolation region; at least one layer of material operatively associated with the isolated device and which extends across an isolation region boundary to form at least one region of overlap within the isolation region; interconnect material formed over a portion of the at least one region of overlap to provide an electrical contact with the layer of material extending across the isolation boundary, wherein the layer of material forms part of an emitter mesa overlapped by the electrical contact within the isolation region such that the emitter mesa has a width substantially narrower than a corresponding width of the electrical contact; wherein the interconnect material is formed relatively thick compared to the height of at least the emitter mesa to form a substantially planar electrical contact.

40. A structure as claimed in claim 39 wherein the emitter mesa has a width of less than about 1 μm.

41. A structure as claimed in claim 39 or 40 wherein the at least one layer of material operatively associated with the isolated device comprises one or a combination of: emitter ohmic material; base ohmic material.

42. A structure as claimed in any one of claims 39 to 41 wherein the interconnect material comprises first metal.

43. An integrated circuit device, comprising: a first alignment mark in a layered arrangement of semiconductor materials; at least one portion of the layered arrangement of semiconductor materials converted, with reference to the first alignment mark, to an insulating state to form an isolation region and at least one isolated device region bounded by the isolation region; a first layer of material formed with reference to the first alignment mark to provide a first device element and a second alignment mark spaced apart from the first device element; a second layer of material formed with reference to the second alignment mark to provide a second device element.

44. A device as claimed in claim 43 wherein the second alignment mark is formed at reduced thickness in comparison to the first alignment mark to allow relatively precise positioning of the device elements.

45. A device as claimed in claim 43 or 44 wherein the first device element comprises at least part of an emitter mesa.

46. A device as claimed in claim 43, 44 or 45 wherein the second device element comprises base ohmic material.

47. A device as claimed in any one of claims 43 to 46 further comprising: interconnect material formed over at least one of the first and second device elements to provide at least one electrical contact within the isolation region,

48. An integrated circuit device comprising: at least one portion of a layered arrangement of semiconductor materials converted to an insulating state to form an isolation region and at least one isolated device region bounded by the isolation region; at least one heat spreader for dissipating heat from the at least one isolated device region comprising interconnect material formed over at least a portion of the isolation region adjacent the isolated device region.

49. A device as claimed in claim 48 wherein the interconnect material forms a heat spreading region sized to provide a relatively large surface area.

50. A device^' as claimed in claim 49 wherein the heat spreading region is positioned over and at least about 4 times the area of a subcoilector region of the isolated device region.

51. A structure as claimed in claim 49 or 50 wherein the heat spreading region comprises one or more of: gold; nickel; aluminium copper.

52. A structure or device as claimed in any one of claims 34 to 38, 39 to 42 and 47 to 51 wherein the interconnect material comprises a thickness in the range of about 0.5 to about 1 μm.

53. A structure or device as claimed in any one of claims 34 to 52 wherein the layered semiconductor material comprises one or more compound semiconductor materials.

54. A structure or device as claimed in any one of claims 34 to 42 or 45 wherein the emitter comprises one or more compound semiconductor materials.

55. A structure or device as claimed in claim 53or 54wherein the compound semiconductor material comprises at least one or more of:

GaAs; InGaAs;

InGaP; AIGaAs.

56 A structure or device as claimed in any one of claims 34 to 55 wherein the semiconductor device comprises at least one or a combination of: a HBT transistor device; a resistor; a capacitor; a diode.

57. Apparatus adapted for manufacturing semiconductor devices, said apparatus comprising: processor means adapted to operate in accordance with a predetermined instruction set, said apparatus, in conjunction with said instruction set, being adapted to perform the method steps of any one of claims 1 to 33.

58. A computer program product comprising: a computer useabfe medium having computer readable program code and computer readable system code embodied on said medium, for manufacturing semiconductor devices, within a data processing system, said computer program product comprising: computer readable code within said computer usable medium for performing the method steps of any one of claims 1 to 33.

59. A method substantially as herein described with reference to at least one of the accompanying drawings.

60. An apparatus, device, substrate, article or assembly substantially as herein described with reference to at least one of the accompanying drawings.