CN113921598B - Metal wiring method of HBT device - Google Patents
Metal wiring method of HBT device Download PDFInfo
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- CN113921598B CN113921598B CN202110983574.5A CN202110983574A CN113921598B CN 113921598 B CN113921598 B CN 113921598B CN 202110983574 A CN202110983574 A CN 202110983574A CN 113921598 B CN113921598 B CN 113921598B
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- 239000002184 metal Substances 0.000 title claims abstract description 76
- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000001039 wet etching Methods 0.000 claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- 238000001883 metal evaporation Methods 0.000 claims abstract description 7
- 238000000407 epitaxy Methods 0.000 claims description 15
- 239000010953 base metal Substances 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 6
- 238000005566 electron beam evaporation Methods 0.000 claims description 3
- 238000001017 electron-beam sputter deposition Methods 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 2
- 238000011161 development Methods 0.000 abstract description 5
- 238000013461 design Methods 0.000 description 15
- 239000004065 semiconductor Substances 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 239000002131 composite material Substances 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 101100011794 Caenorhabditis elegans epi-1 gene Proteins 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000013043 chemical agent Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42304—Base electrodes for bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
- H01L29/66318—Heterojunction transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
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- Ceramic Engineering (AREA)
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- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
The invention discloses a metal connecting method of an HBT device, which comprises the steps of changing the shape structure of a first photomask corresponding to a base step and the shape structure of a second photomask corresponding to a connecting metal layer, forming a shielding layer corresponding to a first photomask pattern on a wafer structure of which the manufacturing process of the device is completed after exposure and development, then performing wet etching to form the base step, forming a display window corresponding to the second photomask pattern after exposure and development by adopting the second photomask, and performing metal evaporation on the display window to form the connecting metal layer connected with the base step. The base electrode step and the connecting wire metal layer manufactured by the method can enable the HBT device to be placed in different directions under the condition that the manufacturing process condition is not changed, and can prevent the connecting wire metal layer from generating cracks or fractures at the edge of the base electrode step.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a metal wiring method of an HBT device.
Background
The III-V compound semiconductor Heterojunction Bipolar Transistor (HBT) is used as a third-generation semiconductor material and a device, the design principle is that the distribution and flow of carriers are controlled by utilizing the change of the forbidden band width of a semiconductor and the action of the semiconductor and the electric field force on electrons and holes, and the III-V compound semiconductor heterojunction bipolar transistor has the characteristics of high power density, low phase noise, good linearity and the like, and is widely applied to the fields of microwave oscillators, low-noise amplifiers, power amplifiers, signal mixers, frequency dividers and the like.
The HBT comprises an emitter region, a base region and a collector region which are made of materials with different forbidden bandwidths, a heterojunction is formed between semiconductor materials with different forbidden bandwidths, a large number of interface states exist on the surface of the base region in the process that electron current is injected from the emitter region to the collector region through the base region, and when the current stays on the surface of the base region, electrons and holes are combined to form composite current. The composite current is the main current component affecting the current gain, so that the composite current can be effectively reduced and the current gain can be improved by selecting proper material structure parameters. The fabrication method of the HBT is mainly an epitaxial process. For the Emitter Mesa (EM) and base step BP Pedistal (BP) processes in HBTs, chemical etching is mostly used. However, the chemical corrosion has selectivity to the crystal orientation, so the design of the device is limited by the directionality of the metal wire, and the chemical corrosion and lateral corrosion are excessive, so the stability of the process is not easy to control, and the electrical performance and the stability of the device and the reliability of the device are further influenced.
Particularly, when the base step is manufactured by a wet etching process, the isotropy of the chemical agent causes a phenomenon of concave in one direction, so that the wire metal is easy to crack or break when running in the direction, and the HBT device can only be placed in the other direction during design, so that the degree of freedom of product design is reduced.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a metal wiring method of an HBT device.
In order to achieve the above object, the technical scheme of the present invention is as follows:
a method of metal wiring of an HBT device comprising the steps of:
1) Providing or forming a wafer structure with a part of finished device manufacturing process, wherein the wafer structure comprises a base epitaxy, an emitter platform and base metal, and the emitter platform and the base metal are arranged on the base epitaxy;
2) Providing a first photomask, wherein the first photomask pattern comprises a preset part matched with a preset base electrode step pattern and a connecting line part formed by extending the preset part towards the connecting line direction;
3) Forming a first photoresist layer on the surface of the wafer structure, exposing and developing by adopting the first photomask to form a shielding layer corresponding to the first photomask pattern, and performing wet etching on the base epitaxy to form a base step;
4) Providing a second photomask, wherein the second photomask pattern comprises a first connecting wire part covering a base electrode step corresponding to the connecting wire part and a second connecting wire part formed by extending the first connecting wire part towards the leading-out direction;
5) And forming a second photoresist layer on the surface of the wafer structure, exposing and developing by adopting the second photomask to form an open window corresponding to the second photomask pattern, and evaporating metal on the open window to form a connecting line metal layer connected with the base electrode step.
In an alternative embodiment, the connection metal layer covers the base step formed correspondingly on the connection part.
In an alternative embodiment, the minimum dimension of the wire portion is 2.0 μm in length and 2.0 μm in width.
In an alternative embodiment, the edge of the base step correspondingly formed by the wire connection portion exceeds the edge of the wire connection metal layer correspondingly formed by the first wire connection portion by at least 0.3 μm.
In an alternative embodiment, the emitter platform comprises a first emitter platform and a second emitter platform, the first emitter platform and the second emitter platform are vertically arranged, the second emitter platform is located in the middle of the base step, and the base metal is arranged on two sides of the second emitter platform.
In an alternative embodiment, the link metal layer extends over the base step and overlies a portion of the first emitter mesa.
In an alternative embodiment, step 3 further comprises a step of stripping the masking layer after performing the wet etching.
In an alternative embodiment, step 5 further includes a step of stripping the remaining second photoresist layer and the metal layer thereon after the metal evaporation.
In alternative embodiments, the metal evaporation includes electron beam evaporation, sputtering, or electroplating.
In an alternative embodiment, the base epitaxy is GaAs.
The beneficial effects of the invention are as follows:
(1) The phenomenon that the side surface of the base electrode step is concave after wet etching is avoided, and if the device is not placed in a specified direction, a connecting metal layer is easy to crack or even break.
(2) The invention ensures that the HBT devices can be placed at will without specifying the placing direction in the process of manufacturing, thereby improving the design flexibility.
(3) Only the shape and design of the photomask are changed, and the whole process flow is not required to be changed, so that the complexity and cost caused by the process flow change are reduced.
Drawings
FIG. 1a is a schematic view of the wafer structure of the present invention;
figure 1b is a top view of an HBT device in one embodiment of the present invention;
FIG. 2 is a schematic view of a base step formed in one embodiment of the present invention (top view);
FIG. 3a is a schematic view of a base step and a metal layer formed in one embodiment of the present invention;
FIGS. 3b and 3c are cross-sectional views along the X and Y directions of a base step and a wiring metal layer, respectively, formed in one embodiment of the present invention;
fig. 4a is a schematic view of the structure of the base step and the wiring metal layer formed in the comparative example of the present invention;
fig. 4b and 4c are cross-sectional views along the X-direction and the Y-direction of the base step and the wiring metal layer formed in the comparative example of the present invention, respectively.
Detailed Description
The invention is further explained below with reference to the drawings and specific embodiments. The drawings of the present invention are merely schematic to facilitate understanding of the present invention, and specific proportions thereof may be adjusted according to design requirements. The definition of the context of the relative elements and the front/back of the figures described herein should be understood by those skilled in the art to refer to the relative positions of the elements and thus all the elements may be reversed to represent the same elements, which are all within the scope of the present disclosure.
Examples
Referring to fig. 1a-1b and fig. 3a-3c, a method for forming a metal wiring of an HBT device according to an embodiment of the present application is provided or formed by first providing or forming a wafer structure with a completed part of the device process. The wafer structure sequentially forms a base epitaxy 1, an emitter platform 2 and a base metal 3 through a conventional MBE epitaxy or MOCVD method, and the emitter platform 2 and the base metal 3 are arranged on the base epitaxy 1. The emitter mesa 2 comprises a first emitter mesa 21 and a second emitter mesa 22, the first emitter mesa 21 being arranged perpendicular to the second emitter mesa 22. In a preferred embodiment, the second emitter platform 22 is perpendicular to the middle of the first emitter platform 21, so that the first emitter platform 21 and the second emitter platform 22 are arranged in a T-shape, and the base metal 3 is disposed on two sides of the second emitter platform 22. In addition, the emitter platform 2 is further provided with a collector layer, a dielectric layer and other conventional HBT structures. In one embodiment, the HBT device is a GaAs HBT, the base epi 1 comprises a stack of n-type collector layer and p-type base layer, and the emitter mesa 2 and base metal 3 are provided on the p-type base layer. The base epitaxy 1 is GaAs, the n-type collector layer is n-type GaAs, the p-type base layer is p-type GaAs, and an etch stop layer (for example, inGaP) may be further disposed between the p-type base layer and the emitter mesa 2.
In the embodiment of the present application, as shown in fig. 1a, the cut direction of the HBT device is defined to be divided into an X direction (0, 1) and a Y direction (0, 1, -1) perpendicular to the X direction. As shown in fig. 1b, taking the wafer structure placed in the Y direction as an example, when the wafer structure is placed in the Y direction, that is, the length direction of the base metal 3 and the second emitter mesa 22 is in the Y direction, the base epitaxy 1 forms the base step 11 by wet etching, and the cross-sectional shape of the base step 11 cut in the X direction is trapezoidal, and the cross-sectional shape of the base step cut in the Y direction has a concave phenomenon.
In the present embodiment, during the process of the HBT device, after completing the processes of emitter mesa 2 etching, base metal 3 deposition, etc., a base step process is required. Firstly, designing a base step pattern, and then designing a first photomask according to the base step pattern. The shape of the base step 11 is shown in fig. 2, which is formed after the base step process is completed by using the first mask. The first photomask pattern comprises a preset part matched with the preset base electrode step pattern and a connecting line part formed by extending the preset part towards the connecting line direction, wherein the connecting line direction is the extending connection direction of the connecting line metal layer 4. In a preferred embodiment, the connection direction is the opposite direction of the Y direction, and the connection direction may be selected from other different directions according to the requirement. The connecting line part in the first photomask graph is positioned at the middle position of the edge of the preset part along the X direction. The emitter platform 2 and the base metal 3 are arranged above the base step 11 part formed corresponding to the preset part, and the base step 11 part formed corresponding to the connecting wire part is used for being connected with the connecting wire metal layer 4. In a preferred embodiment, after the base step 11 is formed, the second emitter mesa 22 is located in the middle of the base step 11, and the base metal 3 is located on both sides of the second emitter mesa 22.
In a specific embodiment, a first photoresist layer is formed on the surface of the wafer structure, a masking layer corresponding to the first mask pattern is formed after the exposure and development of the first mask, and then wet etching is performed on the base epitaxy 1 and the masking layer is stripped to form the base step 11. The etching solution is the volume ratio H 3 PO 4 :H 2 O 2 :H 2 O=1:1:10. By changing the first photomask corresponding to the base step 11, the shape of the base step 11 is changed, and a platform for leading out the wiring metal layer 4 is formed on the preset base step 11, so that the wiring metal layer 4 meets the wiring requirement, and the wiring metal layer 4 is prevented from cracking or breaking. Not only the shape design of the base step 11 is changed, but also the shape design of the wiring metal layer 4 is changed.
Further, the design of the wiring metal layer pattern is performed, and then the second photomask is designed according to the wiring metal layer pattern. The second photomask pattern comprises a first connecting line part covering the base electrode step 11 corresponding to the connecting line part and a second connecting line part formed by extending the first connecting line part in the extraction direction, wherein the extraction direction is the direction of leading out and connecting the connecting line metal layer to another device unit. In a preferred embodiment, the shapes of the first connection portions in the second mask pattern and the connection portions in the first mask pattern are preferably rectangular, where the size range represents the length and width, and other shapes may be selected in other designs as desired. In a further preferred embodiment, the minimum dimension of the wire portion is 2.0 μm in length and 2.0 μm in width. The larger the size of the wiring portion, the easier the process is to implement, the size of the wiring portion is related to the size of the wiring metal layer 4, and if the size of the wiring metal layer 4 is smaller than 1.4 μm, the problem of wire breakage is easy to occur, specifically, the size of the wiring portion may be 2.6 μm in length and 2.6 μm in width.
Finally, a second photoresist layer is formed on the surface of the wafer structure, a development window corresponding to the second photomask pattern is formed after the second photomask is exposed and developed, metal evaporation is performed on the development window, and the rest of the second photoresist layer and a metal layer above the second photoresist layer are stripped to form a connecting line metal layer 4 connected with the base electrode step 11. As shown in fig. 3a, the wiring metal layer 4 now covers over the base step 11 formed corresponding to the wiring portion and over a partial area of the first emitter mesa 21. In a preferred embodiment, the edge of the base step 11 exceeds the edge of the link metal layer 4 by at least 0.3 μm at the portion where the link metal layer 4 is connected to the base step 11. If the edge of the base step 11 and the edge beyond the wiring metal layer 4 are smaller than 0.3 μm, the wiring metal layer 4 may protrude out of the base step 11, and metal chips may be generated to cause leakage. In particular embodiments, metal evaporation includes electron beam evaporation, sputtering, or electroplating.
As shown in fig. 3b and 3c, when the base epi 1 is cut along the X direction, the base step 11 is formed by wet etching, and the cross-sectional shape of the side surface of the base step 11 is trapezoidal, and the wiring metal layer 4 is formed above the base step 11 and extends along the side surface of the base step 11, and no crack or break is generated in the wiring metal layer 4. When the base epitaxy 1 is cut along the Y direction, the base step 11 is formed by wet etching, and at this time, the cross-sectional shape of the side surface of the base step 11 is a polygon having a recess, and since the base step 11 portion corresponding to the wiring portion is present, the wiring metal layer 4 is formed only above the base step 11, and the wiring metal layer 4 is not present at the side edge of the base step 11, thereby preventing the wiring metal layer 4 from cracking or breaking.
Comparative example
Referring to fig. 4a-4c, the comparative example differs from the example in that: the first mask used for the base step 11 'has only a preset portion and no connecting portion, and the connecting metal layer 4' extends along the Y direction and covers the base step 11 'and is connected with the base step 11'. As shown in fig. 4a, the HBT device placement direction is also the Y direction at this time. The first mask corresponding to the base step 11 'and the second mask corresponding to the wiring metal layer 4' of the HBT device are rectangular. Reference is made to embodiment one.
In this case, as shown in fig. 4b and 4c, the side edge of the base step 11 'in the X direction is also a continuous slope, at this time, the wiring metal layer 4' may perform routing on the base step 11', while the side wall of the base step 11' in the Y direction is concave, and the concave side wall may form a tip at the top of the side edge of the base step 11', at this time, the wiring metal layer 4' cannot perform routing on the base step 11', and if routing, cracks or even breaks may easily occur at the top of the side edge of the base step 11'.
It follows that the embodiments of the present application differ from the comparative examples only in the shape design of the base step and the wiring metal layer, resulting in a change in the structure and coverage of the wiring metal layer overlying the base step edge. Even though the base step after wet etching still has the concave phenomenon, the connecting wire metal layer above the edge of the base step can not cover the side wall of the concave of the base step, so that the connecting wire metal layer can be prevented from generating cracks or breakage.
According to the invention, through changing the design mode of the base electrode step and the photomask of the connecting wire metal layer, not only can cracks or breaks caused by the concave phenomenon caused by wet etching on the connecting wire metal layer during wiring be avoided, but also the HBT device can be placed at will without specifying the placing direction in the process of manufacturing, and the design flexibility is improved. Under the condition of not changing the processing conditions, the invention can solve the problem that the connecting metal layer is easy to crack or break by only changing the designs of the first photomask corresponding to the base step and the second photomask corresponding to the connecting metal layer, and can also reduce the complexity and the cost caused by the change of the process flow.
The above embodiments are only used to further illustrate a metal connection method of HBT devices of the present invention, but the present invention is not limited to the embodiments, and any simple modification, equivalent variation and modification made to the above embodiments according to the technical substance of the present invention falls within the scope of the technical solution of the present invention.
Claims (9)
1. A metal wiring method of an HBT device is characterized in that: the method comprises the following steps:
1) Providing or forming a wafer structure with a part of finished device manufacturing process, wherein the wafer structure comprises a base epitaxy, an emitter platform and base metal, the emitter platform and the base metal are arranged on the base epitaxy, the emitter platform comprises a first emitter platform and a second emitter platform, and the first emitter platform and the second emitter platform are vertically arranged;
2) Providing a first photomask, wherein the first photomask pattern comprises a preset part matched with a preset base electrode step pattern and a connecting line part formed by extending the preset part towards the connecting line direction;
3) Forming a first photoresist layer on the surface of the wafer structure, exposing and developing by adopting the first photomask to form a shielding layer corresponding to the first photomask pattern, performing wet etching on the base epitaxy to form a base step, wherein the second emitter platform is positioned in the middle of the base step, and the base metal is arranged on two sides of the second emitter platform;
4) Providing a second photomask, wherein the second photomask pattern comprises a first connecting wire part covering a base electrode step corresponding to the connecting wire part and a second connecting wire part formed by extending the first connecting wire part towards the leading-out direction;
5) And forming a second photoresist layer on the surface of the wafer structure, exposing and developing by adopting the second photomask to form an open window corresponding to the second photomask pattern, and evaporating metal on the open window to form a connecting line metal layer connected with the base electrode step.
2. The method of metal wiring of HBT device of claim 1 wherein: and the connecting wire metal layer covers the base electrode step correspondingly formed on the connecting wire part.
3. The method of metal wiring of HBT device of claim 1 wherein: the minimum dimension of the connecting line part is 2.0 μm in length and 2.0 μm in width.
4. The method of metal wiring of HBT device of claim 1 wherein: the edge of the base electrode step correspondingly formed by the connecting line part exceeds the edge of the connecting line metal layer correspondingly formed by the first connecting line part by at least 0.3 mu m.
5. The method of metal wiring of HBT device of claim 1 wherein: the wiring metal layer extends over the base step and covers over a portion of the first emitter mesa.
6. The method of metal wiring of HBT device of claim 1 wherein: step 3 further comprises the step of stripping the shielding layer after wet etching.
7. The method of metal wiring of HBT device of claim 1 wherein: step 5 further comprises a step of stripping the remaining second photoresist layer and the metal layer thereon after the metal evaporation.
8. The method of metal wiring of HBT device of claim 1 wherein: the metal evaporation includes electron beam evaporation, sputtering or electroplating.
9. The method of metal wiring of HBT device of claim 1 wherein: the base epitaxy is GaAs.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6387768A (en) * | 1986-09-30 | 1988-04-19 | Fujitsu Ltd | Manufacture of semiconductor device |
| CN109390319A (en) * | 2017-08-09 | 2019-02-26 | 株式会社村田制作所 | Semiconductor device |
| CN111448665A (en) * | 2017-12-07 | 2020-07-24 | 高通股份有限公司 | Emitter-base lattice structure in heterojunction bipolar transistors for RF applications |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3846347B2 (en) * | 2002-03-27 | 2006-11-15 | 住友電気工業株式会社 | Bipolar transistor and manufacturing method thereof |
| JP4788096B2 (en) * | 2003-06-04 | 2011-10-05 | 住友電気工業株式会社 | Heterojunction bipolar transistor |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6387768A (en) * | 1986-09-30 | 1988-04-19 | Fujitsu Ltd | Manufacture of semiconductor device |
| CN109390319A (en) * | 2017-08-09 | 2019-02-26 | 株式会社村田制作所 | Semiconductor device |
| CN111448665A (en) * | 2017-12-07 | 2020-07-24 | 高通股份有限公司 | Emitter-base lattice structure in heterojunction bipolar transistors for RF applications |
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