WO2007070050A1 - Structure a faible charge de grille pour transistor mos a effet de champ d'alimentation - Google Patents

Structure a faible charge de grille pour transistor mos a effet de champ d'alimentation Download PDF

Info

Publication number
WO2007070050A1
WO2007070050A1 PCT/US2005/045432 US2005045432W WO2007070050A1 WO 2007070050 A1 WO2007070050 A1 WO 2007070050A1 US 2005045432 W US2005045432 W US 2005045432W WO 2007070050 A1 WO2007070050 A1 WO 2007070050A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
regions
conductivity type
gate
substrate
Prior art date
Application number
PCT/US2005/045432
Other languages
English (en)
Inventor
Edouard D. De Fresart
Zhu-Qing Feng
Ganming Qin
Pei-Lin Wang
Xiao-Ping Wang
Hong-Wei Zhou
Original Assignee
Freescale Semiconductor, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor, Inc. filed Critical Freescale Semiconductor, Inc.
Priority to PCT/US2005/045432 priority Critical patent/WO2007070050A1/fr
Priority to TW095146797A priority patent/TW200731532A/zh
Publication of WO2007070050A1 publication Critical patent/WO2007070050A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate

Definitions

  • the present invention generally relates to field effect transistors (FETS), and more particularly to TMOS type FETS.
  • FIG. 1 illustrates conventional prior art TMOS device 20.
  • TMOS device 20 is formed in substrate 21 having N++ drain region 22 at lower surface 23 of substrate 21, above which lies N-Epi region 24.
  • P-body regions 26 extend into N-Epi region 24 from upper surface 25 of substrate 21.
  • P+ body contact regions 28 and N+ source regions 30 extend into P- body regions 26 from upper surface 25.
  • Gate insulator 32 covered by gate electrode 34 extends between source regions 30 over channel regions 27 in P- body regions 26 and across so-called JFET region 36 located between P-body regions 26.
  • Contacts 31 are provided to P+ body contact regions 28 and N+ source regions 30, and contact 35 is provided to gate electrode 34.
  • Wp is the gate length and Lace is the length between facing P- body regions 26.
  • the channel lengths L CH are about (l/2)*(Wp-Lacc).
  • Wp is typically of the order of about four micro-meters or more and Lace about 2.4 micro-meters or more.
  • TMOS devices of the type illustrated in FIG. 1 are very useful, they suffer from a number of limitations well known in the art.
  • the on-resistance R DS(ON) is often higher than desired
  • the gate-source and gate-drain capacitances C GS and C GD are often larger than desired
  • the gate charge Q G can be larger than desired
  • other device properties may also be less than optimum. While various improvements have been made in the past to attempt to ameliorate these problems, it has often been the case that what is done to improve one characteristic results in degradation of another important characteristic.
  • R DS(ON) can be improved by increasing the doping in JFET region 36, this tends to undesirably increase C GD and/or Q G , and/or undesirably reduce the break-down voltage BV DSS .
  • CQ D and Q G can be reduced by thickening the gate oxide above the JFET region, this tends to increase R DS(ON ) and/or undesirably perturb the threshold voltage.
  • a figure of merit (FOM) R DS(ON) * Q G can be defined at a predetermined gate to source bias, that is useful in predicting the capabilities of TMOS power devices for higher speed, higher power applications.
  • Present day TMOS power devices have FOM values in the range of about 90-130 (milli-Ohms) * (nano-Coulombs) for advanced trench-FETs and about 130-200 (milli-Ohms) * (nano-Coulombs) for planar devices at, for example, a gate to source bias of about 4.5 volts.
  • TMOS devices In order to be able to efficiently switch significant amounts of power (e.g., 20-200 amps) at frequencies in the range of about 10E5 to 10E6 cps or higher, smaller values of FOM are important. Thus, there is an ongoing need for TMOS devices whose figure of merit is more suited to higher speed, higher power applications. Accordingly, there is a need for TMOS devices having these and other desirable features. Further, it is desirable to provide an improved device structure and method that provides TMOS devices of the desired properties, especially devices with figures of merit equal or less than about 90 (milli-Ohms) * (nano- Coulombs). In addition, it is desirable the changes in device structure and method of fabrication used to improve the devices be compatible with existing device manufacturing techniques. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.
  • FIG. 1 is a simplified schematic cross-sectional view through a TMOS device according to the prior art
  • FIG. 2 is a simplified schematic cross-sectional view through a TMOS device according to an embodiment of the present invention
  • FIG. 3 is a simplified schematic cross-sectional view through a TMOS device according to a further embodiment of the present invention.
  • FIG. 4 shows a graph of doping concentration as a function of depth from the principal surface for the TMOS devices of FIGS. 2-3 at a central location under the gate electrode;
  • FIG. 5 shows a graph of net active dopant concentration as a function of depth from the principal surface for the TMOS devices of FIGS. 2-3, showing further details and at different locations within the device;
  • FIGS. 6-26 are simplified schematic cross-sectional views showing further details and according to further embodiments of the present invention, illustrating sequential steps in methods of fabricating devices of the type illustrated in FIGS. 2 and 3, wherein FIGS. 6-8 show initial sequential steps applicable to the devices of both FIGS. 2 and 3, and FIGS. 9-16 show further sequential steps applying to the device of FIG. 2, and FIGS. 17-26 show further sequential steps applying to the device of FIG. 3.
  • MOS devices may be P-channel type devices referred to as PMOS devices or N- channel type devices, referred to as NMOS devices.
  • This invention relates usefully to NMOS devices and is described herein for such structures. However, this is for convenience of illustration and not intended to be limiting and the principles taught herein also apply to PMOS devices.
  • P -type and N-type are intended to be equivalent to and include the more general terms “first conductivity type” and “second conductivity type” respectively, where “first” and “second” can refer to either P or N conductivity types.
  • FIG. 2 is a simplified schematic cross-sectional view through TMOS device 40 according to an embodiment of the present invention.
  • Device 40 comprises substrate 41, conveniently of silicon but other semiconductors may also be used, having lower surface 43 and upper surface 45.
  • N++ drain region 42 is provided generally at or adjacent lower surface 43.
  • N-Epi region 44 extends upwardly from N++ drain region 42.
  • P-body regions 46 extend into N-Epi region 44 from surface 45 and are laterally separated by distance Lace.
  • P++ body contact regions 48 and N++ source regions 50 extend into P-body regions 46.
  • Gate dielectric (e.g., of silicon dioxide) 52 overlies surface 45 above channel regions 47 and so-called JFET region 56, and extends at least to and/or partly above source regions 50.
  • Conductive gate electrode 53 of width Wp overlies gate dielectric 52.
  • Gate electrode 53 is desirably a composite sandwich wherein layer 54 is conveniently of doped poly-silicon and layer 55 is conveniently of a polycide such as, for example, tungsten-silicide WSi x where, generally, 1.5 ⁇ x ⁇ 2, but other composition ranges and other polycides can also be used.
  • dielectric layer 60 e.g., of silicon oxide
  • source metallization 64 of, for example, Al, Cu, Au, Si and/or alloys thereof, may bridge over gate electrode 53 above active channel regions 47 and JFET region 56, making contact to source regions 50 on either side of gate electrode 53.
  • Al with a trace of Cu is preferred for metallization 64 but this is not essential and, as used herein, the abbreviation "Al:Cu" is intended to include not only the preferred combination but also the many other possible metal combinations that can be used, including but not limited to those listed above.
  • conductive barrier material 51 of, for example, Ti/TiN or other conductive intermetallic between source and body contact regions 50, 48 and source/body metallization 64 to retard inter-diffusion of polycide 55 and metallization 64, and thereby maintain low resistance contacts to source/body contact regions 50, 48.
  • Other conductive contact materials may also be used for source/body metallization 64 or metallization 64 may be applied directly to source/body contact regions 50, 48, although this is less desirable.
  • Side-wall spacers 61, 62 are provided to separate the lateral edges of gate electrode 53 from source and body contacts 51 and source metallization 64.
  • the channel lengths L C H are about (l/2)*(Wp- Lacc).
  • FIG. 3 is a simplified schematic cross-sectional view through TMOS device 70 analogous to that of FIG. 2, but according to a further embodiment of the present invention. Like reference numbers are used to identify like regions, and the discussion of FIG. 2 with respect to such like region is incorporated herein by reference.
  • Device 70 of FIG. 3 differs from device 40 of FIG. 2 in at least two significant respects. First, device 70 includes thickened dielectric region 72 (also referred to as an "oxide plug") in gate dielectric layer 52 approximately centrally located under gate electrode 53 about mid-way between P-body regions 46. Second, N-type PField regions 73 are provided in JFET region 56 on either side of oxide plug 72 and extending to P-body regions 46.
  • thickened dielectric region 72 also referred to as an "oxide plug”
  • N-type PField regions 73 are provided in JFET region 56 on either side of oxide plug 72 and extending to P-body regions 46.
  • Providing oxide plug 72 reduces the gate-drain capacitance C GD and allows Wp and Lace to be 174 th to l/3 rd larger than the values for device 40 of FIG. 2. This reduces the JFET pinch-off effect in region 56, thereby providing further improvement in R DS(ON >-
  • the combination of PField regions 73 and enhanced doping in JFET region 56 allows the impurity profile in JFET region 56 to be controlled (see FIGS. 4-5) so as to provide improved FOM in the range of 70 to 90 (milli-Ohms) * (nano-Coulombs, without compromising the breakdown voltage BV DSS - This is a significant improvement over prior art TMOS devices.
  • the structure of FIG. 2 is preferred when cost is a dominant factor and the structure of FIG. 3 is preferred when enhanced performance is a dominant factor. However, both device structures are useful and provide improved performance compared to the prior art.
  • Trace 81 shows the concentration of P-type dopant (e.g., boron) to about depth 82 beneath gate electrode 53
  • trace 83 shows the concentration of N-type dopant (e.g., phosphorous) to the sum of depth 84 plus distance 85
  • trace 86 shows the net doping, that is, the difference between the N-type and P-type doping, as a function of distance into substrate 41 from principal surface 45.
  • Depth 84 is identified in FIG. 4 as corresponding approximately to JFET region 56.
  • the P-type dopant giving rise to trace 81 originates via lateral out-diffusion from P-body regions 46.
  • the N-type dopant of trace 83 in region 84 of FIG. 4 originates from an N-type implant into JFET region 56 to enhance the doping therein.
  • the further slight downward trend in N-type doping in region 85 of FIG. 4 is due to the tail of this implant extending into otherwise uniformly doped N-epi region 44 of devices 40, 70. What is important for obtaining the improved performance of the invented structures illustrated in FIGS.
  • N-epi-region 44 terminates at boundary 87 at depth 84 plus distance 85 where it intersects highly doped drain region 42 of thickness 88.
  • FIG. 5 shows graph 90 of net active dopant concentration as a function of depth from principal surface 45 for TMOS device 40 of FIG. 2 and device 70 of FIG. 3, showing further detail and at different locations within the device, i.e., at X ⁇ 0 (trace 92), X ⁇ 0.33 Wp (trace 93), X ⁇ 0.38 Wp (trace 94), X ⁇ 0.42 W P (trace 95), and X- 0.5 W P (trace 96).
  • the horizontal scale on FIG. 5 has been expanded relative to FIG. 4 to show greater detail, wherein distance 97 indicates the approximate depth of P-body region 46 and depth 98 indicates the approximate depth of JFET region 56 (also see FIGS. 2-3).
  • Trace 92 indicates the net active dopant concentration. It will be noted from trace 92 in this enlarged presentation that the net dopant concentration at X- 0 decreases substantially linearly with distance from principal surface 45 through the P-body region 46 and substantially through JFET region 56 of devices 40, 70. This is an important factor in the improved performance of the invented structures.
  • FIGS. 6-26 are simplified schematic cross-sectional views showing further detail and according to further embodiments of the present invention, illustrating sequential steps in methods of fabricating device 40 of FIG. 2 and device 70 of FIG. 3, wherein FIGS. 6-8 show initial sequential steps applicable to both devices 40 and 70, and FIGS. 9-16 show further sequential steps applying to device 40 of FIG. 2 and FIGS. 17-26 show further sequential steps applying to device 70 of FIG. 3.
  • FIG. 6 shows step 101 wherein there is provided semiconductor wafer 41 of preferably silicon having N++ doped layer or substrate 42 on which has been grown or otherwise formed N-type layer or region 44.
  • Layer or region 44 is preferably an epi-layer but this is not essential, and the identification of layer 44 on FIGS 6-26 as an "N-Epi" layer is merely by way of example and not intended to be limiting.
  • the combination of highly doped layer or region 42 surmounted by region 44 of substantially uniform doping may be achieved in other ways well known in the art.
  • Layer or substrate 42 is conveniently arsenic doped to about 0.004 Ohm-cm, but higher or lower doping levels may also be used.
  • Layer 44 is conveniently phosphorous doped to about 0.1 to 1.0 Ohm-cm with about 0.2 to 0.5 Ohm-cm being preferred, but higher and lower doping can also be used. Layer 44 is preferably about 3-4 micrometers in thickness, but thinner or thicker layers can also be used.
  • Initial oxide layer 110 of a few thousand Angstrom units thickness is provided on upper surface 45 by any convenient means.
  • Mask layer 112 of, for example, photoresist is applied on initial oxide layer 110 and patterned to provide openings 113, 114 extending to semiconductor surface 45.
  • P-type doped regions 115, 116 are introduced into N-type layer 44 through openings 113, 114 respectively, thereby providing the structure illustrated in FIG. 6.
  • P-type doped regions 115, 116 are generally referred to as "P-edge” regions or "P-edge implants.” They are desirable but not essential to the present invention.
  • step 102 of FIG. 7 mask layer 112 is removed, and field oxide layer 120 grown or otherwise formed to a thickness about twice that of initial oxide 110, but larger or smaller thickness values may also be used.
  • Mask layer 126 is applied and patterned to expose central portion 121 of field oxide layer 120. Central portion 121 is conveniently removed by etching via opening 125 in mask layer 126.
  • the higher temperatures encountered during deposition or growth of field oxide 120 cause initial doped regions 115, 116 to diffuse downwardly and laterally in N-layer 44, thereby providing expanded P-type regions 123, 124 respectively, as shown in FIG. 7.
  • screen oxide 130 typically of a few hundred Angstroms units thickness is provided on surface 45, e.g., by deposition or thermal growth, and phosphorous implant 133 is provided.
  • a dose in the range of about 0.5E12 to 5E12 per sq cm is useful with about 2El 2 per sq cm being preferred, at an energy in the range of about 150 to 350 keV with about 250 keV being preferred.
  • the phosphorous (or other dopant) atoms of implant 133 form buried doped region 134 centered at distance 135 of about 0.1 to 0.6 micrometers below surface 45. Doped buried region 134 will eventually provide the principal doping for JFET region 56 of FIGS. 2-3.
  • ion implantation 133 is a preferred method of providing buried doped region 134, it is not essential and other doping and/or deposition techniques well known in the art can also be used to provide buried doped region 134.
  • implant 133 is described above as a single implant at a particular energy and dose, this is merely for convenience of description and persons of skill in the art will understand based on the teachings herein that multiple implants at varying energies and doses may also be performed. These are often referred to in the art as "chain implants” and it will be understood that chain implants are a convenient way of achieving various doping profiles and are intended to be included in the terms "implant” or "implantation” as used herein. The foregoing steps are common to the formation of both device 40 of FIG.
  • PField implant 221 can be optionally performed to create shallow N-type doped layer 219 approximately just underneath surface 45.
  • PField implant layer 219 is preferably formed using arsenic implant 221 at about 20-80 KeV, depending upon the thickness of screen oxide layer 130, with about 60 keV being convenient and to a dose in the range of about 0.5E12 to 5E12 per sq cm with about 2El 2 to 3El 2 per sq cm being convenient.
  • the purpose of PField implant layer 219 is to facilitate adjusting the dopant concentration in JFET region 56 near surface 45 (also see FIG.
  • step 201 of FIG. 10 screen oxide 130 is preferably removed by a brief etch and gate oxide 230 formed in its place, typically by thermal growth to a thickness depending upon the desired voltage capabilities and gate capacitance of the device. Gate oxide thicknesses in the range of 100-500 Angstroms units are convenient with thicknesses in range of 350-500 Angstrom units being preferred for higher voltage power devices, but larger or smaller thicknesses can also be used.
  • step 201 poly- silicon or other blanket semiconductor (SC) layer 212 is provided over oxide layers 120, 230.
  • SC blanket semiconductor
  • Layers 212, 214, 216 are conveniently but not essentially formed by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD). However, other formation techniques may also be used. Sputtering and evaporation are non-limiting examples of alternative deposition methods for any and all of layers 212, 214, 216.
  • the thicknesses of layers 212, 214 should be chosen in conjunction with the choice of materials for these layers so as to provide relatively low resistance gate electrodes. In general, thicknesses of the order of a few thousand Angstrom units are convenient.
  • the thickness of dielectric layer 216 is chosen by the device designer so as to limit capacitive coupling between the source and gate leads to acceptable levels without producing an overly thick device superstructure. Persons of skill in the art will understand how to make such choices.
  • Masking layer 218 of, for example, photoresist is applied over dielectric layer 216 and patterned to provide openings 220, 222 wherein underlying portions of layers 212, 214, 216 are removed, conveniently by etching, thereby producing the structure shown in FIG. 10. In step 202 of FIG.
  • step 11 masking layer 218 is removed and sidewall oxidation performed to form first side-wall spacers 224, 226 on the exposed lateral edges of poly-SC layer 212 and polycide layer 214.
  • first sidewall spacers 224, 226, buried doped region 134 diffuses upward and downward to form wider N-doped region 234 extending substantially from surface 45, as shown in FIG. 11.
  • P-type implant 236 of, for example, boron is provided through openings 220, 222 to a dose of about 5El 3 per sq cm at an energy of about 70 keV, to form doped regions 228, 229 beneath openings 220, 222.
  • a high temperature drive is provided at, for example, 900 to 1200 degrees centigrade, with about 1000-1100 degrees centigrade for 70-120 minutes being preferred.
  • P-doped regions 250, 252 correspond to P-body regions 46 and N- doped region 254 corresponds to JFET region 56 in FIG, 2.
  • Regions 255, 256, 262, 264 lie laterally outside of FIG. 2 and are not shown therein.
  • step 205 of FIG. 14 mask region 266 located approximately centrally in opening 222 is provided, thereby leaving openings 270 between mask region 266 and side-wall spacers 226.
  • N+ implant 263 of, for example, arsenic at an energy of about 50-100 keV to a dose of about 1E15 to 10E15 per sq cm, preferably at about 80 keV to a dose of about 4E15 per sq cm, is applied conveniently through oxide layer 230 to form source regions 278, 280, as shown in FIG. 14. While ion implantation is preferred, other doping means well known in the art may also be used, hi step 206 of FIG.
  • a blanket layer of dielectric such as, for example, silicon oxide is deposited over the structure of FIG. 13 (e.g., by CVD, PECVD, evaporation or sputtering) and then differentially etched using means well known in the art to provide second side-wall spacers 274, 276 on the lateral edges of layers 212, 214, 216 in openings 220, 222.
  • the anisotropic etch also removes oxide layer 230 in openings 220, 222.
  • P-type implant 286 is provided into surface 45 through openings 220, 222 to form P-type regions 282, 284.
  • any type of convenient P-type implant material may be used but boron implanted at energies in the range of about 10-80 keV to a dose of about 0.5E15 to 3E15 per sq cm is convenient, with an energy of about 40 keV and a dose of about IE 15 per sq cm being preferred, thereby providing the structure illustrate in FIG. 15.
  • opening 293 is etched through dielectric layer 216 to permit contact to polycide layer 214.
  • an inter-metallic conductive barrier layer is deposited, masked and etched to leave regions 290 in contact with source regions 278, 280 and body contact region 284, and region 292 in contact with polycide layer 214.
  • Dielectric layer 230 of FIG. 16 corresponds to gate dielectric 52 of FIG. 2; layers 212, 214, 216 of FIG. 16 correspond to layers 54, 55, 60 respectively of FIG. 2; metallization 294 of FIG. 16 corresponds to metallization 64 of FIG. 2; P-type regions 250, 252 of FIG. 16 correspond to P-body regions 46 of FIG. 2; region 254 of FIG. 16 corresponds to JFET region 56 of FIG.
  • source regions 278, 280 of FIG. 16 correspond to source regions 50 of FIG. 2; body contact region 284 of FIG. 16 corresponds to body contact region 48 of FIG. 2; N-epi region 44 of FIG. 16 corresponds to N- epi region 44 of FIG. 2, N++ drain region 42 of FIG. 16 corresponds to N++ region 42 of FIG. 2; first sidewall spacers 224, 226 of FIG. 16 correspond to first sidewall spacers 61 of FIG. 2; and second sidewall spacers 274, 276 correspond to second sidewall spacers 62 of FIG. 2. Regions 255, 256, 262, 264 of FIG. 16 are not shown in FIG. 2.
  • FIGS. 17-26 illustrate steps subsequent to steps 101-103 of FIGS. 6-8, that are particularly adapted to form device 70 of FIG. 3.
  • step 301 of FIG. 17 the structure of step 103 of FIG. 8 is modified by depositing oxidation barrier layer 342 of, for example, silicon nitride over oxide layers 120, 130.
  • Mask layer 344 of, for example, photoresist is applied over barrier layer 342 and patterned to provide openings 347, 348, 349 extending to oxide layers 120, 130, thereby providing the structure illustrated in FIG. 17.
  • a further oxidation step is carried out so that those regions not protected by oxidation barrier layer 342 increase in thickness.
  • thicker oxide region 72 corresponding to oxide plug 72 of FIG. 3, forms under opening 348 in oxidation barrier layer 342.
  • the oxide regions under openings 347, 349 also increase slightly in thickness, but this is not essential. Those portions of oxide layers 120, 130 covered by oxidation barrier layer 342 are not significantly further oxidized.
  • the structure of FIG. 18 comprising oxide plug 72 is obtained.
  • PField implant 321 is provided to create shallow N-type doped layer 319 approximately just beneath surface 45.
  • PField implant layer 319 is preferably formed using arsenic implant 321 at about 20-80 KeV, depending upon the thickness of oxide layer 130, with about 60 keV being convenient and to a dose in the range of about 0.5E12 to 5E12 per sq cm with about 2E12 per sq cm being convenient.
  • the purpose of PField implant layer 319 is to facilitate adjusting the dopant concentration in JFET region 56 so as to achieve the linear dropoff in net doping concentration with distance from surface 45, such as is illustrated in FIGS. 4- 5.
  • step 304 screen oxide 130 is preferably removed by a brief etch and gate oxide 330 formed in its place, typically by thermal growth to a thickness depending upon the desired voltage capabilities of the device. Gate oxide thicknesses in the range of 100-500 Angstroms units are convenient with thicknesses in range of 350-500 Angstrom units being preferred for higher voltage power devices, but larger or smaller thicknesses can also be used.
  • step 304 poly-silicon or other blanket semiconductor (SC) layer 312 is provided over oxide layers 120, 330.
  • SC blanket semiconductor
  • Layers 312, 314, 316 are conveniently but not essentially formed by chemical vapor deposition (CVD) or plasma enhance chemical vapor deposition (PECVD). However, other formation techniques may also be used. Sputtering and evaporation are non-limiting examples of alternative deposition methods for any and all of layers 312, 314, 316.
  • the thicknesses of layers 312, 314 should be chosen in conjunction with the choice of materials for these layers so as to provide relatively low resistance gate electrodes.
  • dielectric layer 316 In general, thicknesses of the order of a few thousand Angstrom units are convenient.
  • the thickness of dielectric layer 316 is chosen by the device designer so as to limit capacitive coupling between the source and gate leads to acceptable levels without producing an overly thick device superstructure. Persons of skill in the art will understand how to make such choices.
  • Masking layer 318 of, for example, photoresist is applied over dielectric layer 316 and patterned to provide openings 320, 322 wherein underlying portions of layers 312, 314, 316 are removed, conveniently by etching, thereby producing the structure shown in FIG. 20. In step 305 of FIG.
  • masking layer 318 is removed and sidewall oxidation performed to form first side-wall spacers 324, 326 on the exposed edges of poly-SC layer 312 and polycide layer 314.
  • buried doped region 134 diffuses upward and downward to form wider N-doped region 334 extending substantially from PField implant 319 and surface 45, as shown in FIG. 21.
  • P-type implant 336 of, for example, boron is provided through openings 320, 322 to a dose of about 5E13 per sq cm at an energy of about 70 keV, to form P-doped regions 328, 329 beneath openings 320, 322.
  • a high temperature drive is provided at, for example, 900 to 1200 degrees centigrade, with about 1000 to 1100 degrees centigrade for 70 to 120 minutes being preferred,
  • P-doped doped regions 328, 329 expand to form P-doped regions 350, 352, N-doped region 334 expands and becomes divided into three regions, that is, central "JFET" region 354 and peripheral regions 355, 356 (not shown in FIG. 3), and P-doped regions 123, 124 expand to become P-doped edge regions 362, 364, as shown in FIG. 23.
  • P-doped regions 350, 352 correspond to P-body regions 46
  • N- doped region 354 corresponds to JFET region 56 in FIG. 3.
  • Regions 355, 356, 362, 364 lie laterally outside of FIG. 3 and are not shown therein.
  • step 308 of FIG. 24 mask region 366 located approximately centrally in opening 322 is provided, thereby leaving openings 370 between mask region 366 and side-wall spacers 326.
  • N+ implant 363 of, for example, arsenic at an energy of about 50-100 keV to a dose of about 1E15 per sq cm to 10E15 per sq cm, preferably at about 80 keV to a dose of about 4E15 per sq cm is applied, conveniently through oxide layer 330 to form source regions 372, 384, as shown in FIG. 24. While ion implantation is preferred, other doping means well known in the art may also be used.
  • a blanket layer of dielectric such as, for example, silicon oxide is deposited over the structure of FIG. 24 and then differentially etched using means well known in the art to provide second side-wall spacers 374, 376 on the lateral edges of layers 312, 314, 316 in openings 320, 322.
  • the anisotropic etch also removes oxide layer 330 in openings 320, 322.
  • P-type implant 386 is provided into surface 45 through openings 320, 322 to form P-type regions 382, 384.
  • P-type implant material Any type of convenient P-type implant material maybe used but boron implanted at energies in the range of about 10-80 keV to a dose of about 0.5E15 to 3E15 per sq cm is convenient, with an energy of about 40 keV and a dose of about IE 15 per sq cm being preferred, thereby providing the structure illustrate in FIG. 25.
  • step 310 of FIG. 26 opening 393 is etched through dielectric layer 316 to permit contact to polycide layer 314. Then an inter-metallic conductive barrier layer is deposited, masked and etched to leave regions 390 in contact with source regions 378, 380 and body contact region 384, and region 392 in contact with polycide layer 314. Then a layer of Al:Cu or other highly conductive material is deposited over the structure and masked and etched to provide source/body metallization 394 in contact with conductive barrier layer regions 390 and gate metallization 396 in contact with conductive barrier layer region 392. The structure illustrated in FIG. 3 is then substantially complete. Dielectric layer 330 of FIG. 26 corresponds to gate dielectric 52 of FIG.
  • first sidewall spacers 324, 326 of FIG. 26 correspond to first sidewall spacers 61 of FIG. 3; and second sidewall spacers 374, 376 correspond to second sidewall spacers 62 of FIG. 3. Regions 355, 356, 362, 364 of FIG. 26 are not shown in FIG. 3.
  • a TMOS device comprising, a semiconductor substrate of a first conductivity type and having a first principal surface, spaced- apart body regions of a second conductivity type extending a first distance into the substrate from the first principal surface and separated near the first surface by a first region of the first conductivity type, source regions of the first conductivity type located substantially at the first surface in the spaced-apart body regions and separated from the first region by channel regions, an insulated gate located above the first surface overlying at least the channel regions and the first region, a drain region of the first conductivity type located in the substrate beneath the first region, and wherein the net active dopant concentration in a generally central location in the first regions decreases substantially linearly with distance from the first surface through a portion of the first region.
  • the spaced-apart body regions extend a first depth into the substrate from the first surface and the portion of the first region extends a distance from the first surface approximately equal to at least half the first depth.
  • the portion of the first region extends a distance from the first surface approximately equal to the first depth.
  • the device further comprises a region of greater separation between the gate and the first surface located approximately centrally under the gate.
  • the first region has a doping greater than portions of the substrate immediately beneath the first region.
  • the greater doping of the first region relative to the portions of the substrate immediately beneath the first region is obtained by ion implantation.
  • the first region has its greatest net doping proximate the first surface.
  • the first region while predominantly of the first conductivity type has a net active doping concentration that declines substantially linearly with distance from the first surface, wherein the net active doping concentration arises from a difference between doping of a second opposite conductivity type and doping of the first conductivity type.
  • a TMOS device made by a process comprising, forming in a substrate of a first conductivity type, a drain region, forming in the substrate spaced apart body regions of a second, opposite conductivity type extending from a first surface of the substrate into an interior portion of the substrate to substantially a first depth separated from the drain region by a first portion of the substrate, forming a JFET region of the first conductivity type in the substrate between the spaced apart body regions and extending to the first surface and having a dopant concentration higher than that of a second portion of the substrate beneath the JFET region, wherein a net active dopant concentration in the JFET region declines substantially linearly as a function of distance from the first surface through at least half of the JFET region, providing a gate separated from the first surface and extending over portions of the spaced-apart body regions adapted to function as channel regions and over the JFET region, and forming source regions of the first conductivity type in the body regions
  • the method of forming the JFET region comprises implanting a buried region of dopant ions of the first conductivity type into the JFET region.
  • the method of forming the JFET region having a net active dopant concentration that declines substantially linearly with distance from the surface comprises, implanting ions of a second opposite conductivity type in regions adjacent the JFET regions so that some of said ions of the second conductivity type diffuse laterally into the JFET region.
  • the method of forming the JFET region further comprises implanting a buried layer of ions of the first conductivity type in the JFET region.
  • the method of forming the JFET regions further comprises implanting at least two groups of ions into the JFET region at different depths.
  • the at least two groups of ions comprise different ions.
  • a method for forming an MOS device comprising, providing a semiconductor substrate of a first conductivity type having an upper surface, first implanting through the upper surface a buried doped region of the first conductivity type, forming a gate dielectric on the upper surface, depositing a gate conductor and overlying dielectric layer on the gate dielectric, masking and etching the gate conductor and overlying dielectric layer to provide at least two spaced-apart openings extending to the gate dielectric and defining the lateral extent of the gate, second implanting body regions of a second opposite conductivity type in the substrate through the openings in the gate conductor and overlying dielectric player, anytime after the second implant step, heat treating the device so that the net active impurity concentration in at least a portion of the central region of the substrate under the gate conductor decreases substantially linearly with distance from the surface, forming dielectric spacers on lateral edges of the gate conductor in the openings, thereby narrowing the openings,
  • the method further comprises prior to the depositing step, forming an oxide plug located underneath a central portion of the gate dielectric.
  • the first implanting step comprises implanting first and second buried doped regions having different depths.
  • the step of implanting first and second buried doped regions having different depths further comprises performing such implantations using different dopants.
  • the different dopants are of the same conductivity type.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

La présente invention concerne des procédés (101-103, 200-207, 301-310) et un appareil (40, 70) pour des dispositifs à transistors MOS (40, 70). Le dispositif (40, 70) comporte des première et seconde régions de source de type N, électriquement en parallèle, disposées dans de régions de corps de type P espacées (46), séparées par une région de jonction JFET de type N (56) au niveau d'une première surface (45). Des régions de canal (47) sous-jacentes à la grille (53) au niveau de la première surface (45), s'étendent depuis les régions de source (50) à travers des parties (47) des régions de corps (46) jusqu'à la région JFET (56) qui communique via une région épitaxiale N (44) avec une région de drain sous-jacente (42). Une implantation ionique est utilisée pour une densité de dopage sur mesure (86, 92) dans la région JFET (56) de sorte que la concentration de dopage actif nette (86, 92) dans la partie centrale (X∩0) de la région JFET (56) diminue sensiblement linéairement depuis la première surface (45) vers la région épitaxiale N sous-jacente (44). La relation linéaire s'étend globalement jusqu'à environ la même profondeur (65) que celle des régions de corps de type P (46) et se trouve à travers la différence de la concentration d'impuretés de type N (83) et de type P (81) dans la région JFET (56).
PCT/US2005/045432 2005-12-14 2005-12-14 Structure a faible charge de grille pour transistor mos a effet de champ d'alimentation WO2007070050A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/US2005/045432 WO2007070050A1 (fr) 2005-12-14 2005-12-14 Structure a faible charge de grille pour transistor mos a effet de champ d'alimentation
TW095146797A TW200731532A (en) 2005-12-14 2006-12-14 Low gate charge structure for power MOSFET

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2005/045432 WO2007070050A1 (fr) 2005-12-14 2005-12-14 Structure a faible charge de grille pour transistor mos a effet de champ d'alimentation

Publications (1)

Publication Number Publication Date
WO2007070050A1 true WO2007070050A1 (fr) 2007-06-21

Family

ID=36997662

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/045432 WO2007070050A1 (fr) 2005-12-14 2005-12-14 Structure a faible charge de grille pour transistor mos a effet de champ d'alimentation

Country Status (2)

Country Link
TW (1) TW200731532A (fr)
WO (1) WO2007070050A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8030153B2 (en) 2007-10-31 2011-10-04 Freescale Semiconductor, Inc. High voltage TMOS semiconductor device with low gate charge structure and method of making
CN106898652A (zh) * 2017-03-09 2017-06-27 电子科技大学 一种碳化硅vdmos器件

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8481372B2 (en) * 2008-12-11 2013-07-09 Micron Technology, Inc. JFET device structures and methods for fabricating the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5742164A (en) * 1980-08-27 1982-03-09 Hitachi Ltd Semiconductor device
EP0119400A1 (fr) * 1983-02-17 1984-09-26 Nissan Motor Co., Ltd. MOSFET de type vertical et procédé pour sa fabrication
US4803533A (en) * 1986-09-30 1989-02-07 General Electric Company IGT and MOSFET devices having reduced channel width

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5742164A (en) * 1980-08-27 1982-03-09 Hitachi Ltd Semiconductor device
EP0119400A1 (fr) * 1983-02-17 1984-09-26 Nissan Motor Co., Ltd. MOSFET de type vertical et procédé pour sa fabrication
US4803533A (en) * 1986-09-30 1989-02-07 General Electric Company IGT and MOSFET devices having reduced channel width

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KOBAYASHI T ET AL: "High-voltage power MOSFETs reached almost to the silicon limit", PROCEEDINGS OF THE 13TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS (ISPSD'01), OSAKA, JP, 4 June 2001 (2001-06-04), IEEE, NEW YORK, NY, USA, pages 435 - 438, XP010551657, ISBN: 4-88686-056-7C *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8030153B2 (en) 2007-10-31 2011-10-04 Freescale Semiconductor, Inc. High voltage TMOS semiconductor device with low gate charge structure and method of making
CN106898652A (zh) * 2017-03-09 2017-06-27 电子科技大学 一种碳化硅vdmos器件

Also Published As

Publication number Publication date
TW200731532A (en) 2007-08-16

Similar Documents

Publication Publication Date Title
US10978585B2 (en) MOS device with island region
US20240186412A1 (en) High Voltage Transistor Structure
US7602014B2 (en) Superjunction power MOSFET
US9293376B2 (en) Apparatus and method for power MOS transistor
US8728890B2 (en) Fabrication of MOS device with integrated Schottky diode in active region contact trench
US8928079B2 (en) MOS device with low injection diode
US7608510B2 (en) Alignment of trench for MOS
US7397084B2 (en) Semiconductor device having enhanced performance and method
US7446354B2 (en) Power semiconductor device having improved performance and method
US9660020B2 (en) Integrated circuits with laterally diffused metal oxide semiconductor structures and methods for fabricating the same
CN110875310B (zh) 高压cmos器件与共享隔离区的集成
WO2007027924A1 (fr) Dispositif en silicium-sur-rien a barriere schottky a source/drain metallique et procede associe
WO2008130691A2 (fr) Mosfet de puissance à tranchée latérale haute tension (> 100 v) avec une faible résistance spécifique à l'état passant
CN110828456A (zh) 用于在功率器件中减小衬底掺杂剂向外扩散的氧插入的Si层
CN110957370A (zh) 横向双扩散晶体管的制造方法
US8030153B2 (en) High voltage TMOS semiconductor device with low gate charge structure and method of making
WO2007070050A1 (fr) Structure a faible charge de grille pour transistor mos a effet de champ d'alimentation
TWI411108B (zh) 具有低注入二極體的ｍｏｓ元件
TW202422660A (zh) 包含電晶體單元的半導體元件及其相關製造方法
JP2001511601A (ja) 電界効果により制御される半導体構成素子の作製方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 05854200

Country of ref document: EP

Kind code of ref document: A1