WO2007057957A1

WO2007057957A1 - Plasma display device

Info

Publication number: WO2007057957A1
Application number: PCT/JP2005/021110
Authority: WO
Inventors: Yasunobu Hashimoto; Tomokatsu Kishi; Katsumi Itoh; Isao Furukawa
Original assignee: Fujitsu Hitachi Plasma Display Limited
Priority date: 2005-11-17
Filing date: 2005-11-17
Publication date: 2007-05-24
Also published as: JPWO2007057957A1

Abstract

Provided is a technology by which cost of a PDP device is reduced by reducing the number of power supplies for driving display of the PDP. In the PDP device, positive and negative sustain pulses are applied to X and Y electrodes of the PDP. The heights of the positive and negative sustain pulses are asymmetric, and a potential (Vs1) of the positive sustain pulse and a potential (Va) of an address pulse are equivalent. The common power supply is used for the positive sustain pulse and the address pulse.

Description

Specification

Plasma display device

Technical field

TECHNICAL FIELD [0001] The present invention relates to a technology of a plasma display device (PDP device) including a plasma display panel (PDP), and more particularly, to driving of an electrode of a PDP and a configuration of a power source therefor.

Background art

[0002] Sustain pulses are used so that low breakdown voltage elements can be used compared to conventional PDP device technology.

There is a technology (so-called TERES drive system) that configures a circuit such as a sustain circuit (circuit for sustain pulse application) as a symmetrical positive / negative pulse (voltage pulse) (voltage pulse applied for sustain discharge) . That is, as a sustain pulse, a plurality of short pulses, a positive pulse (positive sustain pulse) and a negative pulse (negative sustain pulse) are alternately repeated. The symmetric positive and negative pulses are the positive pulses. And the absolute value of the negative pulse potential are the same. The conventional sustain voltage is Vs.

[0003] Such a conventional technique is described in Japanese Patent Laid-Open No. 2002-62843 (Patent Document 1). By using positive and negative pulses as sustain pulses, each pulse height (potential absolute value) is halved compared to using one-side polarity pulses. Therefore, it is possible to use a low breakdown voltage element by reducing the power supply voltage in the circuit configuration.

[0004] In the above-described conventional technology that forms a sustain pulse with positive and negative pulses, the potential (Vs, _Vs) of the positive and negative pulses is symmetric. Therefore, under normal operating conditions, the address pulse potential (Va) and the positive sustain pulse potential (Vs) is different.

FIG. 10 shows an example of a drive circuit including the sustain circuit of the prior art, which is a prerequisite technique of the present invention, corresponding to the sustain pulse configuration, and FIG. 11 shows an example of the drive waveform. Figure 12 shows the power supply configuration. For example, the address pulse potential (Va) is + 65V and the positive sustain pulse potential (Vs) is + 85V.

Patent Document 1: JP 2002-62843 A

Disclosure of the invention Problems to be solved by the invention

[0006] In the prior art, while the sustain pulse height is halved, it is necessary to prepare two separate power supplies (Vs power supply 901, —Vs power supply 902) for the positive and negative pulses as the power supply for the sustain pulse. Therefore, there is a problem that the number of power supplies in the PDP device configuration increases, which has been a factor in increasing the cost of the PDP device.

[0007] It should be noted that in the technique disclosed in Japanese Patent Laid-Open No. 2002-62843 (Patent Document 1), a negative voltage is generated by using a single power capacitor for the external sustain pulse.

Will have substantial internal power.

[0008] The present invention has been made in view of the above problems, and an object of the present invention is to solve the above problems and reduce the number of power supplies for display driving of the PDP in the PDP device to reduce the cost. The aim is to provide a technology that can

Means for solving the problem

[0009] Outlines of representative ones of the inventions disclosed in the present application will be briefly described as follows. In order to achieve the above object, the present invention is a technique of a PDP device comprising a PDP and a drive circuit thereof, characterized by comprising the following technical means.

[0010] Typical settings in prior art PDP and power supply designs are address voltage Va = 65V and sustain voltage Vs = 85V. Therefore, the power supply cannot be shared while maintaining the positive and negative symmetry of the sustain pulse. Therefore, in the PDP device of the present invention, the configuration of the sustain pulse is shifted by 20V from the conventional one. By doing so, the voltage value of the address pulse and the positive sustaining noise can be made equal (85—2 0 = 65). This makes it possible to reduce the total number of power supplies by sharing the power sources for these pulses. Since it is desirable to reduce the address voltage Va as much as possible for reasons such as device breakdown voltage, the positive sustain pulse potential side is lowered to match the Va side.

In other words, with respect to the conventional X and Y sustain pulses, the positive / negative symmetry is broken and the center is shifted to the negative side. As a result, the positive sustain pulse potential (Vsl) is made lower than the conventional potential (Vs) and equal to the address pulse potential (Va). For example, the positive sustain pulse potential (Vsl) and address pulse potential (Va) are set to 65V, and the negative sustain The Norres potential is 65−2 X 85 = −105V. From common power supply (Vsl power supply) to positive sustain

In this PDP apparatus, for example, the PDP includes at least a first (X) electrode that serves as a sustain electrode (sustain discharge electrode), a second (Y) electrode, and a third (A) electrode that serves as an address electrode. Have The drive circuit applies an address pulse corresponding to the addressing pattern to the A electrode of the PDP, and applies a scan pulse to the Y electrode. In addition, the drive circuit applies a sustain pulse, which is a repetition force of positive and negative pulses, to the X and Y electrodes of the PDP so that the polarities of X and Y are reversed. The sustain pulse consists of repeating unit pulses of a positive pulse and a negative pulse with a reference potential (0V) as a boundary. The drive circuit includes a power supply (power supply circuit) for generating each pulse. The PDP apparatus is configured such that the positive pulse potential in the sustain pulse positive and negative pulses is equal to the address pulse potential.

[0013] In the PDP device, the first pulse (Vsl = Va) which is the voltage of the sustain pulse positive pulse and the address pulse is supplied from the common first power supply (Vsl power supply). The second voltage (Vs2 = Va-2Vs), which is the negative pulse voltage of the sustain pulse, is supplied from the second power supply (Vs2 power supply).

[0014] In this PDP device, the pulse heights of the positive and negative pulses in the sustain pulse are asymmetric, and the absolute value of the positive pulse potential (I Vsl I) is the absolute value of the negative pulse potential (I Vs2 It is configured to be smaller than I). The drive circuit applies a sustain pulse with a waveform in which X and Y have opposite polarities and a constant voltage is applied between X and Y in each unit pulse to the X and Y electrodes.

The invention's effect

[0015] The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. According to the present invention, it is possible to reduce the cost by reducing the number of power sources for PDP display driving in the PDP device.

Brief Description of Drawings

[0016] FIG. 1 is a diagram showing a configuration of a drive circuit centered on a sustain circuit in the PDP device according to the first embodiment of the present invention.

2] The subfield unit in the drive circuit of the PDP device according to the first embodiment of the present invention It is a figure which shows the structure of a driving waveform of a unit.

FIG. 3 is a diagram showing a power supply configuration in the drive circuit of the PDP device according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing an overall configuration centering on a drive circuit in the PDP device according to the first embodiment of the present invention.

FIG. 5 is an exploded perspective view showing a configuration example of a PDP in the PDP device according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a subfield method that is a driving method in the PDP device according to the first embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a drive waveform in a drive circuit of a PDP device according to a second embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a drive waveform in a drive circuit of a PDP device that is Embodiment 3 of the present invention.

FIG. 9 is a diagram showing a configuration of a drive waveform in a drive circuit of a PDP device that is Embodiment 4 of the present invention.

FIG. 10 is a diagram showing a configuration of a drive circuit centered on a sustain circuit in a conventional PDP device.

FIG. 11 is a diagram showing a configuration of drive waveforms in subfield units in a drive circuit of a conventional PDP device.

FIG. 12 is a diagram showing a configuration of a drive waveform in subfield units in a drive circuit of a conventional PDP device.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. 1 to 9 are for explaining an embodiment of the present invention. 10 to 12 are for explaining the prior art (a prerequisite technique of the present invention).

[0018] <Conventional Sustain Circuit and Drive Waveform> First, for comparison with the present embodiment, a driving circuit of a conventional PDP device will be described. Figure 10 shows an example of a sustain circuit in a conventional PDP device. Figure 11 shows an example of drive waveforms (drive voltage and ideal waveform) in a drive circuit including the sustain circuit. FIG. 12 shows a power supply configuration in the drive circuit.

In FIG. 10, a drive circuit such as an X sustain circuit 91, a Y sustain circuit (not shown), and an address circuit 93 is connected to the PDP 40 through electrodes and signal lines connected to the terminals of the capacitive load 10 of each cell. It is connected. The circuit of one cell unit is shown. The X sustain circuit 91 is connected to the capacitive load 10 of the PDP40 cell through the X electrode (X terminal) and the signal line 910. Similarly, the X side is connected to the X side through the Y electrode (Y terminal) and the signal line. A Y sustain circuit with the same configuration is connected. An address circuit 93 is connected to the capacitive load 10 of the cell through an address electrode and a signal line. An address pulse is applied by the address circuit 93 to the capacitive load 10 of the target cell in the PDP 40, and a sustain pulse is applied by the sustain circuit, thereby generating a sustain discharge. An X sustain pulse is applied to the X terminal of the capacitive load 10 by the X sustain circuit 91, and similarly, a Y sustain pulse is applied to the Y terminal by the Y sustain circuit.

[0020] Although the configuration of the Y-side circuit (Y sustain circuit) is omitted, the configuration is basically the same as that of the X-side circuit (X sustain circuit). However, a scan drive circuit (scan driver) is required on the Y side. The scan driver is necessary for address driving in the address period together with the address driver. Therefore, the Y sustain circuit is provided with a scan driver, or the scan driver is inserted between the Y sustain circuit and the capacitive load 10.

In the X sustain circuit 91, a Vs power source 901, which is a first power source, supplies a voltage Vs through a first signal line (power supply line) 911. A _Vs power source 902 as a second power source supplies a voltage −Vs through a second signal line (power supply line) 912. In the address circuit 93, a Va power source 931 that is a power source supplies an address voltage Va.

The switch elements (913, 914) are for switching the voltage (Vs, 1 Vs) applied to the capacitive load 10 through the signal lines (911, 912). Specifically, the switch elements (913, 914) are transistors. Configured. Vs is supplied by ◯ N of the first switch element 913, and the second switch element 914 Vs is supplied by turning ON.

[0023] The power recovery circuit 930 is a prior art, and is a circuit for starting / stopping a sustain pulse. In the power recovery circuit 930, a sustain pulse (positive pulse) to the capacitive load 10 is started up through the coil and diode element by the first switch element ○ N based on the ground, and the second switch The sustain pulse (negative pulse) to the capacitive load 10 falls through the coil and diode element due to the element N.

FIG. 11 shows the drive waveform in units of subfields (SF) in FIG. 1 and shows the address drive waveform (A), the X sustain drive waveform (X), and the Y sustain drive waveform (Y) from the top. 1 During the reset period (Tr), address period (Ta), and sustain period (Ts) in SF, each waveform is marked from each drive circuit to the corresponding electrode (terminal) of the capacitive load 10 of each cell. Added.

[0025] In this conventional driving waveform, the positive voltage (positive sustain panel voltage) in the X sustain pulse (X) is Vs. Since the positive and negative nodes are symmetrical, that is, the potential absolute value is the same for positive and negative pulses, the negative voltage (negative sustain pulse voltage) is -Vs. A positive sustain pulse voltage (Vs) force is applied to the X terminal of the capacitive load 10 through the first signal line 911 with a Vs power supply of 901 power. Also, a negative sustain pulse voltage (one Vs) is applied from the 1 Vs power source 902 to the X terminal of the capacitive load 10 through the second signal line 912. For example, Vs is +85 V and Vs is −85 V, for example.

[0026] In 1 SF, in the reset period (Tr), a predetermined reset pulse is applied to the X and γ electrodes in accordance with the prior art, thereby erasing residual charges and the like. Next, the address pulse (973) applied to the address electrode in the address period (Ta) is addressed by the unit pulse of the voltage (Va) having the potential of Va from the reference potential (0V) to the positive side. This is a pulse corresponding to the pattern.

[0027] Next, pulses (X and Y sustain pulses) applied to the X and Y electrodes in the sustain period (Ts) are positive norms (X and Y sustain pulses) each having a reference potential (0V) force and a Vs potential on the positive side. 9 71) and a negative pulse (972) with a potential of 1 Vs on the negative side. When a sustain pulse of opposite polarity is applied to X and Y, a voltage of 2Vs is applied to the capacitive load 10. FIG. 12 shows details of the power supply portion (901, 902, 931) in the conventional X sustain circuit 91. Note that only the portion having a large relationship is shown. In this power supply configuration, AC voltage is supplied from the AC (alternating current) power supply unit 961, and the AC voltage is converted into DC (direct current) voltage by the rectifier 962 including the AC / DC converter. Based on the DC voltage, the necessary DC voltage {Va, Vs, _Vs} is generated by the DC / DC converter unit 963 composed of a transformer wire.

[0029] (Embodiment 1)

FIG. 1 shows a drive circuit of PDP device 100 according to the first embodiment of the present invention. In the configuration of the first embodiment, the configuration of the power supply and voltage in the sustain circuit is different from the above-described conventional configuration. FIG. 2 shows drive waveforms (drive voltage and ideal waveform) in the drive circuit of the first embodiment. In this drive circuit and waveform, the positive sustain pulse height (positive sustain pulse voltage Vsl) and the address pulse height (address voltage Va) are equal. Therefore, in this configuration, the power supply is shared by the address circuit and the sustain circuit, and the total number of power supplies can be reduced as compared with the conventional technology configuration.

In FIG. 1, driving circuits such as the X sustain circuit 11, the Y sustain circuit 12, and the address circuit 13 are connected to the PDP 40 through electrodes and signal lines connected to the terminals of the capacitive load 10 of each cell. Has been. The circuit of one cell unit is shown. The X sustain circuit 11 is connected to the capacitive load 10 of the PDP40 cell through the X electrode (X terminal) and the signal line 110. Similarly, the same as the X side through the Y electrode (Y terminal) and the signal line The configured Y sustain circuit 12 is connected. An address circuit 13 is connected to the capacitive load 10 of the cell through an address electrode and a signal line. An address pulse is applied to the capacitive load 10 of the target cell in the PDP 40 by the address circuit 13 and a sustain node is applied by the sustain circuit, so that a sustain discharge is generated. The X sustain pulse is applied to the X terminal of the capacitive load 10 by the X sustain circuit 11 and the signal line 110, and the Y sustain pulse is similarly applied to the Y terminal by the Y sustain circuit 12 and the signal line 120.

[0031] In the drive circuit of the PDP 40, the configuration of the Y side circuit (Y sustain circuit 12) is basically the same as that of the X side, and is therefore omitted. Although not shown in the drawings, it is necessary depending on the drive waveform. A power supply (power supply circuit) for supplying a voltage. For example, in addition to the X sustain circuit 11, the Y sustain circuit 12, and the address circuit 13, in addition to the reset circuit (not shown), a pulse by a reset voltage is used. In this specification, a power supply circuit is included in the drive circuit.

[0032] In FIG. 1, the X sustain circuit 11 includes a first power source Vsl power source 101 (in other words, Va power source) and a second power source Vs2 power source 102 (in other words, Va_2Vs power source). Has two power supplies. The Vsl power supply 101 is a power supply shared by the X sustain circuit 11 and the address circuit 13 and supplies the same voltage to the address circuit 13. The address circuit 13 has a configuration that does not require the Va power source 931 that is conventionally required.

In the X sustain circuit 11, the Vsl power supply 101 supplies the voltage Vsl = Va to the X terminal of the capacitive load 10 of the cell through the first signal line (power supply line) 111. The Vs2 power supply 102 supplies the voltage Vs2 = (Va — 2Vs) to the X terminal of the cell capacity load 10 through the second signal line (power supply line) 112. The first signal line 111 and the second signal line 112 are connected to the signal line 110 to the cell via the switch elements (113, 114).

[0034] The switch elements (113, 114) are for switching the voltages (Vsl, Vs2) applied to the capacitive load 10 through the signal lines (111, 112), and are specifically composed of transistors. Is done. When the first switch element 113 is turned on, Vsl is supplied, and when the second switch element 114 is turned on, Vs2 is supplied.

[0035] The power recovery circuit 130 is configured as in the prior art, and is a circuit that raises / lowers the sustain pulse. The power recovery circuit 130 includes a ground 131, first and second switch elements (132, 135), first and second coils (133, 136), and first and second diode elements (134, 137). And connected to the signal line 110. When the first switch element 132 is turned on based on the ground 131, the sustain pulse (positive voltage) to the capacitive load 10 is passed through the first coin 133 and the first diode element 134 based on the ground 131. When the second switch element 135 is turned on, the sustain pulse (negative pulse) to the capacitive load 10 is lowered through the second coiner 136 and the second diode element 137.

[0036] X sustain pulse rise / rise by LC resonance in power recovery circuit 130 The power supply at that time may use the ground 131. In this case, it is not necessary to add another extra power source to the PDP device 100. The ground 131 serving as a power source for the power recovery circuit 130 is a power source intermediate between the Vsl power source 101 and the Vs2 power source 102.

In FIG. 2, the drive waveform of the first embodiment is shown in comparison with FIG. In the drive waveform of this embodiment, the positive voltage (positive sustain voltage) in the X sustain pulse (X) is the first sustain voltage: Vsl, and the negative voltage (negative sustain voltage) is Second sustain voltage: Vs2. Similarly, in the Y sustain pulse, the positive voltage is the first sustain voltage: Vsl, and the negative voltage is the second sustain voltage: Vs2.

[0038] The address voltage Va at A has a conventional waveform, and the positive potential of the sustain pulse voltage at X and Y (positive sustain pulse voltage Vsl) is the same as the potential of the conventional address voltage Va. The whole sustain is shifted from the reference potential (0V). The applied voltage by positive and negative nodes is 2Vs, which is the same as the conventional waveform. That is, in the X and Y sustain pulses, the positive and negative pulses are asymmetric and I Vsl I, I Vs I, I Vs2 I, Vsl = Va, and Vs2 = (Vsl-2Vs) = (Va-2Vs). . The other part of the waveform is the same as the conventional waveform (Fig. 11).

A positive sustain pulse voltage (Vsl) is applied from the Vsl power source 101 to the X terminal of the capacitive load 10 through the first signal line 111. Further, a negative sustain pulse voltage (Vs 2) is applied from the Vs 2 power source 102 to the X terminal of the capacitive load 10 through the second signal line 112. For example, Vsl is + 65V and Vs2 is -105V (when Va = 65V).

[0040] In 1SF, in the reset period (Tr), a predetermined reset pulse is applied to the X and Y electrodes in accordance with the prior art, thereby performing residual charge erasure and the like. Next, in the address period (Ta), an address pulse (73) having a potential of Va on the positive side is applied as in the prior art. In the same address period (Ta), a predetermined voltage (Vax) is applied in X, and a scan pulse with a predetermined voltage (Vay) is applied in Y.

[0041] Next, a pulse (X and Y sustain pulse) applied to the X and Y electrodes in the sustain period (Ts) is a positive pulse (71V) having a reference potential (0V) force on the positive side (Vsl potential). ) And a negative pulse with a potential of Vs2 on the negative side (72) Luz. By applying a sustain pulse of opposite polarity at X and Y, a voltage of 2VS is applied to the capacitive load 10.

FIG. 3 shows details of the power supply portions (101, 102) in the X sustain circuit 11 in the present embodiment. In this power supply configuration, an AC voltage is supplied from an AC (alternating current) power source 61, and the AC voltage is converted into a DC (direct current) voltage by a rectifier 62 including an AC / DC converter. Based on the DC voltage, the necessary DC voltage {Va, Va_2Vs} is generated by the DC / DC converter unit 63 composed of transformer wire.

4 to 6 show a basic configuration in PDP device 100 of the present embodiment. FIG. 4 shows a configuration example of a circuit including the drive circuit 30 for the PD P40. FIG. 5 shows an example of the configuration of the PDP 40 as an exploded perspective view in units of cells. FIG. 6 shows the subfield method, which is a standard driving method in the PDP device 100 configuration, and the configuration of the screen (referred to as a frame or field).

In FIG. 4, the PDP device 100 is configured to include a PDP 40 that is a display panel unit, a drive circuit 30, a control circuit 20, and the like. The drive circuit 30 is connected to the PDP 40, and the control circuit 20 is connected to the drive circuit 30. The drive circuit 30 including the control circuit 20 is sometimes called the drive circuit 30.

[0045] As a hardware configuration of the PDP device 100, for example, an IC or power supply circuit unit in which the back surface of the PD P40 is bonded to a chassis unit (not shown) and each circuit unit such as the control circuit 20 is mounted on the rear side of the chassis unit. Etc. have a PDP module. The circuit part on the rear side of the chassis part and the end part of the electrode of the PDP 40 are connected by a driver module corresponding to the drive circuit 30. The PDP module force S configured as described above is housed in an external housing, and a PDP device set is configured.

The control circuit 20 includes a display data control unit 21, a timing control unit 22, and the like. The control circuit 20 receives externally input interface signals {D (display data), CLK (dot clock), B (blanking signal), V (vertical synchronizing signal), H (horizontal synchronizing signal)}, etc. Based on this, a control signal for controlling the drive circuit 30 is formed, and thereby the drive circuit 30 is controlled. The control circuit 20 processes the display data (D) from the outside and stores it in the frame memory unit 23 of the display data control unit 21. The display data control unit 21 controls the supply of display data to the drive circuit 30. The timing control unit 22 generates a timing signal for controlling the display processing timing and supplies it to each circuit unit. The display data control unit 21 controls the address circuit unit 31 based on the display data (D) in the frame memory unit 23. Further, the address circuit unit 31, the X sustain circuit unit 32, and the Y sustain circuit unit 33 are controlled by the timing signal from the timing control unit 22, respectively.

[0048] The drive circuit 30 includes an address circuit unit 31 (corresponding to the address circuit 13), an X sustain circuit unit 32 (corresponding to the X sustain circuit 11), and a Y sustain circuit unit 33 (corresponding to the Y sustain circuit 12). ). The drive circuit 30 drives the electrode of the PDP 40 according to the control signal from the control circuit 20. The address circuit unit 31 drives the address electrode (data line) of the PDP 40 based on the display data (D) signal from the display data control unit 21. The X sustain circuit unit 32 drives the X electrode of the PDP40. The Y sustain circuit unit 33 drives the Y electrode of the PDP40. The Y sustain circuit unit 33 includes a scan driver, and thereby drives the Y electrode serving as a scanning electrode.

In FIG. 5, the PDP 40 is mainly composed of a substrate mainly composed of two glasses, a front substrate 41 and a rear substrate 42. The PDP40 is constructed by bonding the front substrate 41 side and the rear substrate 42 side so that they face each other via the partition wall 48, etc., and sealing and sealing the exhaust and discharge gas in that space. Is done.

[0050] The front substrate 41 is provided with a plurality of sets of first (X) electrodes and second (Y) electrodes substantially in parallel in the first direction. A sustain discharge is generated between the X and Y electrodes, which are display electrodes (sustain electrodes). For example, the Y electrode becomes the scan electrode. Each X, Y electrode is composed of, for example, a bus electrode and a transparent electrode. The bus electrode is a metal linear bar-shaped electrode that is electrically connected to the driver side. The transparent electrode is an electrode made of a ιτ〇 (indium tin oxide) layer film that is electrically connected to the bus electrode and forms a discharge slit. In this example, the X transparent electrode 51b and the transparent electrode 52b, and the X bus electrode 5la and the Y bus electrode 52a are formed in three dimensions with respect to the front substrate 41. The X and Y electrodes on the front substrate 41 are covered with a dielectric layer 43 and a protective layer 44.

[0051] Further, the rear substrate 42 has a third (A) in the second direction orthogonal to the X and Y electrodes (first direction). A plurality of address electrodes 47 as electrodes are arranged substantially in parallel. The address electrode 47 is covered with a dielectric layer 45. A display cell is formed by a region divided by the partition wall 48 and intersected by the Y-X electrode and the address electrode 47.

[0052] Between the front substrate 41 and the rear substrate 42, for example, a plurality of partition walls 48 are formed for forming regions divided into stripes in the vertical direction (second direction). The phosphor layer (46r, 46g, 46b) of each color of R, G, B is applied to the area divided by the barrier ribs 48 separately. A pixel is composed of a set of display cells of these colors. A form of a box-type cell in which a partition wall is provided in the lateral direction (first direction) is also possible.

[0053] In FIG. 6, one field corresponding to one display screen of the PDP 40: F (for example, 16.7 ms) is a plurality of time-division subfields (SF), n of SFl to SFn (n is for example 10) SF power. Each SF has a reset period (Tr), an address period (Ta), and a sustain period (Ts) in order. Each SF is weighted according to the sustain period (Ts), that is, the number of sustain discharges, and the gradation display of each cell is performed by the combination pattern of lighting / non-lighting of these SFs.

In the display drive of the PDP 40, first, the remaining charge is made uniform as the reset operation in the reset period (Tr), and then the address circuit 13 is used as the address operation in the address period (Ta). And by the drive from the Y sustain circuit 12, the discharge between the A and Y electrodes is performed, and the data memory in the lighting target cell is performed. As a sustain operation during the sustain period (Ts), the sustain discharge (repetitive discharge) is performed between the XY electrodes by driving from the X sustain circuit 11 and the Y sustain circuit 12, and discharge light emission occurs in the lighting target cell. To do.

[0055] According to the first embodiment, in the power supply configuration required for the display drive of the PDP 40 in the PDP device 100, the three power supplies (931, 901, 902) that have been conventionally required are replaced with the two power supplies (101 , 102), and Va and Vsl are set to low voltages, so that it is possible to reduce costs while using low-voltage elements in the device configuration.

[Embodiment 2]

As another embodiment, a configuration will be described in which a power supply voltage other than the sustain pulse in the drive circuit is applied in consideration of common power supply. Basic structure The configuration is the same as in the first embodiment.

FIG. 7 shows a drive waveform in drive circuit 30 of the second embodiment. In the second embodiment, in addition to the sustain pulse voltages (Vsl, Vs2) of the sustain circuit (11, 12) similar to the first embodiment, the first configuration (2-1) includes the reset period (Tr) The potential (Vrx) of the applied voltage (81) to the sustain electrode (X electrode) during the reset operation at is equal to the potential (Va) of the address pulse (73).

[0058] In the second configuration (2_2), the potential (Vry) of the applied voltage (82) to the Y electrode during the reset operation is made equal to the potential (Va) of the address pulse (73). Anyway. As a result, the number of power supplies used in the reset operation can be reduced as compared with the prior art.

[Embodiment 3]

FIG. 8 shows a drive waveform in the drive circuit 30 of the third embodiment. In configuration (3), the potential (Vax) of the voltage (83) applied to the X electrode during the address operation in the address period (Ta) is made equal to the potential (Va) of the address pulse (73). As a result, the number of power supplies used in the address operation can be reduced as compared with the conventional one.

[0060] (Embodiment 4)

FIG. 9 shows drive waveforms in drive circuit 30 of the fourth embodiment. In configuration (4), the voltage applied to the Y electrode during the address operation in the address period (Ta) (84), that is, the scan panel potential (Vay) is set to the potential on the negative pulse side of the sustain pulse (Vs2 = Va — Equal to 2Vs). As a result, the number of power supplies used in the address operation can be reduced as compared with the prior art. The above-described common power supply voltages in the embodiments can be combined.

As described above, according to each embodiment, it is possible to reduce the number of power supplies required for the display driving of the PDP 40 in the PDP device 100, thereby reducing the cost.

[0062] While the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

Industrial applicability

The present invention can be used for a display device such as a PDP device.

Claims

The scope of the claims

[1] A plasma display panel having at least a first electrode and a second electrode as sustain electrodes and a third electrode as an address electrode, and a sustain pulse composed of repetition of positive and negative pulses are supplied to the plasma display panel. A plasma display device having a drive circuit for applying an address pulse to the third electrode and applying an address pulse to the first electrode and the second electrode,

A plasma display apparatus, wherein a positive pulse potential and a potential of the address pulse in the sustain pulse positive and negative pulses are equal.

[2] The plasma display device according to claim 1,

The drive circuit supplies a first positive voltage for the sustain pulse and a first voltage for the address pulse from a first power source, and a second voltage for the negative pulse for the sustain pulse from a second power source. 2. A plasma display device that supplies a voltage of 2.

[3] The plasma display device according to claim 1,

The plasma display apparatus characterized in that the positive pulse potential absolute value in the sustain pulse is smaller than the negative pulse potential absolute value.

[4] The plasma display device according to claim 1,

The drive circuit includes a power recovery circuit that performs Z rising and falling of the sustain pulse,

A plasma display device characterized in that a power source at the time of LC resonance in the power recovery circuit is a ground.

[5] The plasma display device according to claim 1,

A plasma display device, wherein at least one potential of a sustain electrode held during a reset operation in a subfield is equal to a potential of the address pulse.

[6] The plasma display device according to claim 1,

A plasma display device, wherein a potential of a sustain electrode that is not a scan electrode during an address operation in a subfield is equal to a potential of the address pulse at least during a part of the address operation. [7] The plasma display device according to claim 1,

A plasma display device, wherein a potential of a scan pulse applied to a scan electrode during an address operation in a subfield is equal to a potential of a negative pulse of the sustain node.