WO2007029992A1 - Multiple-valued dram - Google Patents
Multiple-valued dram Download PDFInfo
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- WO2007029992A1 WO2007029992A1 PCT/KR2006/003610 KR2006003610W WO2007029992A1 WO 2007029992 A1 WO2007029992 A1 WO 2007029992A1 KR 2006003610 W KR2006003610 W KR 2006003610W WO 2007029992 A1 WO2007029992 A1 WO 2007029992A1
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- WIPO (PCT)
- Prior art keywords
- transistor
- bitlines
- dram
- drain
- word lines
- Prior art date
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/565—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using capacitive charge storage elements
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/02—Structural aspects of erasable programmable read-only memories
- G11C2216/08—Nonvolatile memory wherein data storage is accomplished by storing relatively few electrons in the storage layer, i.e. single electron memory
Definitions
- FIG. 1 is a diagram for explaining a universal lateral gate 100 in which a single electron transistor (SET) device and a metal-oxide-semiconductor (MOS) transistor are coupled to each other.
- SET single electron transistor
- MOS metal-oxide-semiconductor
- an MV multiple- valued
- the word line WL is enabled within a predetermined time before the data is destroyed due to loss of the electric charge.
- the storage node Vs of the cell and the gate of the SET transistor have the same voltage level. Accordingly, the voltage level of the storage node Vs is restored to a voltage level before the electric charge loss according to the Coulomb blockage characteristic of the SET device.
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Dram (AREA)
Abstract
Provided herein is an MV DRAM device capable of storing multiple value levels using an SET device. The device includes one or more word lines; one or more bitlines; a DRAM cell connected to intersections of the word lines and the bitlines; a current source transistor having a source connected to a power supply voltage and a gate and a drain connected to the bitlines; an SET (single electron transistor) device having a gate connected to the bitlines and a source connected to the ground voltage; and a transistor connected between the bitlines and the drain of the SET device, wherein the gate of the transistor is connected to the ground voltage. According to the MV DRAM device of the present invention, since two or more multiple value data are stored in a cell, it is possible to increase the storage density of the device. In addition, since the MV DRAM device only needs to enable the word lines in order to rewrite the data, thereby requiring only a small amount of current flow, it is suitable for a low-power application.
Description
Description MULTIPLE- VALUED DRAM
Technical Field
[1] The present invention relates to a semiconductor memory apparatus and more particularly, to a multiple-valued (MV) dynamic random-access-memory (DRAM) device capable of storing multiple value levels using a single electron transistor (SET) device. Background Art
[2] Recently, a research has been conducted on an SET. The SET has advantages of increasing the integration degree of a circuit and decreasing power consumption. The SET also has inherent characteristics that the drain current of the SET increases and decreases periodically according to a gate bias. Researchers have made an effort to increase functionality of a circuit with fewer transistors by using such characteristics. In particular, the SET device has been proven to have characteristics highly suitable for applications in a multiple- valued logic circuit and therefore, incessant efforts have been made to use the SET device for the multiple- valued logic circuit application.
[3] FIG. 1 is a diagram for explaining a universal lateral gate 100 in which a single electron transistor (SET) device and a metal-oxide-semiconductor (MOS) transistor are coupled to each other.
[4] Referring to FIG. 1, when a constant voltage Vgg is applied to the gate of a transistor Ml, the drain voltage Vds of the SET is maintained at a constant voltage equal to Vgg - Vth. Since the voltage Vgg - Vth is low enough to satisfy a Coulomb blockage condition, the SET shows characteristics that the drain current of the SET increases and decreases periodically according to an input voltage Vin. In this case, a constant current Io is supplied from a constant current source to the drain of the SET.
[5] When the input voltage Vin is changed so as to increase the drain current of the
SET to a current higher than the current Io supplied from the constant current source , the output voltage Vout will be rapidly decreased from a high level to a low level. On the other hand, when the input voltage Vin is changed so as to decrease the drain current of the SET to a current lower than the current Io supplied from the constant current source , the output voltage Vout will be rapidly increased from a low level to a high level.
[6] Therefore, when the input voltage Vin is increased, the output voltage Vout of the universal lateral gate 100 may have a square waveform with a high voltage swing.
[7] FIG. 2 is a diagram showing an exemplary circuit of a quantizer 200 using the universal lateral gate 100 of FIG. 1.
[8] Referring to FIG. 2, the constant current source provides a number of stability
points and the quantizer 200 operates in stable regions defined by dotted lines between two neighboring stability points. More particularly, when a clock signal CLK is enabled, an input voltage Vin is transferred to a storage node SN through a transistor M2 and quantized to a stability point corresponding to the voltage after the clock signal CLK is cut off. Accordingly, it is possible to obtain an input-output (Vin-Vout) voltage characteristic similar to a stepped waveform.
[9] The quantizer 200 having the SET device and the MOS transistor coupled to each other can be used for a memory application. In particular, since the quantizer 200 can store multiple level voltages without performing an additional refresh operation, it is highly effective in a multiple-valued static memory.
[10] FIG. 3 is a circuit diagram showing a DRAM type multiple- valued (MV) static random-access-memory (SRAM) using the quantizer 200 of FIG. 2.
[11] Referring to HG. 3, an MV SRAM cell 300 includes a first transistor Ml connected between an SET and a storage node SN and having a gate connected to the ground voltage; a second transistor M2 connected between a power supply voltage Vdd and the storage node SN and having a gate connected to the storage node SN; a third transistor M3 connected between a bitline BL and the storage node SN and having a gate connected to a word line WL; and a cell capacitor Cs connected between the storage node SN and the ground voltage. The first and second transistors Ml and M2 are depletion transistors and the third transistor M3 is an NMOS transistor.
[12] FIG. 4 is a timing diagram showing write and read operations of the MV SRAM shown in FIG. 3.
[13] Referring to FIG. 4, during a write operation, the word line WL is enabled at tθ.
After the word line WL is enabled, a voltage corresponding to a multiple logic value is applied to the bitline BL at tl. In order to store two bits in each cell, voltages having four different levels need to be applied to the storage node SN through the bitline BL. When corresponding voltage levels are transferred to the storage node SN, the word line WL is cut off at t2 and the bitline BL is precharged to the ground voltage at t3. Accordingly, the voltage levels stored in the storage node SN are maintained without being refreshed in accordance with the principle of the stability point of an operation of the quantizer 200 in FIG. 2.
[14] During a read operation, the word line WL is enabled at t4 and electric charges stored in the cell capacitor Cs are shared with a parasitic capacitor of the bitline BL. At t5, a sense amplifier is enabled so as to sense the multiple value levels.
[15] However, since the MV SRAM cell includes four transistors and one capacitor, the chip size of the MV SRAM cell is increased. A multiple- valued memory is advantageous in that it increases storage density by increasing the number of bits stored in a cell but disadvantageous in that it decreases the number of device used in the cell,
thereby defeating the advantages of the MV SRAM.
[16] FlG. 5 is a diagram showing a ITlC (1 transistor and 1 capacitor) cell of a DRAM.
[17] Referring to FlG. 5, when electric charges are stored in a storage node Vs of a cell capacitor Cs, data is stored in the storage node Vs. The DRAM has a structure in which parasitic capacitors exist in bitlines and word lines. When the data is read from the DRAM, the electric charges stored in the cell capacitor Cs are shared with the parasitic capacitor of the bitline and the voltage level of the bitline is sensed, thereby reading the data.
[18] FlG. 6 is a diagram for explaining a leakage current path viewed from the storage node Vs shown in FlG. 5.
[19] Referring to FlG. 6, the electric charges stored in the cell capacitor Cs are decreased due to a junction leakage current and a sub-threshold current. Therefore, the level of the electric charges stored in the cell capacitor Cs is decreased over time. Accordingly, a refresh operation needs to be performed before the data is destroyed due to loss of the electric charge.
[20] FIGS. 7 and 8 are diagrams showing a structure of a DRAM cell array and timings for a refresh operation.
[21] Referring to FIGS. 7 and 8, the word lines WL are sequentially enabled for every refresh period tref before the electric charges stored in the cell capacitor Cs of the DRAM are lost. Thereafter, the voltage levels stored in the bitlines BL are sensed and amplified using a sense amplifier S/A and data is rewritten, thereby completing the data refresh operation. However, in the DRAM, a large amount of electric current is consumed in order to charge and discharge a relatively large parasitic capacitor of the bitline. Since this consumed electric current increases a standby current, the DRAM is not suitable for a low-power application.
Disclosure of Invention Technical Problem
[22] The present invention is contrived to solve the above-mentioned problem. An advantage of the present invention is that it provides a multiple- valued (MV) DRAM device capable of storing multiple valued data other than binary data in a DRAM cell.
[23] Another advantage of the present invention is that it provides an MV DRAM device applicable to a low-power application by eliminating a sense amplifier for a refresh operation using a Coulomb blockage characteristic of a single electron transistor (SET) device. Technical Solution
[24] According to an aspect of the invention, there is provided an MV (multiple- valued)
DRAM device for storing multiple value levels, the device including: one or more
word lines; one or more bitlines; a DRAM cell connected to intersections of the word lines and the bitlines; a current source transistor having a source connected to a power supply voltage and a gate and a drain connected to the bitlines; an SET (single electron transistor) device having a gate connected to the bitlines and a source connected to the ground voltage; and a transistor connected between the bitlines and the drain of the SET device, wherein the gate of the transistor is connected to the ground voltage.
[25] In the embodiments of the present invention, the DRAM cell may include a cell transistor having a gate connected to the word lines and a drain connected to the bitlines; and a cell capacitor connected between the source of the cell transistor and the ground voltage.
[26] In the embodiments of the present invention, the SET device may include the source and the drain formed on a semiconductor substrate; a metal island disposed between the source and the drain so as to form a tunnel junction between the source and the drain; and the gate disposed in the vicinity of the metal island so as to control electric current flowing through the metal island.
[27] In the embodiments of the present invention, the transistor connected between the bitlines and the drain of the SET device is a depletion transistor that maintains the drain voltage level of the SET device at the ground voltage, and the current source transistor is a depletion transistor.
[28] In the embodiments of the present invention, data stored in the DRAM cell may be refreshed when the word lines are enabled.
[29] In the embodiments of the present invention, the MV DRAM device may further include a plurality of DRAM cells connected to intersections of a plurality of word lines and a plurality of bitlines, and the word lines are sequentially enabled at a predetermined period in order to refresh the DRAM cells.
[30] According to the MV DRAM device of the present invention, since two or more multiple value data are stored in a cell, it is possible to increase the storage density of the device. In addition, since the MV DRAM device only needs to enable the word lines in order to rewrite the data, thereby requiring only a small amount of current flow, it is suitable for a low-power application.
Brief Description of the Drawings
[31] The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which: [32] FIG. 1 is a diagram for explaining a universal lateral gate 100 in which a single electron transistor (SET) device and a metal-oxide-semiconductor (MOS) transistor are coupled to each other;
[33] FlG. 2 is a diagram showing an exemplary circuit of a quantizer 200 using the universal lateral gate shown in FlG. 1 ; [34] FlG. 3 is a circuit diagram showing a DRAM type multiple-valued (MV) static random-access-memory (SRAM) using the quantizer of FlG. 2; [35] FlG. 4 is a timing diagram showing write and read operations of the MV SRAM shown in FlG. 3;
[36] FlG. 5 is a diagram showing a ITlC (1 transistor and 1 capacitor) cell of a DRAM;
[37] FlG. 6 is a diagram for explaining a leakage current path seen from the storage node Vs shown in FlG. 5; [38] FIGS. 7 and 8 are diagrams showing a structure of a DRAM cell array and timings for a refresh operation; [39] FlG. 9 is a diagram showing an MV DRAM using an SET device according to an embodiment of the present invention; [40] FIG. 10 is a diagram showing exemplary voltage characteristics of a storage node
Vs in the case of the binary data and two bit multiple value data; [41] FlG. 11 is a diagram for explaining a refreshing method of an MV DRAM according to an embodiment of the present invention; [42] FlG. 12 is a diagram showing an MV DRAM cell array according to an embodiment of the present invention; and [43] FlG. 13 is a diagram for explaining a refreshing method of an MV DRAM cell array shown in FlG. 12.
Best Mode for Carrying Out the Invention [44] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the attached drawings so that those skilled in the art can easily put the invention into practice. However, the invention may be embodied in a variety of forms, but is not limited to the exemplary embodiments. Like reference numerals in the drawings denote like elements. [45] FlG. 9 is a diagram showing an MV DRAM using an SET device according to an embodiment of the present invention. [46] Referring to FIG. 9, in an MV DRAM 800, a plurality of unit cells 810, 820, and
830 are arrayed at intersections of word lines WL and bitlines BL. The unit cells 810,
820, and 830 include one transistor M3 and one capacitor Cs similar to the DRAM.
The bitline BL is connected to a current source transistor M2 for performing a refresh operation on the unit cells 810, 820, and 830. The bitline BL is also connected to an
SET device and a first transistor Ml. [47] The SET device includes a tunnel junction formed between a source and a drain of the SET device and a metal island disposed between the source and the drain. The gate
of the SET device is disposed in the vicinity of the metal island and controls electric current flowing through the metal island.
[48] In the unit cells 810, 820, and 830, multiple value data is stored unlike the DRAM where binary data is stored. In the binary data storing method, a cell can store only one bit. However, in the multiple value data storing method, a cell can store two or more data, thereby advantageously increasing the storage density of the device.
[49] FIG. 10 is a diagram showing exemplary voltage characteristics of a storage node
Vs in the case of the binary data and two bit multiple value data.
[50] Referring to FIG. 10, the binary data stored in the storage node Vs has a logic high value "1" or a logic low value "0". The logic low value "0" and the logic high value "1" correspond to the ground voltage level OV and a power supply voltage level Vcc, respectively.
[51] Whereas, the two bit multiple value data may have "00", "01 ", "10", and " 11 " value data. The "00", "01", "10", and "11" value data correspond to the ground voltage levels OV, 25OmV level, 50OmV level, and 75OmV level, respectively.
[52] FIG. 11 is a diagram for explaining a refreshing method of an MV DRAM according to an embodiment of the present invention.
[53] Referring to FIG. 11, in the OFF state of the word line WL, the electric charges stored in the cell capacitor Cs are decreased due to a junction leakage current or a subthreshold current of a transistor M3. Therefore, the level of the electric charges stored in the storage node Vs is decreased over time. Accordingly, a refresh operation needs to be performed before the data is destroyed due to loss of the electric charge.
[54] In order to perform a refresh operation, the word line WL is enabled within a predetermined time before the data is destroyed due to loss of the electric charge. When the word line WL is enabled, the storage node Vs of the cell and the gate of the SET transistor have the same voltage level. Accordingly, the voltage level of the storage node Vs is restored to a voltage level before the electric charge loss according to the Coulomb blockage characteristic of the SET device.
[55] In FIG. 11, it is assumed that the difference between the multiple value levels is
25OmV and the amount of current flow supplied from the current source transistor M2 is 10OpA. Moreover, it is assumed that the storage node Vs stores a voltage level of IV during the write operation. When a voltage loss of about 10OmV is occurred in the OFF state of the word line WL, the word line WL is re-enabled.
[56] Accordingly, the voltage level of the storage node SN is restored to IV level by the lOOpA current supplied from the current source transistor M2. When the voltage level of the storage node SN is completely restored to IV level, the word line WL is cut off and the corresponding voltage is stored. In this manner, the word lines are sequentially enabled before the data stored in the cell capacitor Cs is destroyed, thereby maintaining
the data stored in each cell.
[57] FlG. 12 is a diagram showing an MV DRAM cell array according to an embodiment of the present invention.
[58] Referring to FlG. 12, MV DRAM cells are arrayed at intersections of word lines
WL and bitlines BL. In addition, a current source transistor M2 for refreshing multiple value data, an SET device, and a transistor Ml for maintaining the drain voltage of the SET device are connected to each of the bitlines BL.
[59] FlG. 13 is a diagram for explaining a refreshing method of an MV DRAM cell array shown in FlG. 12.
[60] Referring to HG. 13, the word lines WL<0>, WL<1>, and WL<3> are sequentially enabled for every refresh period tref. It is desirable that the refresh period tref is set so as to prevent the data stored in the cell capacitor Cs from being destroyed. Therefore, the voltage level stored in the cell capacitor Cs is maintained.
[61] The MV DRAM refresh method according to the present invention is similar to the
DRAM refresh method known in the art. However, the refresh method according to the present invention only needs to enable the word lines in order to rewrite the data, thereby eliminating the sense amplifier for a refresh operation, which was required in the known refresh method, in which the sense amplifier needs to be operated after the word lines are enabled in order to rewrite the data.
[62] In addition, the known refresh method requires a large amount of current flow in order to refresh the data, whereas the refresh method according to the present invention requires only a small amount of current flow in order to rewrite the data. Accordingly, the MV DRAM refresh method according to the present invention is suitable for a low- power application.
Industrial Applicability
[63] According to the MV DRAM device of the present invention, since two or more multiple value data are stored in a cell, it is possible to increase the storage density of the device. In addition, since the MV DRAM device only needs to enable the word lines in order to rewrite the data, thereby requiring only a small amount of current flow, it is suitable for a low-power application.
[64] Although the exemplary embodiments of the invention have been described in detail, the invention is not limited to the exemplary embodiments, but it will be understood by those skilled in the art that various modifications, additions and substitutions are possible without departing from the scope and spirit of the invention as disclosed in the accompanying claims.
Claims
Claims
[1] An MV (multiple- valued) DRAM device for storing multiple value levels, the device comprising: one or more word lines; one or more bitlines; a DRAM cell connected to intersections of the word lines and the bitlines; a current source transistor having a source connected to a power supply voltage and a gate and a drain connected to the bitlines; an SET (single electron transistor) device having a gate connected to the bitlines and a source connected to the ground voltage; and a transistor connected between the bitlines and the drain of the SET device, wherein the gate of the transistor is connected to the ground voltage. [2] The device of claim 1, wherein the DRAM cell comprises: a cell transistor having a gate connected to the word lines and a drain connected to the bitlines; and a cell capacitor connected between the source of the cell transistor and the ground voltage. [3] The device of claim 1, wherein the SET device comprises: the source and the drain formed on a semiconductor substrate; a metal island disposed between the source and the drain so as to form a tunnel junction between the source and the drain; and the gate disposed in the vicinity of the metal island so as to control electric current flowing through the metal island. [4] The device of claim 1, wherein the transistor connected between the bitlines and the drain of the SET device is a depletion transistor that maintains the drain voltage level of the SET device at the ground voltage. [5] The device of claim 1, wherein the current source transistor is a depletion transistor. [6] The device of claim 1, wherein data stored in the DRAM cell is refreshed when the word lines are enabled. [7] The device of claim 1, further comprising a plurality of DRAM cells connected to intersections of a plurality of word lines and a plurality of bitlines, wherein the word lines are sequentially enabled at a predetermined period in order to refresh the DRAM cells.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/993,413 US8031512B2 (en) | 2005-09-09 | 2006-09-11 | Multiple-valued DRAM |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020050084298A KR100714823B1 (en) | 2005-09-09 | 2005-09-09 | Mutiple valued SRAM |
| KR10-2005-0084300 | 2005-09-09 |
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| WO2007029992A1 true WO2007029992A1 (en) | 2007-03-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| PCT/KR2006/003609 WO2007029991A1 (en) | 2005-09-09 | 2006-09-11 | Multiple-valued sram |
| PCT/KR2006/003610 WO2007029992A1 (en) | 2005-09-09 | 2006-09-11 | Multiple-valued dram |
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| PCT/KR2006/003609 WO2007029991A1 (en) | 2005-09-09 | 2006-09-11 | Multiple-valued sram |
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| KR (1) | KR100714823B1 (en) |
| WO (2) | WO2007029991A1 (en) |
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| KR100844947B1 (en) | 2007-01-16 | 2008-07-09 | 주식회사 엑셀반도체 | Multiple valued dynamic random access memory cell and thereof array using single electron transistor |
| KR100844946B1 (en) | 2007-01-16 | 2008-07-09 | 주식회사 엑셀반도체 | Multiple valued dynamic random access memory cell and thereof array using single electron transistor |
| KR101596034B1 (en) * | 2008-12-18 | 2016-02-19 | 충북대학교 산학협력단 | SET ULG Circuit and Method for controlling Single Electron Transistor Drain Voltage |
| KR101748726B1 (en) * | 2015-07-01 | 2017-06-19 | 엘에스산전 주식회사 | Constant voltage supplying circuit for circuit breaker |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5640350A (en) * | 1996-05-01 | 1997-06-17 | Iga; Adam Sempa | Multi-bit dynamic random access memory cell storage |
| US6246622B1 (en) * | 1999-07-30 | 2001-06-12 | Nec Corporation | Semiconductor memory device |
| US6282115B1 (en) * | 1999-12-22 | 2001-08-28 | International Business Machines Corporation | Multi-level DRAM trench store utilizing two capacitors and two plates |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR0141494B1 (en) * | 1988-01-28 | 1998-07-15 | 미다 가쓰시게 | High speed sensor system using a level shift circuit |
| US5677637A (en) * | 1992-03-25 | 1997-10-14 | Hitachi, Ltd. | Logic device using single electron coulomb blockade techniques |
| JP3179943B2 (en) * | 1993-07-12 | 2001-06-25 | 株式会社東芝 | Semiconductor storage device |
| JPH0830250A (en) * | 1994-07-20 | 1996-02-02 | Fujitsu Ltd | Document processor |
| US5889697A (en) * | 1997-10-08 | 1999-03-30 | Advanced Micro Devices | Memory cell for storing at least three logic states |
| US6538923B1 (en) * | 2001-02-26 | 2003-03-25 | Advanced Micro Devices, Inc. | Staircase program verify for multi-level cell flash memory designs |
-
2005
- 2005-09-09 KR KR1020050084298A patent/KR100714823B1/en active IP Right Grant
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2006
- 2006-09-11 WO PCT/KR2006/003609 patent/WO2007029991A1/en active Application Filing
- 2006-09-11 WO PCT/KR2006/003610 patent/WO2007029992A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5640350A (en) * | 1996-05-01 | 1997-06-17 | Iga; Adam Sempa | Multi-bit dynamic random access memory cell storage |
| US6246622B1 (en) * | 1999-07-30 | 2001-06-12 | Nec Corporation | Semiconductor memory device |
| US6282115B1 (en) * | 1999-12-22 | 2001-08-28 | International Business Machines Corporation | Multi-level DRAM trench store utilizing two capacitors and two plates |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2007029991A1 (en) | 2007-03-15 |
| KR20070029862A (en) | 2007-03-15 |
| KR100714823B1 (en) | 2007-05-07 |
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