WO2007023545A1

WO2007023545A1 - Memory device having redundancy repairing function

Info

Publication number: WO2007023545A1
Application number: PCT/JP2005/015416
Authority: WO
Inventors: Kenji Nagai
Original assignee: Spansion Llc; Spansion Japan Limited
Priority date: 2005-08-25
Filing date: 2005-08-25
Publication date: 2007-03-01
Also published as: US20070047342A1; US7706197B2; JP4652409B2; JPWO2007023545A1

Abstract

In a memory device having a memory cell array divided into a plurality of blocks and a redundancy repairing function performed on a block basis, a block address (BA) for specifying a block is input prior to an access operation to an individual cell in the block, and a block redundancy decision is performed on the input block address (BA). Therefore, it is not required to input a block address (BA) and perform a redundancy decision thereon each time access operation is performed. The time required to start the access operation to a memory cell can be shortened, thereby improving the access speed.

Description

Specification

Technical Field of Storage Device with Redundant Relief Function

TECHNICAL FIELD [0001] The present invention relates to a storage device having a redundancy repair function for a defective memory cell, and a control method for the storage device, and in particular, a storage in which redundancy repair is performed with an access control area for each of a plurality of memory cells as one unit. The present invention relates to a device and a storage device control method.

Background art

In the semiconductor device disclosed in Patent Document 1, the address control circuit 20 is suitable for a memory unit having eight blocks BLKO˜: BLK7 and two redundant blocks RDO˜RDl. Used. The block address to which the address pad force is also input is sent to the block address decoder 24 and the redundant block replacement determination circuit 26 via the address counter 22.

If the block address is not the address of a defective block, the redundant block use instruction signal HIT output from the redundant block replacement determination circuit 26 becomes “L” level. Control is performed so that only the block corresponding to the above block address is selected by the block selection control unit 30.

When the block address is an address of a defective block, the redundant block use instruction signal HIT output from the redundant block replacement determination circuit 26 is at “H” level. Block selection unit 30 forces blocks BLK0 to BLK7 to be unselected. A redundant block to be replaced with the defective block address is selected.

Patent Document 1: Japanese Patent Application Laid-Open No. 2003-77293 (FIG. 1)

Disclosure of the invention

Problems to be solved by the invention

However, in the semiconductor device described in Patent Document 1, address information including a block address is input from the address pad and sent to the redundant block replacement determination circuit 26 for each access. In the redundant block replacement judgment circuit 26, any of the 8 blocks BLKO ~: BLK7 specified by the block address is a bad block Whether or not is determined. When it is determined that the block is defective, replacement is performed with one of the two redundant blocks RDO to RDl.

[0007] For each access, the block specified by the input block address must be replaced with a redundant block, and the access operation cannot proceed during the replacement determination.ヽ. The access time includes the replacement judgment time for the redundant block, and when the access start time is shortened, the replacement judgment time may be a problem.

Means for solving the problem

[0008] The present invention has been made in view of the background art described above. When an access control area is defined for each of a plurality of memory cells and redundant relief is performed with the access control area as a unit, the access control area is It is an object of the present invention to provide a storage device and a storage device control method in which the access start time is shortened by performing redundancy determination prior to the access operation to the individual memory cell to which it belongs.

[0009] The storage device control method of the present invention made to achieve the above object is a method for controlling a storage device having a redundant relief function in which a memory cell array is partitioned into a plurality of blocks and the block is a unit of access control. A method comprising: a step of inputting a block address designating at least one block prior to an access operation to an individual memory cell; and a step of performing redundancy determination on the input block address. To do.

[0010] In the storage device control method of the present invention, at least one block is provided prior to the access operation to the individual memory cell, with respect to a storage device including a plurality of blocks having a redundant relief function as one unit of access control. Enter the specified block address and perform redundancy judgment.

The memory device of the present invention is a memory device in which a memory cell array is partitioned into a plurality of blocks, and the block is regarded as one unit for access control and has a redundant relief function, and prior to an access operation to an individual memory cell. A first block address buffer that stores at least one input block address according to a dedicated command cycle, and a block redundancy determination unit that performs block address redundancy determination according to the block address input. It is characterized by that.

In the storage device of the present invention, for a storage device including a plurality of blocks having a redundancy relief function as one unit of access control, the first block is set in accordance with a dedicated command cycle prior to the access operation to the individual memory cell. At least one block address is stored in the address buffer, and the block redundancy determination unit determines the redundancy of the block address in response to the input of the block address.

The invention's effect

[0013] Thereby, prior to the access operation to the individual memory cells in the block, the block address is input, and redundancy determination for the input block address is performed. At the start of access to an individual memory cell, the necessity of block redundancy has already been completed, and redundancy relief has been completed when redundancy is required. For this reason, it is not necessary to determine the redundancy for the block to be accessed every time an access operation is performed on the memory cells in the selected block. Access request power The time required to start an access operation can be shortened.

In addition, since the block address is input prior to the start of access to the individual memory cell, the block address is input to the address terminal or data input used when starting the access to the individual memory cell, Z and output terminal force can be performed. It is possible to reduce the number of terminals in a storage device that does not require a dedicated address terminal for block address input.

Brief Description of Drawings

FIG. 1 is a circuit block diagram of an embodiment.

FIG. 2 is a diagram showing commands for setting a block address.

FIG. 3 is a circuit example of a block address buffer.

FIG. 4 is a timing chart when setting a block address.

FIG. 5 is a circuit diagram of an address switching buffer that controls switching of address settings during suspend and resume.

[Fig. 6] Timing chart for suspend and resume.

Explanation of symbols 1 = i mand, de: n—da

3 Block address buffer (BAB)

5 Bad block address buffer

7 Redundancy judgment unit

9 Block address decoder

11 Redundant block address decoder

13 Address switching buffer

B block

MA main memory cell array

RB redundant block

RMA redundant memory cell array

ACLK timing signal

BA block address

BAL block address latch signal

BASET Block address set signal

ERS erase command

RED match judgment signal

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, a specific embodiment of a storage device and a control method for the storage device of the present invention will be described in detail with reference to the drawings based on FIG. 1 to FIG.

In the memory device of the present invention, in response to inputting information for accessing the memory cell from the external terminal of the memory device, an external access operation for outputting the memory cell information to the external terminal, and from the external terminal of the memory device to the memory cell Internal access operation that inputs information to be accessed but does not output memory cell information to external pins. The external access operation is a read access operation that inputs an address and outputs memory cell information, and the internal access operation is an erase operation such as a flash memory that is a nonvolatile storage device, a program operation, or a volatile storage device. This applies to a refresh operation of a DRAM or the like.

In FIG. 1, a memory cell array MA has a memory cell area for each predetermined number of memory cells. It is partitioned into a block B. A redundant memory cell array RMA is provided adjacent to the memory cell array MA. In the redundant memory cell array RMA, a redundant block RB, which is a redundant memory cell area, is provided for each predetermined number of redundant memory cells. Block B containing the defective memory cell is replaced with redundant block RB. This configuration has a so-called block redundancy function.

FIG. 1 shows an example of a circuit configuration in which a block address BA required for an external access operation is input prior to an access operation to each memory cell and redundancy determination is performed in advance. .

[0020] The data input / output terminal (IO) and the address terminal (ADD) are connected to the command decoder 1. In the command cycle, various commands to which data input / output terminal (IO) or Z and address terminal (ADD) force is also input are decoded. The data input / output terminal (IO) is connected to the block address buffer (BAB) 3. As will be described later, in the command cycle, the block address to which the data input / output terminal (IO) force is also input is stored in the block address buffer (BAB) 3. The storage timing is performed according to the block address set signal BASET output from the command decoder 1.

[0021] As described later, the block address set signal BASET, together with the block address input from the data input / output terminal (IO) by the command cycle, the data input / output terminal (IO) or Z and address terminal (ADD) ) Force Input command signal is output as a result of decoding.

The block address set signal BASET is also input to the redundancy judgment unit 7 as a redundancy judgment timing signal at the same time. The redundancy judgment unit 7 receives the block address BA from the block address buffer (BAB) 3 and the bad block address FBA stored in advance in the bad block address buffer 5. In response to the block address set signal B ASET, it is determined whether or not the block address BA matches the bad block address FBA. If the block address BA matches the defective block address FBA as a result of the redundancy determination, the high-level match determination signal RED is detected. If the block address BA does not match, the low-level match determination signal RED is sent from the redundancy determination unit 7 to the block address decoder. 9 and output to the enable terminal (EN) of the redundant block address decoder 11. In this case, the block address decoder 9 is activated when a low level signal is input to the enable terminal (EN), and the redundant block address decoder 11 is activated at the enable terminal (EN). , It is activated when a high level signal is input.

That is, the block address BA is input to the block address decoder 9 in response to the low level coincidence determination signal RED, and the block B in the memory cell array MA is selected as the decoded signal YD. In response to the high level coincidence determination signal RED, the redundant block address RBA output from the redundancy determining unit 7 and input to the redundant block address decoder 11 is decoded, and the redundant block in the redundant memory cell array RMA is decoded as the redundant decoded signal RYD. RB is selected.

[0025] According to the block address set signal BASET output from the command decoder 1 in the command cycle, the block address is stored in the block address buffer (BAB) 3, and the redundancy judgment unit 7 Redundancy determination is performed at. As a result, the block B to be accessed is already determined in the block address buffer (BAB) 3 during the access operation. Furthermore, redundancy determination for the stored block address BA is completed, and the access target is redundantly repaired to the redundant block RB as necessary. The access operation is performed on the block B corresponding to the stored block address B A or on the redundant block RB subjected to redundancy repair. Here, the block address buffer (BAB) 3 is an example of a first block address buffer, and the redundancy determining unit 7 is an example of a block redundancy determining unit.

Here, although not shown in FIG. 1, a memory cell is determined by an address for selecting a word line or the like in the block and an address decoder. It is not necessary to input and decode the block address BA for each access operation, and it is not necessary to perform redundancy judgment processing. It is possible to shorten the time until the memory cell access operation starts, and to improve the access speed. A memory controller (not shown) of a memory system equipped with these storage devices only needs to issue a command cycle for setting a block address BA, which will be described later, in the memory cell array area that is accessed externally. As long as a certain block address BA does not change, it is only necessary to input an arbitrary address in that block for each access operation. It can be assigned to processing time for selecting a block different from the block that is performing the operation. In other words, the memory controller can speed up the process of determining the block address for changing a block that does not need to keep the block address BA in the memory controller, thereby increasing the speed of the system.

FIG. 2 is a diagram showing a command system for setting the block address BA. This command sets the block B to be accessed in the series of subsequent access operations in the command cycle prior to the access operation to each memory cell. The command and block address BAin are input according to the combination of signals input from the address terminal (ADD) and data input / output terminal (IO).

[0028] First, a 3-cycle signal set is input as an entry command. In the first cycle, the address terminal (ADD) force is also input with a code of 555h, and the data input / output terminal (IO) force is input with an AAh code. In the second cycle, the code from the address terminal (ADD) to 2AAh and the data input / output terminal (IO) force are also 55h code, and in the third cycle, the address terminal (ADD) force is 555h code and data input. Input 93h code for output terminal (IO) force. Combining power of these codes It is recognized that command decoder 1 has decoded and entered the command cycle of block address BAin.

Next, the block address BAin is input by a write command. In the first cycle, the address terminal (ADD) force is XXh code and the data input / output terminal (IO) force is AOh code. In the second cycle, the address terminal (ADD) force is OOh code and data. Input block address BAin from I / O terminal (IO). As a result, the command decoder 1 recognizes the signal input from the data input / output terminal (IO) in the second cycle as the block address BAin, and fetches the block address BAin into the block address buffer (BAB) 3. Issue block address set signal BASET.

[0030] Further, it is an idid command. In the first cycle, the address pin (ADD) force XXh code and the data input / output pin (IO) force code 90h, and in the second cycle the address pin (ADD) force XXh code and data input. Input the 00h code from the output terminal (IO). Combining power of these codes It is recognized by the command decoder 1 that it has been decoded and exited from the command cycle of the block address BAin. FIG. 3 is a circuit example for storing one bit of the block address buffer (BAB) 3. The transfer gate T1 is conduction controlled by the block address set signal BASET and the inverted signal from the inverter gate II. The transfer gate T1 is connected between the data input / output terminal (IO) and the latch circuit L1. The output of the latch circuit L 1 is output as the block address BA via the inverter gate 12.

In response to the high level block address set signal BASET, the transfer gate T1 becomes conductive and is taken into the block address BAin force latch circuit L1 inputted to the data input / output terminal (IO). In the subsequent access operation, since the block address set signal BASET is maintained at the same level, the contents of the latch circuit L1 are retained and the state where the block address BA is output via the inverter gate 12 is maintained. The block address BA information of the latch circuit L1 is maintained until the aforementioned entry command Z write command is input.

FIG. 4 is a timing chart of a command cycle for setting the block address BA. Command code power described in Fig. 2 Write enable signal This signal is issued in synchronization with the ZWE low level signal. The entry command is decoded by the command decoder 1, and the block address set mode signal BAB-mode changes to high level. It is informed that it is in the block address set command state. Next, a 2-cycle block address BAin write command is issued in synchronization with the low level signal of the write enable signal ZWE. The write command is decoded by the command decoder 1, and the block address set signal BASET is issued as a high level pulse signal. The block address BAin input to the data input terminal (IO) is taken into the block address buffer (BAB) 3, and the block address BA is held. After the block address BA is held, it is issued in synchronization with the low-level signal of the two-cycle exit command power write enable signal ZWE. The Idagit command is decoded by the command decoder 1, and the block address set mode signal BAB-mode goes low. The block address set command state ends.

FIG. 5 is a circuit diagram of the address switching buffer 13 that controls switching of address settings during suspend and resume. In the circuit block diagram of Figure 1, the block address buffer It is provided between (BAB) 3 and the block address decoder 9. A circuit that performs address switching control when a normal access operation that is an external access operation for block B indicated by block address BA is interrupted during a continuous access operation that is an internal access operation that goes beyond the block. It is.

In the continuous access operation, regardless of the block address BA stored in the block address buffer (BAB) 3, the block addresses necessary for the internal access operation are sequentially increased or decreased. This is because the access operation continues beyond the block. On the other hand, in a normal access operation, the block address BA of the block B to be accessed is stored in the block address buffer (BAB) 3 in advance, and the block B accessed according to this block address BA is It has been decided. Therefore, the block address must be switched when a suspend command is entered to pause the continuous access operation and return to the normal access operation, or a resume command is issued to cancel the pause and return to the continuous access operation.

The address switching buffer 13 in FIG. 5 is configured by taking a nonvolatile storage device as an example of a storage device. That is, the continuous access operation is configured as an erase operation in units of blocks. The configuration of the inverter gate 111, the transfer gate Tll, the latch circuit Lll, and the inverter gate 121 is the same as that of the block address buffer (BAB) 3 (see FIG. 3). Block address latch signal BAL and block address BA are input instead of block address set signal BASET and block address BAin in block address buffer (BAB) 3, and block address BA in block address buffer (BAB) 3 is replaced The internal block address intBA is output. Here, the block address latch signal BAL is a signal that outputs a high-level pulse signal when the block address BA is loaded into the address switching buffer 13. When a block address is set in the command cycle, a pulse is output when a suspension command is issued during a normal access operation or during a continuous access operation.

[0037] Counter C, inverter gate 112, and transfer gate T12 are provided, and transfer gate T12 controls conduction between counter C and latch circuit L11. During an erase operation, which is a continuous access operation, transfer gate T12 is turned on by the high level erase command ERS and the signal inverted by inverter gate 112, and the output of counter C is output. The signal is sent to the latch circuit LI 1. Here, the counter C is a normal binary counter and outputs a bit signal that is sequentially incremented according to the timing signal ACLK. The timing signal ACLK is a signal that is issued upon completion of the erase operation for each block.

Here, the counter C is an example of a second block address buffer, and the inverter gates II 1 and 112 and the transfer gates Tl 1 and T 12 are examples of a switching unit.

FIG. 6 is a timing chart showing address switching control including the erasing operation which is a continuous operation and its suspend command.

[0040] When the set command (SET BA) of the block address ΒΑ is instructed, the data input / output terminal (IO) force is also input with "2" or "6" as the block address. At the same time, the block address set signal BASET generates a high level pulse signal. As a result, the block address BA is set to “2” or “6”. At the same time, the block address latch signal BAL generates a high level pulse signal. The block address BA is taken into the address switching buffer 13 (Fig. 5), "2" or "6" is output as the internal block address intBA, and redundancy judgment is performed here.

[0041] When a read command (READm, n) is commanded as a normal access operation, "m" and "n", which are addresses within the block, are also input to the address terminal (ADD) force. In this case, the internal block address intBA maintains "2"! /, So the block to be accessed is unchanged. For the access time of each read command (READm, n), block B to be accessed has already been determined, and redundancy determination has already been completed, so the word line in the selected block is activated at high speed. The memory cell data information can be output to the external terminal of the storage device at high speed.

[0042] When an erase command (ERS), which is a continuous access operation, is commanded, the address switching buffer 13 is latched with the power counter C via the transfer gate T12 in response to the high-level erase command ERS! Circuit L11 force S connected. In response to the timing signal ACLK, the output signal of the counter C that is incremented sequentially from "0" is output as the internal block address intBA.

[0043] When the suspend command (ESUS) is commanded during the erase command (ERS), the block address latch signal BAL generates a high level pulse signal and the erase command ERS. Becomes low level. In the address switching buffer 13, instead of the counter C, the block address BA is sent again to the latch circuit L11. "2" is set again as the internal block address intBA, and redundancy judgment is performed here. Thereafter, when a read command (REA Dn, o) is commanded, a read operation is performed on addresses “n” and “o” in the block corresponding to the block address BA (“2”). For each access time of the read command (READn, o), the block B to be accessed has already been determined and the redundancy judgment has already been completed, so the word line in the selected block is activated at high speed. The memory cell data information can be output to the external terminal of the memory device at high speed. During this time, since the erase operation is temporarily suspended, the timing signal ACLK does not change, and the content of the counter C maintains “j” which is the address before the suspend command (ESUS) is input.

[0044] When the read command (R EADn, o) by the suspend command (ESUS) in the erase command (ERS) is completed and a resume command (ER SM) is issued to return to the erase command (ERS) The erase command ERS goes high again. At this time, the block address latch signal BAL is maintained at a low level. In the address switching buffer 13, the contents of the counter C are sent again to the latch circuit LI 1 instead of the block address BA. The internal block address intBA is again set to a value that increments sequentially from "j" according to the timing signal ACLK.

[0045] After the erase operation of the block corresponding to the final block "3FF" as the block address, when the block address latch signal BAL issues a high level pulse signal, the block address BA is latched in the address switching buffer 13 Sent to L11. "2" is reset as the internal block address intBA and redundancy is determined here, and the normal access operation is resumed. When a read command (READp, q) is issued, “p” and “q”, which are addresses in the block, are input from the address terminal (ADD). In this case, since the internal block address intBA has already been reset to "2", the block to be accessed is unchanged. Read operation is performed for addresses "p" and "q" in the block according to block address BA ("2"). For the access time of each read command (READp, q), the block B to be accessed has already been confirmed, and the redundancy judgment has already been completed. Therefore, the word line in the selected block can be activated at high speed, and the memory cell data information can be output to the external terminal of the storage device at high speed.

As is apparent from the above description, according to the present embodiment, the block address BA is input and the input block address BA is input in the command cycle prior to the access operation to the individual memory cell in the block B. Redundancy determination is performed for. At the start of access to individual memory cells, the necessity of block redundancy and redundancy relief have already been completed. For this reason, it is not necessary to make a redundancy decision for the target block B every time a memory cell in the selected block B is accessed. Access demanding power It is possible to shorten the time required to start the access operation.

[0047] Since the block address BA is input prior to the start of access to an individual memory cell, the input of the block address BA is used as an address terminal ( ADD) and data input / output terminal (IO) force can also be performed. It is possible to reduce the number of terminals in a storage device that does not require a dedicated address terminal (ADD) for the input of the block address BA.

It goes without saying that the present invention is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the spirit of the present invention.

For example, in Figure 2, the power to show the command system for setting the block address is an example. Needless to say, the combination of the number of cycles, each code, the terminals to be used, etc. can be set as appropriate!

When the address switching buffer 13 is arranged, the output intBA is preferably input to the redundancy judgment unit 7 together with the block address decoder 9. This is because redundant sector determination operation is necessary even for internal access operation, and this method is simple. The counter C is not limited to a neutral counter, and the initial value of the counter C can be input from a predetermined address as well as an external force of the storage device. Also, the address range where counter C operates can be set arbitrarily.

In addition, the continuous address operation does not need to execute all the blocks in the storage device in succession. Or it is not restricted to implementing a logical adjacent block continuously.

Further, the effect of the present invention is not limited to the high-speed key for selecting a word line, which is a row selection, but is also effective for the high-speed key for column selection in a storage device using a flexible redundancy technique. Figure

This is because in the case of flexible redundancy straddling a vertical block row in one column direction, the force to select which vertical block can be determined when a dedicated command cycle prior to the access operation to the individual memory cell is set. .

Claims

The scope of the claims

[1] A method for controlling a storage device in which a memory cell array is partitioned into a plurality of blocks, and the block is used as a unit for access control, and a redundant relief function is provided.

Prior to the access operation to the individual memory cell,

A method for controlling a storage device, comprising: inputting a block address designating at least one of the blocks; and performing redundancy determination for the input block address.

[2] The step of inputting the block address is performed in a dedicated command cycle. The block address is input to a data input / output terminal or Z and the address of a memory cell arranged in the block. 2. The storage device control method according to claim 1, wherein the storage device is input from an address terminal.

3. The storage device control method according to claim 1, further comprising a step of holding the input block address.

[4] holding the block address;

Holding a sequential block address indicating the block to be accessed in a continuous access operation performed across the block, and

Selecting the block address that is held when the continuous access operation is paused, and selecting the held sequential block address when the continuous access operation is resumed. The method for controlling a storage device according to claim 1.

[5] A memory device in which a memory cell array is partitioned into a plurality of blocks, and the block is used as a unit for access control and has a redundant relief function,

A first block address buffer for storing at least one input block address in response to a dedicated command cycle prior to an access operation to the individual memory cell; and a redundancy of the block address in response to the input of the block address. A storage device comprising: a block redundancy determination unit that performs determination.

[6] In a continuous access operation performed beyond the block, a second block address buffer that variably stores a sequential block address indicating the block to be accessed; A switching unit that selects the first block address buffer in an access operation performed in the block, and selects the second block address buffer in a continuous access operation performed across the block. The storage device according to claim 5.