JP4073330B2 - Nonvolatile semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device, and is particularly suitable for use in a nonvolatile semiconductor memory device capable of electrically writing and erasing data, such as a flash memory.
[0002]
[Prior art]
A nonvolatile semiconductor memory device such as a flash memory has a chip batch erase function that can electrically write and erase data and automatically erases data stored in memory cells for all memory cells through a series of operations. Generally have. The memory cell array of the nonvolatile semiconductor memory device is composed of a plurality of blocks, and each block is composed of a plurality of memory cells.
[0003]
The erase operation in the chip batch erase described above is executed in units of the smallest block capable of batch erase, and when the data erase in a certain block is completed, the data erase in the next block is automatically started. The chip batch erase automatically erases data stored in all memory cells by executing this data erase operation for all blocks.
[0004]
[Patent Document 1]
JP 2001-195892 A
[0005]
[Problems to be solved by the invention]
However, in the conventional nonvolatile semiconductor memory device, when there is a defective memory cell in which data cannot be erased in a block during the chip batch erase operation (hereinafter, this block is referred to as a “defective block”). Repeat the data erasing operation on the bad block. That is, the nonvolatile semiconductor memory device cannot complete the data erasing operation in the defective block, and cannot execute the data erasing operation in the blocks after the defective block.
[0006]
Therefore, in the function test of the nonvolatile semiconductor memory device, it is necessary to be able to forcibly terminate the chip batch erase operation when the nonvolatile semiconductor memory device to be tested has a defective block. In the functional test of the nonvolatile semiconductor memory device, a time limit for allowing the chip batch erase operation is set on the test device (tester) side, and the test device determines whether the chip batch erase operation is completed within the time limit. To do. If the result of the determination is that the chip batch erase operation has not been completed, the test apparatus determines that a defective block exists in the nonvolatile semiconductor memory device, and forcibly terminates the operation of the test target nonvolatile semiconductor memory device Let
[0007]
Here, the time limit set on the test device side is the time limit (per one minimum block) allowed for data erasure in the minimum block that can be erased at once, and the above-mentioned minimum number of blocks that the nonvolatile semiconductor memory device has. Is the product of Therefore, when the nonvolatile semiconductor memory device has a large capacity with a large number of blocks, the time limit set on the test device side becomes very long. Therefore, if even one non-volatile semiconductor memory device has a defective block, the test device cannot forcibly terminate the chip batch erase operation until the set time limit elapses, and a large amount of time is spent for the function test. It was necessary.
[0008]
Further, in a system equipped with a nonvolatile semiconductor memory device, information about which block of the nonvolatile semiconductor memory device is a defective block cannot be obtained when the chip batch erase operation is not completed. Therefore, in the system, it was impossible to avoid a defective block of the nonvolatile semiconductor memory device and use it, and the mounted nonvolatile semiconductor memory device had to be replaced.
[0009]
In addition, as another method for enabling the chip batch erase operation to be completed when the nonvolatile semiconductor memory device has a defective block, Patent Document 1 does not confirm whether data is erased in the defective block. Thus, there is disclosed a method of preventing the data erasing operation from being repeated, and executing and ending the chip batch erasing.
[0010]
The present invention has been made in view of such a problem, and an object of the present invention is to enable a chip batch erase operation to be efficiently performed even when a defective memory cell exists in a nonvolatile semiconductor memory device. A second object of the present invention is to enable the supply of information related to a defective block in which a defective memory cell exists in a nonvolatile semiconductor memory device to the outside.
[0011]
[Means for Solving the Problems]
A nonvolatile semiconductor memory device according to the present invention includes a memory cell array having a plurality of blocks composed of a plurality of memory cells, an erasing unit, and a setting unit, and blocks data stored in all memory cells of the memory cell array by the erasing unit. 1 block set when batch erasing every time ,in this case, When erasure of data stored in the memory cells constituting the block is not completed within the erasure operation allowable time, the erase operation in the block is terminated.
Further, a storage unit is provided for each block, and a signal indicating quality information indicating whether or not the erase operation for the block is completed within the execution allowable time is stored. And an output means, and after the erase operation in all blocks is completed, Based on the pass / fail information stored in the storage means, all the memory cells A signal indicating whether or not the stored data has been erased is output.
According to the present invention configured as described above, the erase operation in the block in which the defective memory cell exists is forcibly terminated in the execution allowance time of one block unit, and the erase operation in the next block is started. Will be able to.
[0012]
In addition, information such as whether or not the nonvolatile semiconductor memory device has a defective block and which block is a defective block can be obtained.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a block diagram showing a configuration example of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. The nonvolatile semiconductor memory device according to the first embodiment is a semiconductor memory device capable of writing and erasing in block units such as a flash memory and an EEPROM (Electrically Erasable and Programmable Read only Memory).
[0014]
In FIG. 1, reference numeral 1 denotes an address buffer, which receives an address signal ADD from the outside and outputs the input signal to a block / row decoder 5 and a column decoder 6. Further, when a command such as an erase operation is input by the address signal ADD, the address buffer 1 outputs a signal corresponding to the command to the control circuit / sequencer 2.
[0015]
The control circuit / sequencer 2 receives a control signal CTL from the outside and a signal corresponding to a command from the address buffer 1 and controls each functional unit based on the input signal and the like. For example, the control circuit / sequencer 2 applies an erasing pulse for collectively executing a data erasing operation for each block to the memory cell array, or performs an operation for confirming whether or not data has been erased (verify operation). To go.
[0016]
The timer 3 is set by the control circuit / sequencer 2 for a time limit for allowing the data erasing operation in the chip batch erasing. Here, the set time limit is a time that allows execution of a data erasing operation in units of blocks that can be collectively erased, that is, an allowable time for executing an erasing operation per block. The timer 3 measures the elapsed time from the start of the data erasing operation in the chip batch erasing operation for each block, and if the elapsed time exceeds the set allowable execution time, the control circuit / sequencer 2 Notify that.
[0017]
It should be noted that the number of erase pulses allowed per block that can be erased at once is set in the timer 3 instead of the allowable execution time, and the timer 3 counts the number of erase pulses applied for each block in the chip batch erase operation. May be. Here, the erase pulse is a signal for instructing the start of the erase operation, and is applied at a predetermined time interval when the erase operation in the block is not completed. Furthermore, both the allowable execution time and the number of erase pulses applied may be set in the timer 3.
[0018]
A high voltage generating circuit 4 generates a high voltage according to a signal from the control circuit / sequencer 2 and supplies the generated voltage to the block / row decoder 5.
The block / row decoder 5 decodes a row address signal from the address buffer 1 and activates a predetermined word line (not shown). The block / row decoder 5 is controlled in operation (ON / OFF, etc.) based on a signal from the control circuit / sequencer 2. The column decoder 6 decodes the column address signal from the address buffer and outputs the decoded result to the column gate 7.
[0019]
The column gate 7 controls signal transmission between the data buffer / multiplexer (MUX) 8 and the memory cell array 9 based on a signal from the column decoder 6. The data buffer / MUX 8 transmits a signal supplied from the outside by signals I / O 0 to I / O 15 to the column gate 7. Further, the data buffer / MUX 8 receives the data read from the memory cell array 9 or the information related to the defective block from the register information processing circuit 13 according to the signal from the control circuit / sequencer 2 as signals I / O0 to I / O15. To output to the outside.
[0020]
The memory cell array 9 includes N (N is a natural number) blocks 10-i (i is a subscript, i = 0, 1, 2,..., (N−1)) and a sense amplifier 11. Each block 10-i is composed of a plurality of nonvolatile memory cells that can electrically write and erase (rewrite) data. In this embodiment, data erasure at the time of chip collective erasure is performed for each block 10- It is executed with i as a unit. The sense amplifier 11 amplifies read data output from the memory cell array 9 to the column gate 7.
[0021]
Reference numeral 12 denotes a defective block storage register, which stores information indicating whether or not it is a defective block (whether or not there is a defective memory cell in the block) for each block 10-i of the memory cell array 9. That is, the defective block storage register 12 stores, for each block 10-i, information indicating whether or not the data erasing operation has been normally completed within the execution allowable time in the chip batch erasing operation.
[0022]
The register information processing circuit 13 outputs information related to the defective block to the data buffer / MUX 8 based on the information stored in the defective block storage register 12.
Here, the operation of outputting information relating to a defective block by the defective block storage register 12 and the register information processing circuit 13 is controlled based on a signal from the control circuit / sequencer 2.
[0023]
FIG. 2 is a diagram showing a detailed configuration example of the defective block storage register 12 and the register information processing circuit 13 shown in FIG. In FIG. 2, blocks having the same functions as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.
[0024]
As shown in FIG. 2, the bad block storage register 12 has N registers Ri (i = 0, 1,... (N−1)) each having a storage area of at least 1 bit, and a block <0. > Register R0, block <1> register R1,..., Block <N-1> register R (N-1) correspond to each block 10-i of the memory cell array 9, respectively. Each register Ri stores a register value “1” when there is a defective memory cell in the block 10-i, and a register value “0” otherwise.
[0025]
The register information processing circuit 13 includes N switches SWi (i = 0, 1,... (N−1)), a negative OR operation (NOR) circuit 21 and an inverter circuit 22. The switches SWi correspond to the registers Ri, respectively, and the output from the register Ri is input, and the input signal is output to the NOR circuit 21 or the inverter circuit 22. The switch SWi is controlled by a control signal from the control circuit / sequencer 2.
[0026]
The NOR circuit 21 receives the output of the switch SWi and outputs the calculation result to the data buffer / MUX8. The inverter circuit 22 selectively receives the output of the switch SWi, inverts the input signal, and outputs the inverted signal to the data buffer / MUX8. Signals output from the NOR circuit 21 and the inverter circuit 22 are output to the outside from the data buffer / MUX 8 via the input / output terminals I / O0 to I / O15.
[0027]
Next, the operation will be described.
First, the chip batch erase operation in the nonvolatile semiconductor memory device will be described.
FIG. 3 is a flowchart showing the chip batch erase operation. FIG. 3 shows an example in which it is determined whether or not there is a defective memory cell in the block 10-i based on the number of times the erase pulse is applied, instead of the allowable time for the data erase operation in the chip batch erase. .
[0028]
First, when execution of the chip batch erase operation is instructed by an address signal ADD or the like input from the outside, the counter value indicating the block number is set to zero in step S1. Next, in step S2, pre-writing called a preprogram and verification for confirming the operation are performed on the block 10-i indicated by the counter value. This pre-program is performed to prevent so-called over-erase.
[0029]
In step S3, the control circuit / sequencer 2 confirms whether or not the data of all the memory cells included in the block 10-I have been erased by the erase verify.
As a result of the confirmation, if there is a memory cell from which data has not been erased, the counter value indicating the number of times of application of the erase pulse is the maximum in step S4 (the allowable number of data erase operations set in advance in the timer 3, For example, 1000 times).
[0030]
If the counter value indicating the erase pulse application count is not the maximum as a result of the determination, the counter value indicating the erase pulse application count is incremented by 1 in step S5, and the erase target block 10- The erase pulse is applied again to i. After the erasing pulse is applied and a predetermined time (for example, 1 ms) elapses, the operations after step S3 are executed.
[0031]
On the other hand, if the result of determination in step S4 is that the counter value indicating the number of erase pulses applied is maximum, the block number of the block 10-i to be erased is recorded as a defective block number in step S7. Proceed to S8.
Similarly, if all the memory cells have been erased as a result of the confirmation by the erase verify in step S3, the process similarly proceeds to step S8.
[0032]
In step S8, it is confirmed whether or not the counter value indicating the block number is maximum. If the counter value is not maximum, the counter value indicating the block number is incremented by 1 in step S9, and the above-described step S2 Return to.
[0033]
On the other hand, if the counter value indicating the block number is the maximum as a result of the confirmation in step S8, the defective block number recorded in step S7 is read in step S10, and the defective block is identified in step S11. Determine if it exists. As a result of the determination, if there is no defective block, the process ends as a chip batch erase pass (success), and if there is a defective block, the process ends as a chip batch erase fail (failure).
[0034]
Next, an operation of outputting information relating to a defective block after the end of the chip batch erase operation shown in FIG. 3 will be described.
When the control signal indicating a predetermined value is output from the control circuit / sequencer 2 after the chip batch erase operation is completed, each register Ri of the defective block storage register 12 outputs the stored information. At this time, all the switches SWi of the register information processing circuit 13 are controlled by the control signal so as to supply the output of the register Ri to the NOR circuit 21.
[0035]
Therefore, when the outputs of all the registers Ri are simultaneously input to the NOR circuit 21 and the register value of at least one register Ri is “1”, the output of the NOR circuit 21 becomes “L” (low level). The output of the NOR circuit 21 is output to the outside by the data buffer / MUX 8 via, for example, the input / output terminal I / O 5.
[0036]
As a result, when the signal output via the input / output terminal I / O5 is “H” (high level), it is indicated to the outside that each block of the memory cell array 9 is normal, and “L”. In this case, it is indicated to the outside that at least one defective block exists in the memory cell array 9.
[0037]
Furthermore, information that can identify a defective block existing in the memory cell array 9 is output to the outside by shifting the operation mode to the defective block specifying mode. Here, in the defective block specifying mode, a command is input by an address signal ADD, a control signal CTL, or the like, or a predetermined voltage (for example, a high level voltage VHH) is applied to a predetermined external terminal included in the nonvolatile semiconductor memory device. Transition occurs when applied. When the nonvolatile semiconductor memory device is incorporated in the system, the operation mode can be changed to the defective block specifying mode only by inputting a command.
[0038]
The processing operation in the defective block specifying mode will be described below.
FIG. 4 is a diagram showing a flow of processing in the defective block specifying mode.
When a control signal indicating a predetermined value is output from the control circuit / sequencer 2 and a block address [0] is input by an external address signal ADD, the input block address [0] generates a signal BLADD. And supplied to the defective block storage register 12 (step S21).
[0039]
The block <0> register R0 corresponding to the supplied block address [0] outputs the stored information. At this time, the switch SW0 of the register information processing circuit 13 is controlled by the control signal so as to supply the output of the register R0 to the inverter circuit 22. The other switches SW1 to SW (N-1) are open.
[0040]
As a result, the output of the register R0 is inverted by the inverter circuit 22, and is output to the outside by the data buffer / MUX8, for example, via the input / output terminal I / O5. Therefore, when the signal output via the input / output terminal I / O5 is “H”, it is indicated to the outside that the block 10-0 of the memory cell array 9 is normal, and when it is “L”. The block 10-0 is externally shown to be a bad block (step S22).
[0041]
Next, the block address [1] input by the address signal ADD is supplied to the defective block storage register 12 (step S23), and the information stored in the block <1> register R1 is output. At this time, in the register information processing circuit 13, the switch SW1 supplies the output of the register R1 to the inverter circuit 22, and the other switches SW0, SW2 to SW (N-1) are controlled by the control signal so as to open. As a result, similarly to the case of the block <0>, a signal indicating whether or not the block 10-1 is a defective block is output to the outside from the data buffer / MUX8 via the input / output terminal I / O5. (Step S24).
[0042]
Similarly, the block address is sequentially input by the address signal ADD, and the block 10-i indicated by the block address is a defective block according to the information stored in the register Ri corresponding to the input block address. Whether or not the signal is output to the outside via the input / output terminal I / O5 (steps S25 and S26).
[0043]
FIG. 5 is a timing chart showing an output operation of defective block information in the above-described defective block specifying mode.
At time T10, when block address [0] is input from the outside by address signal ADD, period in which output enable signal / OE (symbol / indicates negative logic) is activated to “L”. In the middle, the bad block information SG10 is output via the input / output terminal I / O5. When the defective block information SG10 is “L”, there is a defective memory cell in the block 10-0 (defective block), and when it is “H”, there is no defective memory cell in the block 10-0. .
[0044]
Similarly, at time T11,..., T13, block address [1],..., Block address [N−1] are sequentially input from the outside by the address signal ADD, and the output enable signal / OE is activated to “L”. During this period, defective block information SG11,..., SG1 (N-1) of the block designated by the block address is output via the input / output terminal I / O5.
[0045]
As described above in detail, according to the first embodiment, the execution allowable time of the erase operation per block (or the allowable application number of erase pulses) is set in the timer 3 in advance. When the data stored in the memory cells of the memory cell array 9 is collectively erased by the chip batch erase operation, there is a memory cell in the block 10-i in which data has not been erased even after the execution allowable time has elapsed, that is, the execution allowable If the data erasure of all the memory cells in the block 10-i is not completed within the time, the erasing operation in the block 10-i is forcibly terminated and the erasing operation in the next block is started ( If there is no next block, the process ends.) In addition, the allowable execution time is a time during which data erasure is permitted. Generally, the erase operation in a normal block in which no defective memory cell exists is completed in a time much shorter than the allowable execution time.
[0046]
As a result, even if a defective memory cell exists in the memory cell array 9, the erasing operation in the block in which the defective memory cell exists can be completed in an execution allowable time of one block unit. Chip batch erase operation can be performed efficiently. Therefore, an increase in time required for the chip batch erase operation can be suppressed. For example, in a function test of a nonvolatile semiconductor memory device, an increase in time required for the function test due to the presence of a defective memory cell is suppressed. Test efficiency can be improved.
[0047]
Further, after the chip batch erase operation is completed, information indicating whether or not each block 10-i is a defective block is stored in the defective block storage register 12 by the register information processing circuit 13 as appropriate, and the data buffer / Output to the outside via MUX8. At this time, a signal (information) indicating whether or not there is a defective block in the nonvolatile semiconductor memory device, and if there is a defective block, a signal (information) that can identify the defective block may be externally indicated. it can.
[0048]
Therefore, for example, by monitoring a signal indicating whether or not a defective block exists in a function test in a nonvolatile semiconductor memory device, it is possible to determine whether the function test in the nonvolatile semiconductor memory device is acceptable. Further, for example, in a system equipped with a nonvolatile semiconductor memory device, even if a defective block exists, only a normal block is avoided by avoiding the defective block on the basis of a signal (information) that can identify the output defective block. It can be controlled to use and write and erase data, eliminating the need for replacement as in the prior art.
[0049]
In the processing in the defective block specifying mode shown in FIG. 4 above, the block address input by the external address signal ADD is incremented by one. However, the present invention is not limited to this and is arbitrary. And an arbitrary block address value can be input.
[0050]
(Second Embodiment)
Next, a second embodiment of the present invention will be described.
The nonvolatile semiconductor memory device according to the second embodiment outputs the block address value of the defective block to the outside when outputting information that can identify the defective block in the defective block specifying mode.
[0051]
The nonvolatile semiconductor memory device according to the second embodiment is different from the nonvolatile semiconductor memory device according to the first embodiment described above only in the register information processing circuit, and the first embodiment shown in FIG. Since the overall configuration is the same as that of the nonvolatile semiconductor memory device according to, description of the overall configuration is omitted.
[0052]
FIG. 6 is a diagram illustrating a detailed configuration example of the defective block storage register 12 and the register information processing circuit 13 ′ of the nonvolatile semiconductor memory device according to the second embodiment. In FIG. 6, blocks having the same functions as those shown in FIGS. 1 and 2 are denoted by the same reference numerals, and redundant description is omitted.
[0053]
As shown in FIG. 6, the register information processing device 13 ′ in the second embodiment includes N switches SWi (i = 0, 1,... (N−1)), a negative OR operation (NOR) circuit. 21 and an encoder 61. The switch SWi and the NOR circuit 21 are the same as those in the first embodiment described above.
The encoder 61 is supplied with the output of the switch SWi. When the supplied signal is “H”, the encoder 61 outputs a block address (binary representation) corresponding to the signal to the data buffer / MUX8.
[0054]
The operation of the nonvolatile semiconductor memory device according to the second embodiment is different from the first embodiment described above only in the processing operation in the defective block specifying mode, and the other operations are the same. Only the processing operation in the mode will be described.
[0055]
FIG. 7 is a diagram showing a flow of processing operations in the defective block specifying mode in the second embodiment.
When the operation mode transitions to the defective block specifying mode, the control circuit / sequencer 2 searches the defective block storage register 12 for a register Ri having a register value “1” (step S31). The search is performed by sequentially increasing the block address one by one in accordance with the toggle operation of the output enable signal / OE and confirming the value of the register Ri corresponding to the block address. The control circuit / sequencer 2 controls the switch SWi in the register information processing circuit 13 ′ according to the block address so that the output of the register Ri is supplied to the encoder 61.
[0056]
When a register Ri (register corresponding to a defective block) having a register value “1” is found by the search (step S32), the encoder 61 to which the output of the register Ri is supplied via the switch SWi The address (binary representation) of the block corresponding to Ri is output to the data buffer / MUX8.
[0057]
Further, the data buffer / MUX 8 outputs the block address from the encoder 61 to the outside via, for example, a plurality of input / output terminals I / O0 to I / O (k−1) (step S33). At this time, the data buffer / MUX 8 indicates whether or not the signal output via the input / output terminals I / O0 to I / O (k−1) is a defective block address based on the signal from the encoder 61. Is output to the outside via the input / output terminal I / O 15.
[0058]
Thereafter, the control circuit / sequencer 2 searches the register Ri whose register value is “1” while sequentially increasing the block address. Then, the control circuit / sequencer 2 searches up to the register R (N−1) at the block address corresponding to the block <N−1> which is the final block (step S34), and ends the process.
[0059]
FIG. 8 is a timing chart showing an output operation of defective block information in the defective block specifying mode in the second embodiment.
When the processing operation in the defective block specifying mode is started at time T20, the input / output terminals I / O0 to I / O (k−1) during the period in which the output enable signal / OE is activated to “L”. ) And defective block data SG0 are output via the input / output terminal I / O15. Here, when the bad block information SG20 is "L", the bad block data D0 is valid data and indicates a bad block address. On the other hand, when the bad block information SG20 is “H”, the bad block data D0 is invalid data.
[0060]
After the output enable signal / OE is inactivated to "H", when the output enable signal / OE changes from "H" to "L" at time T21, the block address managed internally is incremented by one. Is done. During the period when the output enable signal / OE is activated to "L", the defective block data D1 is output via the input / output terminals I / O0 to I / O (k-1) and the input / output terminal I / O15. , Bad block information SG21 is output.
[0061]
Similarly, after the output enable signal / OE is deactivated to “H”, when the output enable signal / OE changes from “H” to “L” at time T22, T23,. Incremented by one. During the period when the output enable signal / OE is activated to "L", the defective block data D2, D3 are passed through the input / output terminals I / O0 to I / O (k-1) and the input / output terminal I / O15. And bad block information SG22 and SG23 are output.
[0062]
As described above, according to the second embodiment, the same effect as that obtained by the first embodiment described above can be obtained. In addition, when outputting a signal (information) that can identify a defective block in the defective block identification mode, the block address is automatically incremented one by one by the toggle operation of the output enable signal / OE, corresponding to the block address. Output bad block information about the block to be processed.
[0063]
Thereby, as compared with the first embodiment described above, it is possible to output the bad block information for all the blocks 10-i to the outside with a small number of external control operations. Furthermore, by converting a signal that can identify a defective block into a block address in binary notation by the encoder 61 and outputting the block address, the defective block can be easily recognized outside.
[0064]
In the first and second embodiments described above, it is determined whether or not there is a defective block via the input / output terminal I / O5 and the input / output terminals I / O0 to I / O (k−1). The information shown and the information that can identify the defective block are output, but this is only an example, and the input / output terminal used to output the information to the outside is arbitrary.
[0065]
In the first and second embodiments described above, the NOR circuit 21, the inverter circuit 22, and the like are provided as logic circuits that perform logical operations on information from the defective block storage register 12 in the register information processing circuits 13 and 13 ′. However, the present invention is not limited to this, and may be positive logic or negative logic as long as the logic of a signal output to the outside is determined. For example, when the logic of the signals output from the register information processing circuits 13 and 13 ′ is reversed from the example shown in the first and second embodiments described above, a logical sum ( OR circuit may be used, and a buffer circuit or a cascaded even-numbered inverter circuit may be used instead of the inverter circuit 22.
[0066]
Further, in the first and second embodiments described above, the switch SWi included in the register information processing circuit 13 (13 ′) receives the input signal in accordance with the control signal from the control circuit / sequencer 2 and the NOR circuit 21. Alternatively, the signal is output to the inverter 22 (encoder 61). However, the input signal is always supplied to the NOR circuit 21, and only whether the signal is output to the inverter 22 (encoder 61) depends on the control signal. You may make it control. In this case, the signal output from the NOR circuit 21 and the signal output from the inverter 22 (encoder 61) may be output via different input / output terminals, and the switch SWi is configured by one two terminals. Therefore, the circuit configuration can be simplified.
[0067]
The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.
Various aspects of the present invention will be described below as supplementary notes.
[0068]
(Appendix 1) A nonvolatile semiconductor memory device capable of electrically writing and erasing data,
A memory cell array having a plurality of blocks each composed of a plurality of memory cells;
Erasing means capable of erasing the stored data stored in the memory cell in batches for each block;
Setting means for setting an execution allowable time of the erase operation per one block,
When the data stored in all the memory cells of the memory cell array is sequentially erased for each block by the erasing means, if the erasure of the memory data of the memory cells constituting the block is not completed within the execution allowable time, the block The nonvolatile semiconductor memory device is characterized in that the erasing operation is terminated.
(Additional remark 2) It is characterized by further comprising an output means for outputting a signal indicating whether or not the data stored in all the memory cells has been erased after the erase operation in all the blocks is completed by the erase means. The nonvolatile semiconductor memory device according to appendix 1.
(Supplementary note 3) The nonvolatile semiconductor memory device according to supplementary note 2, wherein the output means further outputs a signal indicating whether or not the erase operation is completed within the permissible execution time for each of the blocks.
(Additional remark 4) The said output means further outputs the signal which shows the information which can identify the block which did not complete erase operation within the said execution permissible time, The non-volatile semiconductor memory device of Additional remark 2 characterized by the above-mentioned .
(Supplementary note 5) The nonvolatile semiconductor memory device according to supplementary note 4, wherein the information identifiable by the block is a block address assigned to the plurality of blocks so as to be different from each other.
(Supplementary note 6) The nonvolatile semiconductor memory device according to supplementary note 1, further comprising storage means for storing pass / fail information indicating whether or not the storage data of the memory cell has been erased in all the blocks.
(Additional remark 7) The said memory | storage means memorize | stores the said quality information for every said block, The non-volatile semiconductor memory device of Additional remark 6 characterized by the above-mentioned.
(Supplementary note 8) The nonvolatile semiconductor memory device according to supplementary note 6, further comprising output means for outputting information in response to an external request based on the stored quality information.
(Supplementary note 9) The nonvolatile semiconductor memory device according to supplementary note 8, wherein the output means performs a logical sum operation on the pass / fail information in response to a request from the outside, and outputs the obtained calculation result. .
(Supplementary note 10) The nonvolatile semiconductor memory device according to supplementary note 8, wherein the output means selectively outputs the pass / fail information related to any one block in response to a request from the outside.
(Additional remark 11) The said output means is provided with the conversion means which converts the said quality information into the information which the said block can identify when selectively outputting the said quality information, The non-volatile of Claim 10 characterized by the above-mentioned Semiconductor memory device.
(Supplementary note 12) The nonvolatile semiconductor memory device according to supplementary note 11, wherein the information identifiable by the block is a block address assigned to the plurality of blocks so as to be different from each other.
(Supplementary note 13) The nonvolatile semiconductor memory device according to supplementary note 11, wherein the output means selectively outputs the pass / fail information relating to any one block and sequentially outputs all the blocks.
(Supplementary note 14) The nonvolatile memory according to any one of supplementary notes 1 to 13, wherein the permissible execution time is determined using the number of times of application of an erase pulse that instructs the block to erase stored data. Semiconductor memory device.
(Supplementary note 15) A data erasing method of a nonvolatile semiconductor memory device capable of electrically writing and erasing data,
For each block composed of a plurality of memory cells, when the stored data stored in the memory cell is sequentially erased in batch, the allowable time for executing the erase operation per one block is set, and the block is configured. A data erasing method, comprising: erasing data stored in a memory cell to be erased when the erasing operation in the block is terminated when erasing data stored in the memory cell is not completed within the set allowable execution time.
(Supplementary note 16) The data erasing method according to supplementary note 15, wherein after the erase operation in all the blocks is completed, a signal indicating whether or not the data stored in all the memory cells has been erased is output. .
(Supplementary note 17) The supplementary note 16 further outputs a signal indicating whether or not the erase operation has been completed within the permissible execution time for each block when the data stored in the memory cell has not been erased. The data erasing method described.
(Supplementary note 18) When the data stored in the memory cell cannot be erased, a signal indicating information that can identify a block in which the erase operation has not been completed within the permissible execution time is further output. The data erasing method described in 1.
[0069]
【The invention's effect】
As described above, according to the present invention, the storage data stored in the memory cell in the non-volatile semiconductor memory device having the memory cell array having the plurality of blocks each composed of the plurality of memory cells is sequentially arranged for each block. When batch erasing is performed, the execution allowable time of the erase operation per block is set, and if the erase of the data stored in the memory cell constituting the block is not completed within the execution allowable time, the erase operation in the block is terminated. To do. As a result, even if a defective memory cell exists in the nonvolatile semiconductor memory device, the erasing operation in the block in which the defective memory cell exists is forcibly terminated with an execution allowable time per block, and the next block The erase operation can be started, the increase in the time required for the chip batch erase operation can be suppressed, and the chip batch erase operation can be performed efficiently.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a nonvolatile semiconductor memory device according to a first embodiment.
FIG. 2 is a diagram illustrating a configuration example of a register information processing circuit in the first embodiment.
FIG. 3 is a flowchart showing a chip batch erase operation in the nonvolatile semiconductor memory device according to the first embodiment.
FIG. 4 is a diagram showing a flow of processing in a defective block specifying mode in the first embodiment.
FIG. 5 is a timing chart showing an output operation of defective block information in the first embodiment.
FIG. 6 is a diagram illustrating a configuration example of a register information processing circuit of the nonvolatile semiconductor memory device according to the second embodiment.
FIG. 7 is a diagram showing a flow of processing in a defective block specifying mode in the second embodiment.
FIG. 8 is a timing chart showing an output operation of defective block information in the second embodiment.
[Explanation of symbols]
1 Address buffer
2 Control circuit / sequencer
3 Timer
4 High voltage generator
5 block / row decoder
6 Column decoder
7 Column gate
8 Data Buffer / Multiplexer
9 Memory cell array
10 blocks
11 sense amplifier
12 Bad block storage register
13 Register information processing circuit

Claims (8)

A nonvolatile semiconductor memory device capable of electrically writing and erasing data,
A memory cell array having a plurality of blocks each composed of a plurality of memory cells;
Erasing means capable of erasing the stored data stored in the memory cell in batches for each block;
Setting means for setting an allowable execution time of the erase operation per one block;
A storage unit that is provided for each block and stores a signal indicating quality information indicating whether or not the erasing operation for the block is completed within the execution allowable time;
After the erase operation in all the blocks is completed by the erase unit, a signal indicating whether or not the data stored in all the memory cells has been erased based on the pass / fail information stored in the storage unit. Output means for outputting,
When sequentially erased for each of the block by the erase it means storing data of all the memory cells of the memory cell array, the quality information on the erase operation to the block upon which is stored in the storage means, moving the object to the next block And the erasing operation is continued . The nonvolatile semiconductor memory device according to claim 1, wherein the output unit further outputs a signal indicating the pass / fail information for each block. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the output means further outputs a signal indicating information that can identify a block in which an erase operation has not been completed within the execution allowable time. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the output means outputs information according to a request from the outside based on the stored quality information. 5. The nonvolatile semiconductor memory device according to claim 4, wherein the output means performs a logical OR operation on the pass / fail information in response to a request from the outside, and outputs the obtained operation result. 5. The nonvolatile semiconductor memory device according to claim 4, wherein the output means selectively outputs the pass / fail information relating to any one block in response to a request from the outside. 7. The non-volatile semiconductor memory device according to claim 6, wherein the output means comprises conversion means for converting the pass / fail information into information identifiable by the block when the pass / fail information is selectively output. . 8. The nonvolatile semiconductor memory device according to claim 3, wherein the information that can be identified by the block is a block address assigned to the plurality of blocks so as to be different from each other.

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