JP3857642B2 - Nonvolatile semiconductor memory device and erase sequence thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device, and more particularly to an erase function and an erase sequence of a flash memory.
[0002]
[Prior art]
As a conventional nonvolatile semiconductor memory device, a flash memory that simultaneously erases data stored in a memory cell array has been proposed. FIG. 13 shows an erase sequence of a conventional NOR flash memory. When blocks to be erased are sequentially selected and erased, the pre-erase write and erase subsequences are successively executed. Here, the pre-erase write is to put all memory cells in the block in a write state (“0” state) in advance in order to perform erasure uniformly.
[0003]
That is, as shown in FIG. 13, for example, when erasing the first, second, and third blocks, after erasure confirmation, the first block is written before erasure and then erased. Then, after confirming execution of erasure, the pre-erase write is performed on the second block, and then erasure is performed. Thereafter, after confirmation of execution of erasure, the third block is written before erasure and then erasure is performed. In the case where the number of blocks is n, the sequence of writing before erasure and erasing are executed after sequentially confirming the execution of erasure.
[0004]
In this case, it is checked whether it is selected as an erasure target by the command or protected (erasure prohibited), and if it is not a block to be erased, writing before erasure is not performed, and if the selected block is an erasure target The pre-erase writing is executed.
[0005]
In addition, the pre-erase write is performed in increments of the row address and the column address in the block and sequentially by one address or several addresses.
[0006]
When the pre-erase write to all the memory cells in the block is completed, the final address is confirmed, and then erase is executed.
[0007]
FIG. 14 shows an example of a method for applying writing (programming) and erasing bias to the transistors constituting the memory cell. Here, as a method for applying the erase bias, a high electric field is applied between the silicon substrate and the word line. However, a method of erasing by applying a high electric field between the word line and the source may be used.
[0008]
The memory cell shown in FIG. 14 includes a source 102, a drain 103, a floating gate 104, and a control gate 105 formed on a silicon substrate 101.
[0009]
Writing is performed by applying a program bias as shown in FIG. 14A to the memory cell and injecting and trapping hot electrons from the drain 103 side of the silicon substrate 101 to the floating gate 104. At this time, since a large current flows through the memory cell, it is not possible to simultaneously write to many cells.
[0010]
Erasing is performed while verifying each bit. Note that programming before erasure may be performed while verifying for each bit.
[0011]
When verifying, even if one bit has a verify-fail (not completely erased) memory cell, the erase bias shown in FIG. 14B is applied again to all the memory cells in the block, and the floating gate 104 The electrons trapped in are discharged to the silicon substrate 101, and the stored data in the memory cells are simultaneously erased. Simultaneous erase and verify are repeated until all memory cells in the block pass the verify step.
[0012]
Further, the verify is performed by counting up the row / column addresses in the block until the final address is confirmed using the address count-up step. Simultaneous erasure and verification of the block are finished, the block address is counted up, and a series of erase sequences is continued for the next erase block.
[0013]
In this way, the pre-erase write, simultaneous erase and verify are repeated for each block to be erased, the final block is confirmed, and the erase sequence is completed.
[0014]
FIG. 15 shows an equivalent circuit of a NOR type flash memory array. The NOR type flash memory shown in FIG. _{i, j} (Shows the case of i = 1, 2, j = 1, 2) and the selection gate S _i And word line WL _i (Showing the case of i = 1, 2), a bit line BL, and a source line S.
[0015]
Since the NOR type flash memory has the array configuration shown in FIG. 15, if the threshold is lowered too much by erasing, the word line WL _i Is low level (“L”) and is not selected, current flows through the bit line BL. _i Even if a word line other than is selected, "1" may always be read. Therefore, weak writing may be performed after erasing.
[0016]
For example, as shown in FIG. 14C as convergence bias, all the word lines are unselected (control gate 105 = 0V), and the high voltage (drain 103 = 5V) is applied only to the bit lines. Of the memory cells on the bit line, in the overerased state, the current concentrates on the memory cell having a low threshold value, and weak writing is performed, and the threshold value of the overerased cell can be slightly increased in a self-convergent manner. .
[0017]
In the program bias shown in FIG. 14A, writing is completed in 5 to 10 μsec, but in the erase bias shown in FIG. 14B, erasing requires 10 to 100 msec. As a result, for example, in the case of a 64 kbyte block, a time of 500 to 1000 msec is required until the erase sequence is completed.
[0018]
[Problems to be solved by the invention]
As described above, the conventional nonvolatile semiconductor memory device has a problem that it takes a long time to complete the erase sequence because it takes a write-erase-erase sequence for each block.
[0019]
The present invention has been made to solve such a problem, and provides a nonvolatile semiconductor memory device having a function capable of completing an erase sequence in a shorter time than the conventional one and an erase sequence thereof. is there.
[0020]
[Means for Solving the Problems]
The nonvolatile semiconductor memory device according to the present invention is to selectively write in units of bits and to collectively erase in units of blocks including a predetermined number of memory cells. The erase sequence consists of three sub-sequences: write before erase, erase and erase distribution reduction (convergence).
[0021]
According to the first aspect of the present invention, a non-volatile semiconductor memory device includes a plurality of blocks each including a plurality of memory cells to be erased at once and a decoder for selecting the memory cells, a sense amplifier, and an erase operation. An address control circuit that counts the addresses of the memory cells and controls a sequence of erasing after performing pre-erase writing on all selected memory cells,
Each of the blocks has a block decoder that latches the selection signal of the block at the time of programming before erasure and simultaneously selects all the blocks at which the selection signal is latched at the time of erasure,
All blocks in which the selection signal is latched are controlled to be erased collectively by the address control circuit.
[0022]
According to the second feature of the present invention, a non-volatile semiconductor memory device includes a plurality of blocks each including a plurality of memory cells to be erased at once and a decoder for selecting the memory cells, a sense amplifier, and an erase operation. An address control circuit that counts the addresses of the memory cells and controls a sequence of erasing after performing pre-erase writing to all the memory cells in the selected predetermined number of blocks,
Each of the blocks has a block decoder that latches the selection signal of the block at the time of programming before erasure and simultaneously selects all the blocks at which the selection signal is latched at the time of erasure,
A predetermined number of blocks in which the selection signal is latched are controlled to be collectively erased by the address control circuit.
[0023]
According to a third aspect of the present invention, a method for executing an erase sequence of a nonvolatile semiconductor memory device is the first to perform pre-erase write when sequentially erasing a plurality of blocks each including a plurality of memory cells. After confirming execution of erasure of the first block, write before erasure of the first block, after confirming execution of erasure of the next block, perform write before erasure of the next block, and so on for each block. After confirming execution of erasure of a block, writing before erasure of the block is performed, and thereafter, erasure is performed for each block at once.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0025]
FIG. 1 shows an erase sequence of a basic nonvolatile semiconductor memory device of the present invention. For example, when erasing the first, second, and third blocks, after the erase execution confirmation, the first block is written before erasure, and after the erase execution confirmation, the second block is erased. Perform pre-writing. Thereafter, after confirmation of execution of erasure, the third block is written before erasure, and then erasure is performed for each block. When the number of blocks is n, after the erase execution confirmation, the pre-erase write and erase sequences are executed.
[0026]
In writing before erasure of each block, if the block is to be erased, a flag is added and erased in the erase sequence. When the pre-erase write is not necessary for the block, the block is skipped and the pre-erase write is executed for the next block.
[0027]
FIG. 2 shows a block configuration of the nonvolatile semiconductor memory device according to the first embodiment. The nonvolatile semiconductor memory device includes a memory cell array 1, a row decoder 2, a column decoder 3, a block decoder 4, a sense amplifier 5, an address control circuit 6, a command interface 7, a state machine 8, a timer. 9, a protect register 10, and an internal power supply control circuit 11.
[0028]
When a predetermined command is received from outside the chip, the command interface 7 transfers a trigger signal for starting a sequence to the state machine 8. The state machine 8 performs automatic erasure by changing the output control signals of the address control circuit 6 and the internal power supply control circuit 11.
[0029]
As shown in FIG. 2, the memory cell array 1 is composed of units (hereinafter referred to as blocks) to which an erasing bias is simultaneously applied. Each block is selected by a row decoder 2, a column decoder 3, and a source in order to select individual memory cells. The cell data is sent to the sense amplifier 5 and output to the I / O. Each block includes a block decoder 4 and outputs a block selection signal SELBLKi.
[0030]
Only the row decoder 2 and the column decoder 3 of the selected block become active, and the memory cells respectively designated by the row address and the column address are selected.
[0031]
FIG. 3 shows a circuit example of the block decoder, and FIG. 4 shows a logical configuration of row selection and column selection that receives the block selection signal SELBLKi.
[0032]
The block decoder of FIG. 3 that outputs the block selection signal SELBLKi is a block that switches between the NAND gate G1 that receives the block address BLK Address and the clocked inverters I2 and I3 via the inverter I1 that receives the block selection signal MULTIIBLK. The latch circuit includes an output portion of the selection signal SELBLKi, an inverter I4 that receives the output of the NAND gate G1, an inverter I5 that receives the set signal SET, and a NAND gate G2 and a clocked inverter I6.
[0033]
The output of the inverter I4 is controlled by the set signal SET and is connected to one terminal of the NAND gate G2. The output of inverter I5 controls inverter I6. The reset bar signal RSTB is connected to the other input of the NAND gate G2.
[0034]
When the block selection signal MULTIBLK is set to “H”, the block decoder shown in FIG. 3 performs the block selection signal for all blocks in which “H” is latched in the erase selection latch circuit composed of G2 and I6. It has a function to set SELBLKi to “H”.
[0035]
The block selection configuration having a row and column selection function shown in FIG. 4 includes a column decoder 3 including AND gates G3 and G4, a row decoder 2 including AND gates G5 and G6, and a source / well decoder 12 including an AND gate G7. Consists of
[0036]
The output of the column decoder 3 is connected to the selection gate line of the memory cell array 1 and performs column selection according to the column address. The output of the row decoder 2 is connected to the word line of the memory cell array 1 and the word line according to the row address. Make a selection. The AND gate G7 constituting the source / well decoder 12 receives the block selection signal SELBLKi and the erase signal ERASE, and if both are “H”, an erase voltage is applied to the common source line S, and the common Data in the cell array can be erased in block units selected by the source line S.
[0037]
The power supply terminals of the AND gates constituting the column decoder 3, the row decoder 2 and the source / well decoder 12 have V _PP1 , V _PP2 , V _PP3 A plurality of internal power supply voltages are supplied from the internal power supply control circuit 11 of FIG.
[0038]
Next, the erase operation of the nonvolatile semiconductor memory device according to the first embodiment will be described using the erase sequence of FIG.
[0039]
In this embodiment, writing before erasure is performed for each block, and thereafter, erasure is performed for each block.
[0040]
That is, in response to a command for instructing erasure, initialization is performed in step S1. In step S2, the row / column address is initialized, and the potential of the internal power control circuit 11 in FIG. 2 is controlled to the write potential.
[0041]
In step S3 for confirming execution of erasure, it is confirmed whether or not the block is the relevant block. 2 is compared with the selected block address, and GO = H is sent from the protect register 10 to the state machine 8 when erasing is executed. If GO = H, write before erase is executed.
[0042]
Thereafter, the pre-erase write is sequentially performed on all the memory cells in the block through the path of step S4 for confirming the final address, step S5 for setting the program and erase selection latch, and step S6 for counting up the address. At the same time, “H” is latched in the erase selection latch of the block decoder 4 of FIG. 2 provided for each block. That is, a flag is added to the block.
[0043]
When all the pre-erase writing in the block is completed, in step S4, AEND = H, and the process proceeds to the next block sequentially through step S7 for counting up the block address and step S8 for checking the final block. S2 to S6 are executed.
[0044]
Here, AEND is a final row / column address confirmation signal, and BEND is a final block confirmation signal.
[0045]
In this way, when the pre-erase write is completed for all the blocks, “H” is latched only in the block to be erased in the erase selection latch.
[0046]
When writing before erasure is not necessary for the block, the process proceeds from step S3 for confirming execution of the erase to step S7 for counting up the block address.
[0047]
When the final block is confirmed in step S8, step S9 for initializing the address and step S10 for confirming the row / column address are followed by verifying until AEND becomes H in step S11 for confirming the final address of the block. Step S12, step S13 for erasing and step S14 for counting up the address are repeated, and when AEND = H, the process proceeds to step S15 for confirming the final block by the confirmation signal, and erasure is terminated at step S16 by the confirmation signal. If it is not the final block, the process proceeds to step S17 to count up the block address, and the above-described erase process is executed.
[0048]
In step S13 for executing erasing, an erasing bias shown in FIG. 14B is applied to the memory cell. For this reason, all the rows / columns are set in a non-selected state, and the signal MULTIBLK for block selection is set to “H”. In this way, the block selection signal SELBLKi becomes “H” for all the blocks in which “H” is latched in the erase selection latch composed of G2 and I6 shown in FIG.
[0049]
At this time, the source / well decoder 12 shown in FIG. 4 transfers the internal boosted potential of the internal power supply control circuit 11 shown in FIG. 2 only to the block in which SELBLKi becomes “H”. Therefore, the erase bias is applied only to the block selected for erase. Thus, a plurality of blocks selected for erasing can be erased collectively.
[0050]
Here, erasing is performed while verifying every bit in step S12 of FIG. In verify read, if even one bit of memory cells that are not in the erased state exist, batch erase of a plurality of blocks selected for erase is executed again. In step S15, the last block is confirmed, and the erase sequence in FIG. 5 is terminated.
[0051]
As is apparent from the above-described steps, in this embodiment, when writing before erasure of each block, as in step S3, confirmation of erasure execution of the block is always performed, and writing before erasure is not required for the block. In this case, skip that block and move to the next block.
[0052]
As described above, according to the first embodiment, unlike the conventional erasing step shown in FIG. 13, a plurality of blocks selected for erasing are erased all at once, so that the erasing sequence can be completed in a short time. Can do.
[0053]
Next, a second embodiment will be described.
[0054]
In the memory, some memory cells may not function due to various factors such as dust generated during the manufacturing process. Therefore, it is common practice to provide redundancy for obtaining a good product by providing redundant cells in the cell array and replacing defective cells with redundant cells. Redundancy can be replaced in units such as word line replacement or bit line replacement, and the flash memory may be provided with block redundancy replaced in units of blocks.
[0055]
The configuration of block redundancy is shown in FIG. The redundancy fuse 13 storing the block address to be replaced, that is, the information of the address holding element and the selected block address are compared by the address control circuit 6, and if they match, the address of the corresponding redundant block is replaced. To the block decoder 4.
[0056]
When a defective block is replaced with a redundant block using block redundancy, the replaced redundant block must be erased. Therefore, separately from the main body block, the block decoder 4 of the redundant block also needs to be provided with erase selection latches composed of G2 and I6 of FIG. When a defective block is selected at the time of programming before erasure, the block selection signal SELBLKi is replaced with a redundant block according to the information of the redundancy fuse 13 in FIG.
[0057]
At this time, “H” is latched in the erase selection latch of the corresponding redundant block. In the subsequent operation, similarly to the first embodiment, the signal MULTIBLK for block selection at the time of erasing becomes “H”, and the erasing bias is simultaneously applied only to the redundant block selected for the redundant block.
[0058]
According to the second embodiment, since a plurality of blocks selected to be erased including redundant blocks are erased at once, it is possible to complete an erase sequence including redundant blocks in a short time.
[0059]
Further, a third embodiment will be described.
[0060]
When erasing a plurality of blocks at the same time, it is necessary to simultaneously bias a large number of memory cells constituting the plurality of blocks. Therefore, if the erasing potential is charged and discharged at the same time, the internal potential may change greatly due to the peak current. .
[0061]
In order to avoid this, the blocks are divided into several groups as shown in FIG. 7A, and the peak current is reduced by shifting the erase pulse voltage. The peak current can be sufficiently suppressed if the time for shifting charge / discharge is 0.1 to 1 μsec with respect to the application time of 1 to 10 msec for the erase bias.
[0062]
If it is desired to shift only the reset operation at the end of erasure, it is sufficient to shift only at the end as shown in FIG. Since the deviation of the pulse is very small compared with the application time of the erase bias, the change of the threshold due to the difference of the erase time can be ignored.
[0063]
According to the third embodiment, since the change of the internal potential due to the peak current generated when erasing a plurality of blocks at once is suppressed, it is possible to realize uniform erasure.
[0064]
A fourth embodiment will be described.
[0065]
If the erase bias is applied to all the blocks in the chip at once, the threshold value after erasure may be largely shifted for each block due to variations in the erase characteristics of the memory cells. Therefore, in this embodiment, the blocks in the chip are divided into several groups, and the erase bias is collectively applied to a plurality of blocks selected in each group.
[0066]
This erase sequence is shown in FIG.
[0067]
That is, in response to a command for instructing erasure, initialization is performed in step S1. In step S2, the row / column address of the first block in the first group is initialized, and the potential of the internal power supply control circuit 11 in FIG. 2 is controlled to the write potential as in FIG.
[0068]
In step S3 for confirming execution of erase, it is confirmed whether or not to erase each group including a plurality of blocks. Similarly to FIG. 5, the data of the protect register (usually composed of fuse elements) 10 shown in FIG. 2 is compared with the selected block address, and GO = H is sent from the protect register 10 to the state machine 8 when erasing is executed. If GO = H, write before erase is executed.
[0069]
Thereafter, the row / column address is counted up in the path of step S4 for confirming the last block address of the group, step S5 for setting the program and erase selection latch, and step S6 for counting up the address. Write before erasure sequentially. At the same time, “H” is latched in the erase selection latch of the block decoder 4 of FIG. 2 provided for each block. That is, a flag is added to the group.
[0070]
In this way, when writing before erasure is completed for all the blocks in the selected group, “H” is latched only in the block to be erased in the erase selection latch.
[0071]
When writing before erasure is unnecessary for the group, the process proceeds from step S3 for confirming execution of the erase to step S7 for counting up the group address, and writing before erasure for each group is performed until the final group is confirmed in step S8. Executed.
[0072]
When all the pre-erase writing in the group is completed, AEND = H is set in step S4, and batch erasure of each group is started.
[0073]
After step S9 for initializing the row / column address and step S10 for confirming the final block address of the last group, step S11 for verifying, step S12 for erasing and step S13 for counting up the address are repeated, and when AEND = H Then, the process proceeds to step S14 in which the final group is confirmed by the confirmation signal, and the erasure is completed in step S15 by the confirmation signal BEND. If it is not the final group, the process proceeds to step S16 to count up the group address and returns to step S2, and as described above, the pre-erase write and erase processes are executed for the group.
[0074]
In step S12 for executing erasing, an erasing bias shown in FIG. 14B is applied to the memory cell. For this reason, all the rows / columns are set in a non-selected state, and the signal MULTIBLK for block selection is set to “H”. In this way, the block selection signal SELBLKi becomes “H” for all the blocks in which “H” is latched in the erase selection latch composed of G2 and I6 shown in FIG.
[0075]
At this time, the source / well decoder 12 shown in FIG. 4 transfers the internal boosted potential of the internal power supply control circuit 11 shown in FIG. 2 only to the block in which SELBLKi becomes “H”. Therefore, the erase bias is applied only to the block selected for erase. Thus, a plurality of blocks selected for erasing can be erased collectively.
[0076]
Here, erasing is performed while verifying every bit in step S11 of FIG. In verify read, if even one bit of memory cells that are not in the erased state exist, batch erase of a plurality of groups selected for erase is executed again. In step S14, the final group is confirmed, and the erase sequence in FIG. 8 is terminated.
[0077]
As is clear from the above-described steps, in this embodiment, when writing before erasure of each group, as in step S3, confirmation of execution of erasure of each group is always performed, and writing before erasure is not required for a certain group. In that case, skip the group and move on to the next group.
[0078]
As described above, according to the fourth embodiment, since a plurality of groups selected for erasure are erased all at once, the erase sequence can be completed in a short time.
[0079]
Next, the configuration of the address control circuit corresponding to the erase sequence of the fourth embodiment will be described. First, an address control circuit for a conventional erase sequence that repeatedly performs pre-erase writing, simultaneous erase, and verify read for each block will be described with reference to FIGS. 9A, 9B, and 10. FIG.
[0080]
FIG. 9A shows the configuration of an address control circuit that counts up block addresses. For example, counting up of eight blocks is performed by three stages of address buffers / counters 14, 15, and 16. An example of the circuit configuration of the address buffer / counter is shown in FIG.
[0081]
The address buffer / counter is a binary counter including a transistor Q1 that receives a reset signal, first and second latches including inverters I7 to I10, first and second transfer gates including transistors Q2 to Q5, and an inverter I11. And a multiplexer composed of NAND gates G8 to G10 and an inverter I12, a carry circuit composed of NAND gates G11 and G12 and inverters I13 and I14, and an input unit for a count-up clock signal ADV.
[0082]
The address buffer / counter receives the count-up clock signal ADV and generates signals INC and INCB for operating the binary counter. The signal ERSB which is “L” in the sequence of FIG. 5 and the input IN and binary from the address pad An output signal OUT that advances the internal address bit by bit is output from the multiplexer that receives the output of the counter. The carry circuit generates a signal CARRY whenever the internal address bit carries.
[0083]
In this manner, in the block address control circuit shown in FIG. 9A, the internal block address that is incremented bit by bit by the count-up clock signal ADV is used as the output signal OUT of the address buffers / counters 14, 15, and 16 as the data bus. Is output.
[0084]
Each time a carry is generated by counting up the block address, the signal CARRY of the address buffer / counter 14 of the least significant bit is sequentially sent to the signal CARRY of the address buffer / counter 16 of the most significant bit. The signal CARRY of the address buffer / counter 16 can be used as a determination signal BEND that the block address count-up has reached the final address.
[0085]
Similarly, in the row / column address control circuit shown in FIG. 9B, the internal row / column address that is incremented bit by bit by the count-up clock signal ADV is used as the output signal OUT of the address buffers / counters 17, 18, and 19. The signal CARRY of the address buffer / counter 19 of the most significant bit can be used as the determination signal AEND that the row / column address count-up has reached the final address.
[0086]
If the address control circuit shown in FIGS. 9A, 9B and 10 is used, it is possible to cope with a conventional erase sequence in which pre-erase write, simultaneous erase and verify read are repeated for each block.
[0087]
Next, referring to FIG. 11, the blocks in the chip are divided into several groups, and an erase sequence according to the fourth embodiment for collectively applying an erase bias to a plurality of blocks selected for erase in each group. The configuration of the address control circuit corresponding to the above will be described.
[0088]
The address control circuit shown in FIG. 11 includes an output terminal for the most significant bit signal CARRY in the address buffers / counters 20, 21, 22 for row / column addresses, and address buffers / counters 23, 24, 25 for block addresses. The signal CARRYIN and the signal CARRY are connected via multiplexers 26 to 30. Here, in the multiplexers 26 to 30, the input A is connected to the output O when the select S is “H”, and the input B is connected to the output O when the select S is “L”.
[0089]
For example, when the conventional address control circuit shown in FIG. 11 is used for erasing one block at a time, if the signal 1BLKERS is set to “H”, the address control circuit shown in FIG. The address control circuit shown in FIG.
[0090]
That is, when all the row / column addresses are counted up, AEND = H, and the block is selected one block at a time from the reset (all “0”) according to the block count-up clock signal BLKADV, and all the blocks are selected. BEND = H.
[0091]
In the batch erase of a plurality of groups according to the fourth embodiment, 1BLKERS in FIG. 11 is set to “L”. In the connection method of the multiplexers 26 to 30 shown in FIG. 11, only the signal CARRY of the address buffer / counter 23 corresponding to one bit of the lowest block address is stored in the address buffers / counters 20, 21, 22 for row / column addresses. Since it is connected to the most significant bit signal CARRY, it becomes an address control circuit corresponding to two groups of batch erase biases.
[0092]
The row address, the column address, and the lower 1 bit of the block address count up the address as one group, and when all of these are selected, AEND = H.
[0093]
Therefore, according to the erase sequence of FIG. 8, the erase sub-sequence is entered after the pre-erase write for two groups is completed. Accordingly, “H” is latched in the erase selection latches of both groups, and at the time of erasure, the two groups are simultaneously erase biased. In this case, the erase execution determination must be performed every time the lowest address of the block address changes.
[0094]
As described above, by using the address control circuit shown in FIG. 11, the blocks in the chip are divided into several groups, and the erase bias is simultaneously applied to a plurality of blocks in the group selected for erase in each group. It becomes possible to deal with examples.
[0095]
Groups to be erased at once are grouped according to the decoder configuration. FIG. 12 shows a decoding configuration of a two-stage decoding system consisting of main decoding / sub decoding. The two-stage decoding system shown in FIG. 12 includes memory blocks 31 to 34, a main decoder G13, sub-decoders G14 to G17, and inverters I15 and I16. The same configuration is repeated as shown in the upper part of FIG.
[0096]
When a two-stage decoding method comprising the main decoder G13 and the sub-decoders G14 to G17 is adopted, for example, it is selected by the main decoder using the lower 2 bits (BLKAD [0], BLKAD [1]) of the block address. Since four blocks are grouped, it is sufficient to perform batch erasure in units of four blocks.
[0097]
In this way, not only the address but also the internal power supply can be switched in units of main decoders, and the load capacity of the internal power supply can be made smaller than when biasing with a full chip. In a flash memory, a booster circuit using a charge pump is generally used as an internal power supply. Therefore, if the internal power supply is also used as a main decoder unit, the chip area can be reduced.
[0098]
A fifth embodiment will be described.
[0099]
Using the convergence bias shown in FIG. 14 (c), when bit lines are biased in the non-selected state of all word lines and weakly written into over-erased cells, erasing is performed by simultaneously biasing bit lines of a plurality of blocks. A description will be given of shortening the time required for the sequence.
[0100]
Since self-convergence is not selective writing with verify for each bit, if it is simultaneously biased to a column of a plurality of blocks, it can be executed in the same manner as a batch erasure of a plurality of blocks.
[0101]
Also in the self-convergence, similarly to the batch erase of a plurality of blocks, the signal MULTIBLK for block selection is set to “H”, and the corresponding columns of the plurality of erase selection blocks are simultaneously selected. The convergence bias shown in FIG. 14C is simultaneously applied to the selected column, and self-convergence writing to the over-erased cells of the selected column can be executed at once.
[0102]
As described above, according to the fifth embodiment, the time required for the erase sequence can be shortened by simultaneously applying the convergence bias to the corresponding columns of a plurality of blocks in the self-convergence writing.
[0103]
For example, in the fourth embodiment, an address control circuit using a binary counter, a carry circuit, and a multiplexer has been described. However, the present invention is not necessarily limited to this. Similar functions can be realized using other circuit configurations.
[0104]
Although the nonvolatile semiconductor device has been described as a NOR flash memory, the application target is not necessarily limited to the NOR type. If the circuit configuration and the erase sequence are slightly changed, the AND type, NAND type, DINOR The same can be applied to a flash memory such as a mold.
[0105]
【The invention's effect】
As described above, according to the nonvolatile semiconductor device and the erase sequence thereof of the present invention, the erase time can be greatly shortened by simultaneously biasing and erasing a plurality of blocks of memory cells.
[Brief description of the drawings]
FIG. 1 shows an erase sequence of a basic nonvolatile semiconductor memory device of the present invention.
FIG. 2 is a diagram showing a configuration of a nonvolatile semiconductor memory device according to a first example of the present invention.
FIG. 3 is a diagram showing an example of a block decoder circuit of the nonvolatile semiconductor memory device according to the first example of the present invention.
FIG. 4 is a diagram showing a block selection configuration of the nonvolatile semiconductor memory device according to the first example of the present invention.
FIG. 5 is a diagram showing an erase sequence according to the first embodiment of the present invention.
FIG. 6 is a diagram showing a configuration of a nonvolatile semiconductor memory device according to a second example of the present invention.
FIG. 7 is a diagram showing an ERASE pulse of the nonvolatile semiconductor memory device according to the third example of the present invention.
FIG. 8 is a diagram showing an erase sequence according to a fourth embodiment of the present invention.
FIG. 9 is a diagram showing an address control circuit of a conventional nonvolatile semiconductor memory device for an erase sequence.
FIG. 10 is a diagram showing a configuration of an address buffer / counter circuit of a conventional nonvolatile semiconductor memory device for erase sequence.
FIG. 11 is a diagram showing an address control circuit for realizing a fourth embodiment of the present invention.
FIG. 12 is a diagram showing a two-stage decoding method for realizing the fourth embodiment of the present invention.
FIG. 13 is a diagram showing an erase sequence of a conventional nonvolatile semiconductor memory device.
FIG. 14 is a diagram showing bias conditions of a conventional nonvolatile semiconductor memory device.
FIG. 15 is a diagram showing a cell array configuration of a conventional nonvolatile semiconductor memory device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Row decoder, 3 ... Column coder, 4 ... Block decoder, 5 ... Sense amplifier, 6 ... Address control circuit, 7 ... Command interface, 8 ... State machine, 9 ... Timer, 10 ... Protection register DESCRIPTION OF SYMBOLS 11 ... Internal power supply control circuit, 12 ... Source well decoder, 13 ... Redundancy fuse, 14-25 ... Address buffer / counter, 26-30 ... Multiplexer, 31-38 ... Memory block

Claims (11)

A plurality of blocks comprising a plurality of memory cells to be erased at one time and a decoder for selecting the memory cells;
A sense amplifier,
At the time of erasing, the address of the memory cell is counted , confirmation of erasing execution is performed to check whether the first block is selected as a block to be erased by a command or an erasure prohibited block , and the first block is confirmed. If the block is an erasure target, the first block is written before erasure, and similarly, the execution of the next block is confirmed. If the next block is the erasure target, the next block is erased. In the same manner, the execution of block erasure is confirmed for each block, and if it is an erasure target, the block is written before erasure , and then the blocks to be erased are batched. An address control circuit for controlling the sequence to be erased,
Each of the blocks has a block decoder that latches the selection signal of the block at the time of programming before erasure and simultaneously selects all the blocks at which the selection signal is latched at the time of erasure,
A non-volatile semiconductor memory device in which all blocks in which the selection signal is latched are controlled to be collectively erased by the address control circuit. 2. The nonvolatile semiconductor memory device according to claim 1, wherein when erasing all the blocks in which the selection signal is latched, the erase bias is applied for a longer time than when erasing one block. When batch erase all blocks in which the selection signal is latched, the nonvolatile semiconductor memory device according to claim 1, wherein the shifting the applying time point of the erase bias for each of the blocks. The nonvolatile semiconductor memory device further includes a redundant block that replaces a defective block, and an address holding element of the defective block that replaces a block address with the redundant block when the defective block is accessed,
If the defective block is selected for erasure, the defective block replaced redundant block, when the pre-write and erase latches the selection signal of the redundant block, the time of erasing, all of the selection signal is latched Each has a block decoder that simultaneously selects redundant blocks,
2. The nonvolatile semiconductor memory device according to claim 1, wherein all the redundant blocks in which the selection signal is latched and all the blocks in which the selection signal is latched are controlled by the address control circuit so as to be erased at once. A circuit for selecting a column of the memory cell and applying a write voltage after the batch erasing, and performing weak writing at once on the memory cell connected to the column;
2. The circuit according to claim 1, wherein when the circuit is used, a column selected by the same column address in all blocks in which the selection signal is latched is collectively written into all the blocks erased collectively. Nonvolatile semiconductor memory device. A plurality of blocks comprising a plurality of memory cells to be erased at one time and a decoder for selecting the memory cells;
A sense amplifier,
Dividing the plurality of blocks into a plurality of groups, counting the addresses of the memory cells at the time of erasing, and checking whether the first group is selected as a group to be erased by a command or a group for which erasure is prohibited If the first group is an erasure target, all the blocks in the first group are erased collectively by performing pre-erase writing on all the blocks in the first group. and, similarly, confirms the erasure execution of the next group, the next if the group is in erasure of the target, the next group by performing a pre-erase write for all blocks in the next group all blocks collectively erased in, and so on, confirms the erasure execution of the group, erasing foreword write of the group if the erasure of the target The and an address control circuit for controlling the sequence for collectively erasing all blocks in the group by performing,
Each of the blocks has a block decoder that latches the selection signal of the block at the time of programming before erasure and simultaneously selects all the blocks at which the selection signal is latched at the time of erasure,
A nonvolatile semiconductor memory device in which the block in which the selection signal is latched is controlled to be collectively erased by the address control circuit. A circuit for selecting a column of the memory cell and applying a write voltage after the batch erasing, and performing weak writing at once on the memory cell connected to the column;
The function of performing weak writing on all the blocks erased at once by collectively using the columns selected by the same column address in all the blocks in which the selection signal is latched when using the circuit. Nonvolatile semiconductor memory device. A method of executing an erase sequence for collectively erasing a plurality of blocks each including a plurality of memory cells, wherein the block latches a selection signal of the block at the time of programming before erasure, and the selection signal at the time of erasure Each having a block decoder that simultaneously selects all the latched blocks, and the blocks in which the selection signals are latched are controlled to be collectively erased by an address control circuit,
The address control circuit includes:
Counting the address of the memory cell;
Check whether the first block is selected as a block to be erased by a command or whether the block is forbidden to be erased. If the first block is to be erased, the first block Write before erasure,
Similarly, confirmation of execution of erasure of the next block is performed, and if the next block is to be erased, writing before erasure of the next block is performed,
In the same manner, the execution of block erasure is confirmed for each block.
After that, erase all the blocks to be erased at once.
A method for executing an erase sequence of a nonvolatile semiconductor memory device. 9. When the pre-erase write is not required for the block, the block is skipped and the execution of the erase is confirmed for the next block. Of executing an erasing sequence of the nonvolatile semiconductor memory device of the present invention.   9. The method of executing an erase sequence of a nonvolatile semiconductor memory device according to claim 8, wherein when writing before erasure is completed for all blocks, a flag is added only to the block to be erased. 9. The method of executing an erase sequence of a nonvolatile semiconductor memory device according to claim 8, wherein the plurality of blocks are divided into a plurality of groups, and all the blocks in each group are erased collectively.

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