JP2003323798A - Semiconductor storage device and method of controlling the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device and a method for controlling the same, by which data access is accelerated and a data transfer rate is improved by reducing the refresh operation cycle using stable low-consumption current operation. <P>SOLUTION: A control signal SW is output prior to a refresh operation mode signal M(I), and respective switch parts 13 and 14 select a holding address bus LAdd and a holding redundancy discrimination result bus LJ from respective holding parts 11 and 12 and output address information, which is a refresh operation object to a word-line drive system circuit 64. After the address information from the respective holding parts 11 and 12 is output, a control signal LCH is output, an address-switching part 10 selects a refresh address bus Add(I) which is the object of the next refresh operation, and the respective holding parts 11 and 12 hold an address Add(I) taken into an internal address bus IAdd and its redundancy discrimination result (I). <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a refresh operation and a control method thereof, and more particularly to a semiconductor memory device capable of realizing a reduction in refresh operation time by a low current consumption operation. And a control method thereof.

[0002]

2. Description of the Related Art In recent years, with the spread of mobile devices, the functions required for the devices have increased, and as a result, static random access memories (hereinafter referred to as SRA) that have been conventionally installed have been installed.
(Abbreviated as M), a semiconductor memory having a larger capacity has been required. Therefore, while using highly integrated DRAM memory cells as compared to SRAM memory cells,
Since a DRAM memory cell has a built-in control related to a refresh operation, an external control circuit such as a refresh controller is unnecessary, and a DRAM having a refresh function, which has a data access operation equivalent to that of an SRAM and has a refresh function, has been used. ing.

In the pseudo SRAM, a data access operation cycle in which a data access operation and a subsequent precharge operation are externally controlled as one operation cycle, and a refresh operation and a subsequent precharge operation are internally controlled as one operation cycle. The refresh operation cycle is performed independently at any time. Therefore, the refresh operation cycle must compete with the data access operation cycle, or the refresh operation cycle must be interrupted in consecutive data access operation cycles. That is, the refresh operation cycle is executed regardless of the request for the data access operation cycle under external control. Therefore, it is necessary to shorten the refresh operation cycle in order to speed up the data access operation or improve the data transfer rate.

Here, in the refresh operation cycle,
The refresh operation is performed on the memory cell corresponding to the refresh address Add (I) output by the built-in address counter or the like. In the data access operation cycle, the data access operation is performed on the memory cell corresponding to the data access address Add (O) input from the outside.

FIG. 19 shows a conventional technique in which the refresh operation cycle is shortened. Japanese Patent Laid-Open No. 11-120790
Redundancy discrimination circuit 7 of the third embodiment disclosed in Japanese Patent Publication
Shows a circuit block diagram with 00c. FIG. 19 is a circuit block which selects either the data access address Add (O) or the refresh address Add (I) and supplies the address to the address decoder 300 via the address register 400.

The redundancy discriminating circuit 700c has the following configuration. The data access address Add (O) is input to the input terminal A of the selection circuit 760, and the refresh address Add (I) is input to the input terminal B. Selection circuit 7
An internal command signal cpf is applied to the selection control signal input terminal SB of 60.
Is entered. The output signal n00 of the selection circuit 760 is input to the coincidence detection circuit 770 together with the redundant address. The output signal n100 of the match detection circuit 770 is input to the input terminal D of the flip-flop 780 and the input terminal A of the selection circuit 790. The operation timing of the flip-flop 780 is controlled according to the clock signal CLK. The internal command signal cpf is input to the load input signal LD, and its output signal n200 is input to the input terminal B of the selection circuit 790. The internal command signal ref is input to the selection control signal input terminal SB of the selection circuit 790.

The address register 400 has the following structure. Data access address Add (O)
Each of the refresh address Add (I) and the refresh address Add (I) are input to one end of the selection switch. The other ends of the selection switches are both input to a latch circuit configured by an inverter gate or the like. The output from the latch circuit is connected to the address decoder 300 via a logic level adjusting inverter gate provided as necessary. The selection switch is controlled by the output signal of the redundancy judgment circuit 700c.

FIG. 20 shows operation waveforms. Clock signal CL at which the refresh operation cycle (Ref1) is started
When the internal command signal ref transitions to the high level after the start of the first cycle of K, the input terminal B of the selection circuit 790 is selected and the signal n200 which is the result of the match detection of the redundancy judgment of the (A-1) address is output. . (A-1) When the address is a detection result that does not match the redundant address, the output switch signal n200 and the refresh operation mode control signal (not shown) control the selection switch of the address register 400 to refresh the refresh address. Add (I)
Is captured.

After the start of the second cycle of the clock signal CLK, the internal command signal ref transits to the low level to deactivate the selection circuit 790. Further, the internal command signal cpf transits to the high level to select the input terminal B of the selection circuit 760. As a result, it has already been incremented (A)
The refresh address Add (I) of the address is taken into the match detection circuit 770, and the match detection result is output as the output signal n1.
Output as 00. Output signal n10 obtained at this time
The match detection result of 0 is the result for the address (A). This result is taken into the flip-flop 780 in synchronization with the rising of the third cycle of the clock signal CLK. Taken into flip-flop 780 (A)
The match detection result of the address refresh address Add (I) is the refresh operation of the next cycle (Ref2).
Are taken out after the start of the first cycle of the clock signal CLK, which is the start cycle of.

Here, the internal command signal cpf is the data access address Add in the redundancy judgment circuit 700c.
(O) or the refresh address Add (I) is a signal for controlling which address is selected. The data access address Add (O) is selected in the low level state and the refresh address Add is selected in the high level state.
Select (I). Therefore, it is a signal that makes a signal transition substantially in synchronization with each operation cycle. That is, it is in the low level state in the data access operation cycle and is in the high level state in the refresh operation cycle.

The refresh address Add (I) associated with the refresh operation is preceded by one operation cycle to detect a match with the redundant address, and no match detection operation is performed during the refresh operation cycle.

[0012]

However, as shown in FIG.
In the prior art shown in FIGS. 9 and 20, the selection switch in the address register 400 is selected by the high level transition of the internal command signal ref after the refresh operation is started, and the refresh address Add to the address register 400 is selected.
The address path of (I) is established. Therefore, the rewriting of the latch unit in the address register 400 is performed after the refresh operation is started. In a semiconductor memory such as a pseudo SRAM having an operation specification in which a data access operation mode and a refresh operation mode are independently required, the data access operation cycle may be before the start of the refresh operation cycle. In this case, it is necessary to change the selection switch. Although the refresh address Add (I) in the refresh operation cycle of the next cycle has been previously determined, the latch operation of the refresh address Add (I) to the address register 400 cannot be advanced. This is a problem because the refresh operation cycle time cannot be shortened.

In the operation specification in which the refresh operation cycle is preferentially performed when the operation request of the refresh operation mode and the operation request of the data access operation mode occur at the same time, the data access operation cycle is performed after the end of the refresh operation cycle. . Since the refresh operation cycle is not shortened, the data access time is not shortened, and high-speed data access cannot be realized, which is a problem. In addition, including a case where the data access operation cycle is preferentially executed, a cycle time formed by a pair of a refresh operation cycle and a data access operation cycle, or a plurality of data accesses continuous with the refresh operation cycle It is not possible to shorten the cycle time configured with one set of operation cycles. This is a problem because the data transfer rate cannot be improved.

In the flip-flop 780 of the redundancy judgment circuit 700c, the refresh operation cycle (Ref
In response to the internal command signal cpf that has transited to the high level after the rise of the clock signal CLK of the second cycle in 1), the signal n10 is received at every rise transition of the clock signal CLK of the third to ninth cycles during the refresh operation period.
The operation of taking in 0 is repeated. In the refresh operation, activation of the word line and differential amplification of the bit line pair,
Then, the word line is deactivated and the bit line pair is equalized. At this time, many memory cells are connected to the word line and the bit line to be driven, and the wiring length is long. Therefore, a large load capacitance must be charged / discharged as the sum of parasitic capacitance and wiring capacitance, and the peak current during charging / discharging becomes large. Signal n
Since the capturing operation of 100 is repeatedly performed, there is a great possibility that the coincidence detection circuit 770, the flip-flop 780, and the like will be adversely affected by voltage fluctuations such as the power supply voltage and the ground voltage due to a large peak current, and the signal n1.
The voltage level of 00 and the circuit threshold level may fluctuate, which may cause erroneous latching in the flip-flop 780, which is a problem.

In the prior art, in order to speed up the data access operation, the refresh operation cycle (Ref1)
In the precharge period (PRE) after the end (9th cycle of the clock signal CLK), the internal command signal cpf becomes low level and the selection circuit 760 transits to the selected state of the data access address Add (O). Further, the internal command signal ref also maintains the low level state. As a result, if the match detection circuit 770 detects a mismatch, the data access address Add (O) is latched in the address register 400 via the selection circuit 790. However, since the valid data access address Add (O) is input after the start of the data access operation cycle, the data access address A in this case is
dd (O) is not valid address information. Therefore, when the next cycle is the data access operation cycle or the refresh operation cycle (Ref2) (see FIG. 20), the latch information of the address register 400 is rewritten and the match detection circuit 770 performs the match detection again. Will be required. Invalid data access address Add input during the valid operation period
Due to (O), a match detection operation with an unnecessary redundant address and an address latch operation are performed, so that the current consumption cannot be reduced, which is a problem. Unnecessary current consumption is inevitably increased with the increase in the number of address bits and the redundant configuration, which becomes more and more problematic as the capacity increases.

For memory cells having good data retention characteristics, the refresh operation is not performed for each refresh request, but the refresh operation is set to be performed once every predetermined number of times. There has been proposed a semiconductor memory having a so-called thinning refresh function, which reduces the number of operations to reduce current consumption during refresh operation. However, in the conventional technique, the match detection operation with the redundant address is performed before the refresh address Add (I) that is thinned out and the refresh operation is not performed.
This is a problem because it is not possible to reduce current consumption due to unnecessary circuit operation. As the capacity increases, the number of redundant configurations increases, resulting in a large amount of unnecessary circuit operations, which is a problem.

The present invention has been made in order to solve the above-mentioned problems of the prior art, and shortens the refresh operation cycle and speeds up data access by stable low current consumption operation without being affected by noise. Another object of the present invention is to provide a semiconductor memory device capable of improving the data transfer rate and a control method thereof.

[0018]

In order to achieve the above object, a semiconductor memory device according to a first aspect of the present invention has a first operation mode in which a first address to be accessed is designated for each access and an access operation is performed. , The second operation mode which is executed asynchronously with the first operation mode and performs the access operation by designating the second address to be accessed for each access according to a predetermined order. Connected to the bus, redundancy judgment result bus,
Access to the second address in the second operation mode of the next time, the address holding unit that stores the redundancy judgment result, the redundancy judgment result holding unit, and the first or second operation mode by the control signal prior to the second operation mode of the next time. In this case, an internal address bus or address holding unit and a first and second switching unit for selecting the redundancy judgment result bus or the redundancy judgment result holding unit are provided.

According to another aspect of the semiconductor memory device of the present invention, at the time of access in the first or second operation mode, the first switching unit stores the first address stored in advance in the first address or the address holding unit on the internal address bus. One of the two addresses is selected, and the second switching unit selects either the redundancy judgment result of the first address on the redundancy judgment result bus or the redundancy judgment result of the second address stored in advance in the redundancy judgment result holding unit. Select. The address holding unit and the redundancy judgment result holding unit store the second address and its redundancy judgment result in the next second operation mode from the internal address bus and the redundancy judgment result bus prior to the next second operation mode. It

Further, in the control method of the semiconductor memory device according to an eighth aspect, the first address and the redundancy judgment result of the first address or the second pre-held second address are the access targets in the first or second operation modes. An access target selecting step of selecting an address and its redundancy judgment result, and a second address and its redundancy judgment result as an access target in the next second operation mode after the selection of the second operation mode in the access target selecting step. And an operation target holding step for holding in advance.

As a result, the second address specified in the predetermined order will be the second address of the next time.
Since the second address to be accessed can be determined prior to the operation mode, the second address in the next second operation mode and the redundancy determination result obtained by performing the redundancy determination on this address are held in advance. You can keep the second
It is not necessary to perform the second address determination operation, the second address redundancy determination operation, and the redundancy determination result determination operation at the start of the operation mode. Therefore, the operation period of the second operation mode can be shortened.

When the first operation mode and the second operation mode are a pair of access operations, the cycle time can be shortened, and when the second operation mode is prioritized, the access time of the first operation mode can be shortened. Can be shortened.
Further, when the second operation mode is performed between the first operation modes as needed, the occupation rate of the first operation mode can be improved.

According to a second aspect of the semiconductor memory device,
The semiconductor memory device according to claim 1, further comprising a predecoding unit that predecodes at least one of the first and second addresses, and the internal address bus and the redundancy determination result bus include the predecoded address and the predecoded address. A feature is that a redundancy judgment result is output.

According to another aspect of the semiconductor memory device of the present invention, at least one of the first and second addresses is predecoded by the predecoding unit and transmitted to the internal address bus, and the predecoded second address and its redundancy are provided. The judgment result is stored in the address holding unit and the redundancy judgment result holding unit from the internal address bus and the redundancy judgment result bus.

As a result, prior to the second operation mode,
Since the predecoding process of the second address can be performed in advance, the operation period of the second operation mode can be further shortened.

According to a third aspect of the semiconductor memory device,
2. The semiconductor memory device according to claim 1, wherein each operation cycle is configured with an operation period of the first or second operation mode and a non-operation period from the end of the operation period to the start of the next operation period as one unit. , The first or second operation mode is set, and an address switching unit for establishing an address path for outputting the first or second address to the internal address bus is provided, and the address switching unit includes the first or second address switching unit.
When the operation mode is switched between the operation modes, the address path is switched only at the first switching timing after the start of the operation cycle.

According to a fourth aspect of the semiconductor memory device of the present invention,
2. The semiconductor memory device according to claim 1, further comprising an address switching unit that captures and latches the first or second address and outputs the latched address to an internal address bus, and the address switching unit has a first capture timing after the start of the operation cycle. Only in, the first or second address is fetched and latched.

According to another aspect of the semiconductor memory device of the present invention, the address switching unit switches the address path only at the first switching timing after the start of the operation cycle in which the operation mode is switched. Only at the first fetch timing after the start, the first or second address is fetched and latched by the address switching unit.

According to a fifth aspect of the semiconductor memory device of the present invention,
2. The semiconductor memory device according to claim 1, wherein each operation cycle includes an operation period of the first or second operation mode and a non-operation period from the end of the operation period to the start of the next operation period as one unit. , The first or second operation mode is set, and the first and second switching units switch the operation mode between the first and second operation modes only at the second switching timing after the start of the operation cycle. , Internal address bus or address holding unit,
Further, the selection of the redundancy judgment result bus or the redundancy judgment result holding unit is switched.

According to a sixth aspect of the semiconductor memory device of the present invention,
2. The semiconductor memory device according to claim 1, wherein the first and second switching units capture and latch outputs from the internal address bus or address holding unit and the redundancy judgment result bus or redundancy judgment result holding unit. A second latch section is provided, and the internal address bus or the address holding section and the redundancy judgment result bus or the redundancy judgment result holding section are selected only at the second fetch timing after the start of the operation cycle.

According to another aspect of the semiconductor memory device of the present invention, the internal address bus or the address holding unit and the redundancy judgment result bus are provided by the first and second switching units only at the second switching timing after the start of the operation cycle in which the operation modes are switched. Alternatively, the selection of the redundancy judgment result holding unit is switched, and in the semiconductor memory device according to claim 6, the first judgment is made only at the second acquisition timing after the start of the operation cycle.
In the second switching unit, the internal address bus or the address holding unit and the redundancy judgment result bus or the redundancy judgment result holding unit are selected and taken in.
It is latched by the latch part.

A method of controlling a semiconductor memory device according to a ninth aspect is the method of controlling a semiconductor memory device according to the eighth aspect, wherein the first address is supplied to the access target selecting step or the operation target holding step is performed. At least one of switching of the selection in the access target selecting step and switching of the supply in the address supplying step only after the start of the operation cycle in which the operation mode is switched. It is characterized by performing.

As a result, the address setting becomes undefined during the non-operation period, unnecessary address input and redundancy judgment operation are not performed, and unnecessary current consumption due to unnecessary circuit operation can be suppressed. It is possible to effectively reduce the current consumption when the number of address bits and the redundant configuration increase as the capacity increases.

A semiconductor memory device according to a seventh aspect is
The semiconductor memory device according to claim 1, further comprising an executability determination unit that determines whether or not the second operation mode can be executed for each second address, and the second address that is determined to be non-executed by the executability determination unit. Inhibits the supply of the second address to the internal address bus, deactivates the control signal, and, in the non-execution second operation mode, the first and second
It is characterized in that the selection of the switching unit is prohibited.

A semiconductor memory device control method according to a tenth aspect of the present invention is the semiconductor memory device control method according to the eighth aspect, wherein the execution propriety is determined for each second address. It is characterized that the access target selecting step and the operation target holding step are prohibited with respect to the second address which has a judging step and is judged not to be executed by the executability judging step.

As a result, the second operation mode is not performed for the second address that has been determined to be non-executed, so that the second address is stored in the address holding unit prior to the second operation mode. Redundancy determination of 2 addresses, and second
It is possible to prohibit storage of the redundancy judgment result of the address in the redundancy judgment result holding unit, prohibit the selection of the first and second switching units, and reduce the current consumption due to unnecessary circuit operation. It is possible to effectively reduce the current consumption when the number of address bits and the redundant configuration increase as the capacity increases.

[0037]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a semiconductor memory device of the present invention,
First to fourth embodiments of the invention and a control method thereof will be described in detail with reference to the drawings based on FIGS. 1 to 18.

The first embodiment shown in FIG. 1 is a case where the present invention is applied to a semiconductor memory device having an operation specification in which a built-in refresh operation and an external data access operation are independently operated at any timing. Is. Since the refresh operation mode and the data access operation mode can be operated independently of each other, an external controller for the refresh operation is unnecessary, and the pseudo SR
It is a semiconductor memory device that has more complete compatibility with SRAMs such as AMs. Note that FIG. 1 shows only a portion related to the row address system.

The predetermined control terminal 50 is connected to the I / O controller 54 and outputs an external access request signal REQ (O) in response to a control signal input from the control terminal 50. The external access request signal REQ (O) is connected to the row address buffer 52 together with the address signal input from the address terminal 50 having a predetermined number of bits, and outputs the data access address Add (O) to the address switching unit 10.

The refresh request signal REQ (I) output from the built-in refresh timing timer 56 every predetermined time is input to the refresh address counter 53. The refresh address Add (I) is input from the refresh address counter 53 to the address switching unit 10.

The external access request signal REQ (O) output from the I / O controller 54 is the refresh request signal R.
It is input to the access arbiter 60 together with EQ (I).
The access arbiter 60 receives request signals REQ (O) and REQ (I) input as level signals or pulse signals.
By detecting the level transition of, it is possible to detect the leading and trailing of the generated signal between the request signals. From the access arbiter 60, when the external access request signal REQ (O) has priority, the data access operation mode signal M (O) gives priority to the refresh request signal REQ (I) as the detection result of the signal before and after. The refresh operation mode signal M (I) is output to the mode determination unit 62.

In the mode determining section 62, the control signal LC is supplied in accordance with the input operation mode signals M (O) and M (I).
H and SW are output. The control signal LCH is input to the address switching unit 10, and the address to be supplied to the internal address bus IAdd is set to the data access address Add.
Control is performed to switch between (O) and refresh address Add (I).

Further, the refresh address Add is input to the internal address holding unit 11 and the internal address redundancy judgment result holding unit 12 and is applied to the internal address bus IAdd.
When (I) is supplied, the storing operation in each of the time keeping units 11 and 12 is controlled. An internal address bus IAdd is connected to the internal address holding unit 11 and holds a refresh address Add (I) which is controlled by the control signal LCH and is supplied to the internal address bus IAdd. The redundancy judgment result bus RJ from the redundancy judgment unit 15 connected to the internal address bus IAdd is input to the internal address redundancy judgment result holding unit 12 and is supplied to the internal address bus IAdd under the control of the control signal LCH. The redundancy judgment result RJ (I) for the refresh address Add (I) is held.

The control signal SW is input to the switching unit A (13) and the switching unit J (14) and stored in the data access address Add (O) or the internal address holding unit 11 supplied to the internal address bus IAdd, respectively. Refresh address Add (I) and the data access address Add (O) from the redundancy determination unit 15
Redundancy judgment result RJ (O) or the holding redundancy judgment result LJ stored in the internal address redundancy judgment result holding unit 12
One of (I) is selected to access the address bus MAdd for access and the redundancy judgment result bus MJ for access.
Is output to.

The access target address bus MAdd and the access target redundancy judgment result bus MJ are connected to the word line drive system circuit 64. The word line drive system circuit 64 performs a decoding process or the like on the input address to be accessed and the redundancy judgment result (hereinafter, both are collectively referred to as address information), and thereby the corresponding word line WL0 to WLn. (Hereinafter, collectively referred to as WLs) is selectively activated. In this case, depending on the redundancy judgment results RJ (O) and RJ (I) that are input, the word line WL
Redundant word lines SWL0 to SWLm instead of 0 to WLn
(Hereinafter, collectively referred to as SWLs) is selectively activated. The selectively activated word line WLs or redundant word line SWLs is input to the memory cell array 66 and selects a memory cell to be accessed.

In the semiconductor memory device of the first embodiment, the data access operation mode required by the input of the control signal from the control terminal 50 and the refresh operation mode required by the built-in refresh timing timer 56 at predetermined time intervals. And are required to operate independently of each other. Therefore, the access arbiter 60 requests the request signal REQ.
After the adjustment between (O) and REQ (I) is performed, the operation to be executed is determined. Specifically, the control signal input from the control terminal 50 is input to the I / O control unit 54 and an external data access request is output to the access arbiter 60 as an external access request signal REQ (O). A refresh trigger request REQ (I) is output from the refresh timing timer 56, and the access arbiter 60
A request for refresh operation is output to.

The access arbiter 60 has an external access request signal REQ (O) and a refresh request signal REQ.
When one of the request signals (1) and (I) is output, either the data access operation mode signal M (O) or the refresh operation mode signal M (I) is corresponding to the requested operation. One operation mode signal is output. When the operation requests conflict with each other, the external access request signal REQ (O) and the refresh request signal REQ (I) are adjusted, and the operation mode signal M (O) or M
After either one of (I) is output with priority, one of the operation mode signal M (I) or M (O) which is the other operation is output following the end of the operation. Either the control of prioritizing the refresh operation prior to avoiding the loss of data or the control of prioritizing the external data access operation prioritizing the response of the external access can be selected in advance. Regardless of the order of the operation sequence, the cycle time tCE is defined by both continuous operations.

When the data access operation mode signal M (O) is output from the access arbiter 60, the address switching unit 10 causes the data access address bus Add by the control signal LCH output from the mode determination unit 62.
When (O) is selected, the data access address A from the row address buffer 52 is input to the internal address bus IAdd.
dd (O) is captured. Further, the internal address holding unit 11 and the internal address redundancy judgment result holding unit 12 are maintained in the holding state, and the data access address Add (O) fetched on the internal address bus IAdd and the data output by the redundancy judgment unit 15 are held. The redundancy judgment result RJ (O) of the access address Add (O) is not newly stored.

Further, according to the control signal SW output from the mode determination unit 62, the switching unit A (13) and the switching unit J (14) select the internal address bus IAdd and the redundancy determination result bus RJ to access. The data access address Add (O) is applied to the address bus MAdd.
Are taken in, and the redundancy judgment result RJ (O) is taken in to the access target redundancy judgment result bus MJ.

The address signal input from the address terminal 50 is selected as the data access address Add (O) via the row address buffer 52 by the address switching unit 10 and taken into the internal address bus IAdd. It is selected by (13) and taken into the access target address bus MAdd. The data access address Add (O) fetched on the internal address bus IAdd is simultaneously subjected to redundancy judgment by the redundancy judgment unit 15, and the redundancy judgment result RJ (O) becomes the switching unit J (14).
Is selected in step S4 and fetched in the access target redundancy judgment result bus MJ.

The mode determination section 62 is operated by the operation mode signal M.
(O), M (I) each time the control signal LCH,
Since the SW is switched, once the data access operation mode signal M (O) is input, the control signals LCH and SW are maintained in the above states until the refresh operation mode signal M (I) is input, and each address bus IAdd, MA
An address path through which the data access address Add (O) is propagated is established in dd.

When the refresh operation mode signal M (I) is output from the access arbiter 60, the mode determination unit 6
The address switching unit 10 selects the refresh address bus Add (I) according to the control signal LCH output from No. 2, and the refresh address Ad from the refresh address counter 53 is input to the internal address bus IAdd.
d (I) is captured. Further, the internal address holding unit 1
1 and the internal address redundancy judgment result holding unit 12 enter the storage state of the address information, and the redundancy judgment of the refresh address Add (I) taken in the internal address bus IAdd and the refresh address Add (I) output by the redundancy judgment unit 15 The result RJ (I) is stored.

The control signal SW output from the mode determination unit 62 causes the switching unit A (13) and the switching unit J (14) to hold the internal address holding unit 11 and the internal address redundancy judgment result holding unit 12. The address bus LAdd and the holding redundancy judgment result bus LJ are selected, and the refresh address A stored in the internal address holding unit 11 is stored in the access target address bus MAdd.
dd (I) is fetched, and the redundancy judgment result RJ (I) of the refresh address Add (I) stored in the internal address redundancy judgment result holding unit 12 is fetched in the access target redundancy judgment result bus MJ.

The refresh operation is started for the refresh address Add (I) stored in the internal address holding unit 11 and the redundancy judgment result RJ (I) stored in the internal address redundancy judgment result holding unit 12. Immediately thereafter, the data is taken into the access target address bus MAdd and the access target redundancy judgment result bus MJ, and after the completion of the fetching, the internal address holding unit 11 and the internal address redundancy judgment result holding unit 12 receive data until the next refresh operation is performed. The storage needs to be completed.

When the refresh request signal REQ (I) is adjusted by the access arbiter 60 and the refresh operation mode signal M (I) is output, the mode determining section 62 outputs the control signal SW in advance, and the switching section. A
The holding address bus LAdd and the holding redundancy judgment result bus LJ are selected by (13) and the switching unit J (14) to start the refresh operation. Each timekeeping section 1
From 1 and 12, the refresh address Add (I) and its redundancy determination result RJ (I) are used as the address information to be refreshed, and the word line drive system circuit 6
Taken in 4.

After the address information stored in each time keeping unit 11 and 12 is output, it is necessary to update the stored contents. That is, it is necessary to update the address information to be the target of the next refresh operation. This update is performed by the control signal LCH from the mode determination unit 62. The timing of this update can be any timing before the start of the next operation mode. It may be during the operation period in which the current refresh operation is performed or during the precharge period after the current refresh operation is completed. Within the period until the start of the next operation mode, the access arbiter 60 does not output the next operation mode signals M (O) and M (I). When the next operation mode is the refresh operation, the unupdated address information from the holding units 11 and 12 is not taken into the word line drive system circuit 64. Further, when the next operation mode is the data access operation mode, the data access address bus Add (O) is selected by the address switching unit 10 and the refresh address Add (I) to be updated from the refresh address counter 53. Can be supplied.

The refresh address Add (I) and the redundancy judgment result RJ of the respective time keeping units 11 and 12 which have been updated.
(I) is continuously held in each of the holding units 11 and 12 regardless of the operation state until the next refresh operation.

Although not shown, the refresh timing signal REQ from the refresh timing timer 56.
By outputting the control signal at a predetermined timing preceding (I), the control signal LCH is output to output the refresh address Add (I) during the period in which the operation mode signals M (O) and M (I) are not output. Alternatively, the redundancy judgment result RJ (I) may be taken into each of the holding units 11 and 12.

It goes without saying that the count value of the refresh address counter 53 should be updated before selecting the refresh address bus Add (I) by the control signal LCH.

The refresh address Add (I) from the refresh address counter 53 is updated in parallel with the refresh operation. Then, the updated refresh address Add (I) is selected by the address switching unit 10 by the control signal LCH and taken into the internal address bus IAdd before the start of the refresh operation corresponding to the Add (I). It is stored in the address holding unit 11. At the same time, the redundancy judgment unit 15 makes a redundancy judgment, and the redundancy judgment result RJ (I) is stored in the internal address redundancy judgment result holding unit 12. These pieces of address information are held until the start of the corresponding refresh operation.

At the start of the corresponding refresh operation,
The refresh signal Add (I) and the redundancy determination result RJ (I) held in the respective holding units 11 and 12 are selected by the control signal SW by the switching unit A (13) and the switching unit J (14), Access target address bus MAdd and access target redundancy judgment result bus M
The word line WLs or the redundant word line SWL after being taken in by J and decoded in the word line drive system circuit 64 and the like.
It is output to the memory cell array 66 as s.

The mode determination section 62 is operated by the operation mode signal M.
(O), M (I) each time the control signal LCH,
Since the SW is switched, once the refresh operation mode signal M (I) is input, the control signals LCH, S are input until the data access operation mode signal M (O) is input.
W is maintained in the above state, and the internal address bus IAdd
The refresh address Add (I) is propagated to.
Further, the access target address bus MAdd and the access target redundancy judgment result bus MJ are connected to the holding address bus L.
Since Add and the holding redundancy judgment result bus LJ are selected, the refresh address Add held in advance is added.
(I) and the redundancy judgment result RJ (I) can be supplied to the word line drive system circuit 64, and the supply time of address information can be shortened.

FIG. 2 shows a specific example of the circuit configuration of the subsequent stage from the address switching unit 10 of the first embodiment.
The address switching unit 10 is configured to include a switching circuit 101 for each address bit, and each switching circuit 101 has each address bit information of the data access address Add (O) and the refresh address Add.
It is composed of switch sections SW1 and SW2 for switching each address bit information of (I), and an inverter gate I4 for logically inverting the control signal LCH.

The redundancy determining section 15 determines whether the data access address Add (O) or the refresh address Add is added.
A redundancy determination circuit 151 is provided for each address information set as (I). Each redundancy judgment circuit 15
1, the address information set as the data access address Add (O) or the refresh address Add (I) is provided with a comparison unit CP1 for each address bit information, and each address bit information and redundant address information not shown are provided. The address bit information is compared bit by bit. The redundancy judgment result RJ (O) or RJ (I) is output to the redundancy judgment result bus RJ as a judgment result of whether the data access address Add (O) or the refresh address Add (I) matches the redundancy address. It The redundancy configuration is selected by the redundancy judgment result RJ (O) or RJ (I) output when the address information matches. The redundancy determining circuit 151 is provided for each redundant address in correspondence with the number of replaceable redundant configurations.

The internal address holding unit 11 comprises a holding circuit 111 for each address bit, and each holding circuit 111 fetches each address bit information of the refresh address Add (I) on the internal address bus IAdd. The switch unit SW3 and a latch unit for latching the address bit information of the fetched refresh address Add (I) are provided. The latch section is configured by connecting the input / output terminals of the inverter gates I5 and I6 to each other. An inverter gate I7 is connected to the output terminal of the latch section, and the output terminal of the inverter gate I7 constitutes a holding address bus LAdd.

Further, the internal address redundancy judgment result holding unit 1
Reference numeral 2 is configured to include a holding circuit 111 for each redundancy judgment result bus RJ, and its output terminal forms a holding redundancy judgment result bus LJ.

Like the address switching unit 10, the switching unit A (13) comprises a switching circuit 101 for each address bit, and each switching circuit 101.
Each of the switch sections SW1 and SW2 of the respective address bit information of the data access address Add (O) propagated to the internal address bus IAdd and the holding address bus LAd held in the holding circuit 111 in advance.
Refresh address Add (I) output to d
And each address bit information of is input. The address bit information is switched by the control signal SW and output to the access target address bus MAdd.

The switching unit J (14) is a switching unit A.
It has the same configuration as (13). Switching circuit 10
For each 1, the redundancy judgment result RJ (O) of the data access address Add (O) output to the redundancy judgment result bus RJ.
And the refresh address A previously held in the holding circuit 111 and output to the holding redundancy judgment result bus LJ.
The redundancy judgment result RJ (I) of dd (I) is the control signal S
It is switched by W and output to the access target redundancy judgment result bus MJ.

In the word line drive system circuit 64, the access target address bus MAdd is connected to the predecoder PD, and the predecoder PD is connected to the main decoder MD. The address information propagated to the access target address bus MAdd is decoded. The decoded address information passes through the word line driver WD to selectively activate a predetermined word line WL. The access target redundancy judgment result bus MJ is connected to the redundancy word line driver SWD, and also connected to the inhibit (INH) terminals of the predecoder PD and the main decoder MD. Redundancy determination result RJ propagated to access target redundancy determination result bus MJ
When (O) or RJ (I) indicates a match with the redundant address, the predecoder PD and the main decoder MD are deactivated, and a predetermined redundant word line SWL is selectively activated from the redundant word line driver SWD. ..

In the specific example of FIG. 2, the address switching unit 1
0, switching unit A (13), and switching unit J (1
4) is composed of a switching circuit 101, and switches SW depending on the logic levels of the control signals LCH and SW.
One of SW1 and SW2 is statically conducted to establish a signal path. The established signal path is the switch unit SW1,
It is maintained until re-switching by SW2.

The control signals LCH and SW are set in the operation mode M.
It is possible to perform control to switch the address path by inverting the logic level at the timing when (O) and M (I) are switched. Further, in order to secure high-speed response for external data access operation, an address path for the data access address bus Add (O) is established as a standard address path, and the refresh request signal REQ (I The refresh address mode Add (I) may be switched to when the refresh operation mode M (I) for (1) is generated.
Refresh address Add propagated in this case
(I) is address information for the next refresh operation, which is propagated to the holding units 11 and 12 for holding in advance. Since the address information to be refreshed is fetched from the holding units 11 and 12 that are held in advance, even if the refresh address bus Add (I) is switched to when the refresh operation mode M (I) occurs, the address information Does not affect the response speed of the refresh operation.

FIG. 3 shows the operation of the first embodiment.
The operation waveforms when the refresh operation mode M (I) continues are shown. When the refresh timing signal REQ (I) is output from the refresh timing timer 56, the refresh address counter 53 increments the refresh address Add (I) from (0000) to (0001). Here, the address transition is shown with a time spread, indicating that the count-up operation in the counter 53 sequentially progresses bit by bit. If a synchronous counter is used, the time width of address transition can be reduced.

Output refresh request signal REQ
(I) propagates to the mode determination unit 62 as the refresh operation mode signal M (I) via the access arbiter 60, and the high-level control signal SW is output. Here, the control signal SW is maintained at the high level during the operation period of the refresh operation, and the holding address bus LAdd and the holding redundancy judgment result bus LJ are continuously connected to the access target address bus MAdd and the access target redundancy judgment result bus MJ. The case is shown. Holding address bus LA
The refresh address (0000) held in each of the holding units 11 and 12 in the previous refresh operation mode, and the mismatch determination redundancy result (Judge = 0) are output to the dd and the retention redundancy determination result bus LJ. Therefore, in response to the high-level transition of the control signal SW, the address (0000) and the mismatch determination (Judge = 0) are output to the access target address bus MAdd and the access target redundancy determination result bus MJ. The memory cell at the address (0000) is selected by these address information.

During this period, the logical level of the control signal LCH is maintained at the low level, so the address switching unit 1
With the switch unit SW1 of 0, the internal address bus IAd
d is connected to the data access address bus Add (O). The internal address bus IAdd is set to indefinite address information output via the row address buffer 52. An indetermination determination result for this indeterminate address information is set in the redundancy determination result bus RJ.

The control signal LCH outputs a high level pulse for a predetermined time in response to the transition of the control signal SW to the low level after the operation period of the refresh operation is completed and the precharge period is entered. During this period, the switch SW2 of the address switching unit 10 causes the internal address bus I
Add is connected to the refresh address bus Add (I). On the internal address bus IAdd, the refresh address (0001) which has been counted up at the time of outputting the refresh request signal REQ (I) is set,
On the redundancy judgment result bus RJ, a match judgment is made as a redundancy judgment result RJ (I) of the address (0001) (Judge = 1).
Is output. Further, the switch section SW3 of each of the holding sections 11 and 12 is also turned on by the high-level control signal LCH, so that the address (0001) and the match determination (Judge) are performed.
= 1) is stored.

With the end of the high level pulse period of the control signal LCH, the switch unit SW of the address switching unit 10
1, the internal address bus IAdd is again connected to the data access address bus Add (O), and undefined information is set in the internal address bus IAdd and the redundancy judgment result bus RJ. However, since the switch unit SW3 of each of the holding units 11 and 12 is non-conductive, the indefinite information is not stored, and the address (0001) that is the target of the next refresh operation and the redundancy determination result (Judge).
= 1) is held.

Subsequent refresh request signal REQ
The same operation is repeated for (I). In the circuit operation of FIG. 3, the refresh address counter 53 is counted up according to the refresh request signal REQ (I), the address information to be the target of the next refresh operation is set, and after the operation period of the refresh operation ends. During the precharge period, the address information set by the refresh address counter 53 is stored in the internal address holding unit 11, and the redundancy judgment result RJ (I) performed by the redundancy judgment unit 15 is stored in the internal address redundancy judgment result holding unit. Store in 12.

FIG. 4 shows a breakdown of the refresh operation time tRF1 in one operation cycle in the first embodiment in comparison with the refresh operation time tRF of the prior art. In the prior art, the refresh address count-up operation and the redundancy determination operation for the refresh address are performed in parallel with the refresh operation preceding the target refresh operation. These preceding operations are embedded in the operation period of the refresh address switching operation, the refresh address decoding operation, and the memory cell refresh execution operation in the refresh operation period.

In the first embodiment, in addition to the prior operation in the prior art, the refresh address switching operation can be performed in parallel with the refresh operation preceding the target refresh operation. As a result, the time Δt1 required for the address switching operation
The time can be shortened. The refresh operation time tRF1 is tRF1 = tRF−Δt1.

The switching operation to the refresh address means switching the connection to the internal address bus IAdd from the data access address bus Add (O) to the refresh address bus Add (I).
The load capacity of the internal address bus IAdd may be large, and the switching time Δt until the refresh address Add (I) is set in the internal address bus IAdd.
1 may require a great deal of time. As the load capacitance of the internal address bus IAdd, the parasitic capacitance due to the bus wiring, the holding units 11 and 12, the switching units 13 and 14,
And the input capacity of the redundancy judgment unit 15 and the like. Of these, the redundancy determination unit 15 needs to be provided according to the redundant configuration, and needs to be provided for each redundant address that enables replacement to the redundant configuration. In the case of having a large number of redundant configurations, it is necessary to provide a large number of redundancy determining units 15, which increases the load capacity of the internal address bus IAdd.

FIG. 5 shows a modification of the first embodiment.
The word line drive system circuit 64 and the memory cell array 66 are divided into banks A to D, and activation control is performed for each of the banks A to D by bank control signals BK0 to BK3. Switching unit A (13A to 13D) and switching unit J (14A
14D) are provided for each of banks A to D, and bank control signals BK0 to BK are provided by NAND gates 16 to 19.
An AND operation is performed with the control signal SW for each K3, and activation is performed for each of the banks A to D to switch the selection destination. The activation control may be performed only for the bank that requires the refresh operation, and the current consumption can be reduced.

FIG. 6 shows an example of layout layout when the semiconductor memory device of the first embodiment is divided into four memory banks A to D. In the semiconductor memory device of FIG.
The address terminals 50 and the row address buffers 52 are arranged in the entire chip in the vicinity of the center of the short side of the chip along the direction of the long side of the chip due to restrictions on the interface with the outside during mounting. In accordance with this arrangement, the refresh address counters 53 are also distributed. The address switching units 10 are also arranged in a distributed manner between the row address buffer 52 and the refresh address counter 53.

In the arrangement of FIG. 6, each holding portion 11, 1
2 or each of the switching units 13 and 14 is arranged at any position in the chip long side direction where the address switching units 10 are distributed. The length in the long side direction of the chip is large, and the parasitic resistance RLD and the parasitic capacitance CLD are large in the case of long-distance wiring. Further, the predecoder PD to which the address information is input is composed of a multi-input logic gate corresponding to the address bit width, and has a large input capacitance. Therefore, it is necessary to devise a circuit arrangement so that the signal propagation delay is not increased by these loads and the high-speed response is not limited.

Therefore, in FIG. 6, by arranging the holding units 11 and 12 and the switching units 13 and 14 on the side of the predecoder PD, the address switching unit 10 to the holding units 1 are arranged.
1, 12 and the switching units 13 and 14 are arranged so that the holding units 11 and 12 and the switching units 13 and 14 and the predecoder PD are connected to each other with a wiring distance shorter than the wiring distance to the switching units 13 and 14. There is. Thereby, the holding units 11 and 12
Also, the wiring load between each switching unit 13 and 14 and the predecoder PD is reduced to reduce the propagation delay time of address information. At this time, the wiring load may be arranged between the address switching unit 10 and each of the holding units 11 and 12, but the storage operation of the address information in each of the holding units 11 and 12 should be performed sufficiently in advance. If this is done, the refresh operation time will not increase. It is possible to shorten the time until the address information is fixed and further shorten the operation time.

As described in detail above, according to the semiconductor memory device and the control method thereof according to the first embodiment,
The refresh address Add (I), which is the second address sequentially designated by the refresh address counter 53 according to a predetermined order, is targeted for access prior to the next refresh operation mode, which is the second operation mode. Refresh address Add
Since (I) can be determined, the refresh address Add in the next refresh operation mode is previously set.
(I) and the redundancy determination result RJ (I) obtained by performing the redundancy determination on this address Add (I) can be held. It is not necessary to perform the refresh address Add (I) determination operation, the refresh address Add (I) redundancy determination operation, and the redundancy determination operation determination operation at the start of the refresh operation mode. Therefore, the operation period of the refresh operation mode can be shortened.

Further, in the operation specification in which the data access operation mode and the refresh operation mode which are the first operation modes are a pair of access operations, the cycle time can be shortened. When the refresh operation mode is prioritized, the access time of the data access operation mode can be shortened. Further, when the refresh operation mode is performed between a plurality of data access operation modes as needed, the occupation rate of the data access operation mode can be improved.

Further, since the storage in the internal address holding unit 11 and the internal address redundancy judgment result holding unit 12 is performed by one-time storage operation by the high level pulse signal which is one shot drive of the control signal LCH, the voltage fluctuation. It is unlikely to be adversely affected by the above. If one-shot driving is performed at a timing when the voltage change is small such as in the precharge period after the end of the refresh operation period, the possibility of being adversely affected by the voltage change is further reduced, and the storage operation can be surely performed. .

Further, the word line drive system circuit 64 and the memory cell array 66 are divided into banks A to D, and the switching section A (13A to 13D) and the switching section J are divided for each bank.
(14A to 14D), and bank control signals BK0 to BK0
If activation control is performed by BK3, it is possible to operate only for the bank that requires the refresh operation,
It is possible to reduce current consumption.

If the holding units 11 and 12 and the switching units 13 and 14 are arranged on the side of the predecode PD and the wiring distance between them is shortened, the wiring load is reduced and the address information It is possible to reduce the propagation delay time. It is possible to shorten the time until the address information is fixed and further shorten the operation time.

In the first specific example of the second embodiment shown in FIG. 7, instead of the predecoder PD included in the word line drive system circuit 64 in the first embodiment (FIG. 1), the address switching section 10 is used. The predecoder 20 is provided at the subsequent stage. The internal pre-decode address bus IAD connected to the output of the pre-decoder 20 is
And the holding units 11 and 12, and the switching units 13 and 14, respectively.

Further, in the second specific example of the second embodiment shown in FIG. 8, in place of the predecoder PD of the first embodiment (FIG. 1), data is provided at the subsequent stage of the row address buffer 52 and the refresh address counter 53. Access address Add (O) and refresh address Add (I)
Dedicated first and second predecoders 23, 24 for
Is equipped with. First and second predecoders 23, 24
External and internal predecode address A output from
D (O) and AD (I) are selected by the address switching unit 10.

FIG. 9 shows the breakdown of the refresh operation time tRF2 in one operation cycle in the second embodiment, which is the refresh operation time tRF in the prior art and the first embodiment.
And in comparison with tRF1. In the second embodiment, in addition to the preceding operation in the first embodiment, the refresh address predecoding operation can be performed in parallel with the refresh operation preceding the target refresh operation. As a result, the time Δt2 required for the predecoding operation can be further shortened. The refresh operation time tRF2 is tRF
2 = tRF−Δt1−Δt2.

FIG. 10 shows an example layout layout of the semiconductor memory device of the first specific example of the second embodiment when it is divided into four memory banks A to D as in the case shown in FIG. The main decoder MD of the word line drive system circuit 64 is provided in each of the banks A to D in proximity to the memory cell array.
0-3 and word line drivers WD0-3 are arranged. Since the row address buffer 52, the refresh address counter 53, and the address switching unit 10 are arranged on the entire chip in the vicinity of the center of the short side of the chip along the long side direction of the chip, in the case of long-distance wiring, the parasitic resistance RLD Therefore, the parasitic capacitance CLD becomes large. Further, the main decoders MD0 to MD3 to which the address information from the predecoder 20 is input are composed of multi-input logic gates corresponding to the address bit width, and have a large input capacitance. Therefore, it is necessary to devise a circuit arrangement so that the signal propagation delay is not increased by these loads and the high-speed response is not limited.

Therefore, in FIG. 10, the address switching unit 1
The predecoder 20 arranged at the rear stage of
1 and 12 and the respective switching units 13 and 14 are arranged so that the address switching unit 10 is connected to the predecoder 2
The wiring distance is set to be shorter than the wiring distance up to 0. This reduces the wiring load between the predecoder 20 and the holding units 11 and 12 and the switching units 13 and 14 to reduce the propagation delay time of address information. At this time, the wiring load may be arranged between the address switching unit 10 and the predecoder 20, but the storage operation of the address information in each of the holding units 11 and 12 is sufficiently performed to refresh the wiring. There is no increase in operating time. It is possible to shorten the time until the address information is fixed and further shorten the operation time.

Although FIG. 10 illustrates the first specific example of the second embodiment, the second specific example is also illustrated in FIG.
The first and second predecoders 23 and 24 and the address switching unit 10 are arranged at the positions where the predecoders 20 are arranged to shorten the wiring distance between the predecoders 23 and 24 and the address switching unit 10. Needless to say, the same effect can be obtained.

As described in detail above, according to the semiconductor memory device and the control method thereof according to the second embodiment,
Prior to the refresh operation mode that is the second operation mode, the refresh address Ad that is the second address is previously set.
Since the pre-decoding process of d (I) can also be performed, the operation period of the refresh operation mode can be further shortened.

Further, the predecoder 20 and each holding unit 11,
12 and the wiring distance between the switching units 13 and 14,
Alternatively, the predecoders 23 and 24 and the address switching unit 1
By shortening the wiring distance from 0 and reducing the wiring load,
It is possible to reduce the propagation delay time of address information. The operating time can be further shortened.

In the third embodiment shown in FIG. 11, a mode holding unit with history holding function 30 is provided instead of the mode judging unit 62 in the first embodiment (FIG. 1). A control signal LCH (O),
LCH (I) and SW are output, and the data access address bus A in the address switching unit 10 is output.
dd (O) selection, refresh address bus Add
The configuration is such that (I) is selected and the switching units 13 and 14 are selected.

A data access operation mode signal M (O) and a refresh operation mode signal M (I) are input to the mode determining unit 30 with a history holding function. These operation mode signals M are adjusted by the access arbiter 60.
Control signal L only when (O) and M (I) are switched.
At least one of CH (O), LCH (I), and control signal SW may be controlled to switch the bus selection state of the address switching unit 10 or the switching units 13 and 14. it can. The switched selected state is maintained until the operating mode signals M (O) and M (I) are further switched. This control is controlled by the control signal LC
If applied to H (I), the address switching unit 10
Thus, when the refresh address bus Add (I) is in the selected state, each of the time keeping units 11 and 12 continues to maintain the address information storable state. This state continues until the control signal LCH (O) is output, and the address information stored at the time of outputting the control signal LCH (O) is held until the next refresh operation mode.

Further, control signals LCH (O), LCH
The control of at least one of (I) and the control signal SW may be configured to output a pulse for each of the operation mode signals M (O) and M (I). In this case, the address switching unit 10 or each switching unit 1
The configuration is such that the buses 3 and 14 are selected by pulse driving. If the address information fetched by pulse driving is held by a latch circuit or the like, the necessary address information can be fetched accurately for each operation mode signal M (O), M (I).

FIG. 12 shows a specific example of the circuit configuration of the subsequent stage from the address switching unit 10 of the third embodiment. The address switching unit 10 includes a switching circuit 102 instead of the switching circuit 101 in the specific example of the first embodiment (FIG. 2). Each switching circuit 102
A switch unit SW4 for switching between each address bit information of the data access address Add (O) and each address bit information of the refresh address Add (I),
SW5 is provided, and each switch unit SW4, SW5 is
It is controlled by control signals LCH (O) and LCH (I). Data access address Add (O) and refresh address A fetched through the switch units SW4 and SW5
dd (I) is latched by a latch unit configured by connecting the input and output terminals of the inverter gates I1 and I2 to each other. The address bit information latched in the latch section is
Internal address bus IAd via inverter gate I3
It is output to d.

Each switch unit S of the internal address holding unit 11
W3 and each switch section SW3 of the internal address redundancy judgment result holding section 12 are controlled by the control signal LCH (I). The address information is stored in synchronization with the selection of the refresh address Add (I) in the address switching unit 10.

FIG. 13 shows operation waveforms of the control signals LCH (O), LCH (I) and SW for the operation mode signals M (O) and M (I) in the operation of the third embodiment. In FIG. 13, the operation mode signals M (O) and M (I)
Is input as a high-level pulse signal.

When the pulse signal of the refresh operation mode signal M (I) is input, the control signal SW transits to the high level, and the switch units SW2 of the switching units 13 and 14 are switched.
Is made conductive. The refresh address Add (I) and the redundancy judgment result RJ that are held are stored in the holding address bus LAdd and the holding redundancy judgment result bus LJ.
(I) is taken into the word line drive system circuit 64. At the same time, the refresh operation activation signal RFACT shifts to a high level by a control circuit (not shown) to start the refresh operation. Refresh operation activation signal RFACT
Goes to the low level and the refresh operation is completed, the control signal LCH (I) is output as a pulse, the switch sections SW2 of the address switching section 10 become conductive, and the refresh address Add for the next refresh operation is added.
(I) is taken into each latch section of the address switching section 10 and each switch section SW of each time keeping section 11 and 12
3 is conducted and stored in each of the holding units 11 and 12.

In the next operation mode, the pulse signal of the data access operation mode signal M (O) is input. The control signal SW changes to the low level, and the switching units 13 and 14
Each switch section SW1 is turned on. At the same time, the control signal LCH (O) is output as a pulse and the address switching unit 1
Each switch unit SW4 of 0 is turned on, and the data access address Add (O) is taken into each latch unit of the address switching unit 10. Data access address Add
(O), the redundancy judgment result RJ (O) is taken into the word line drive system circuit 64 via the internal address bus IAdd and the redundancy judgment result bus RJ.

Next, it is a case where the refresh operation is continuously performed. Refresh operation mode signal M (I)
Pulse signals are continuously output. As a result, the control signal SW maintains the high level and the holding address bus LA
dd, holding redundancy judgment result bus LJ is continuously selected. This state continues until the data access operation mode signal M (O) is input and the control signal SW is transited to the low level. The control signal LCH (I) is the operation mode signal M
A pulse is output every (I). This is because the refresh address Add (I) is updated for each refresh operation and stored in each of the holding units 11 and 12.

14 and 15 are operation waveforms in the case where the refresh operation mode is continuous in the operation of the third embodiment. FIG. 14 shows a case where the address switching unit 10 and the holding units 11 and 12 are controlled by the control signal LCH (I) in the refresh operation. Figure 15 shows
In the refresh operation mode, the control of the address switching unit 10 is performed by the control signal LCH (I) 1 and the control of each of the holding units 11 and 12 is performed by the control signal LCH (I) 2.

In the operation waveform of FIG. 14, since the control signal SW is maintained at the high level in the state where the refresh operation mode continues, even in the precharge period after the end of the operation period of each refresh operation mode. , Unnecessary address information is not propagated to the access target address bus MAdd and the access target redundancy judgment result bus MJ. In addition, the control signal LCH (I)
Is pulse-driven at the end of the operation period of each refresh operation, and the refresh address Add (I) is latched in the latch unit of the address switching unit 10. Therefore, unnecessary address information is stored in the internal address bus IAdd during the precharge period. It is not propagated and each holding unit 11,
The operation of storing the address information in 12 is also performed by the 1-pulse operation.

In the operation waveform of FIG. 15, in the state where the refresh operation mode continues, the control signal SW is
As in the case of FIG. 14, it is maintained at the high level, and the access target address bus MA is also maintained in the precharge period after the end of the operation period of each refresh operation mode.
Unnecessary address information is not propagated to dd and the access target redundancy judgment result bus MJ. Further, the control signal LCH (I) 1 is pulse-driven during the operation period of each refresh operation, the refresh address Add (I) is latched in the latch unit of the address switching unit 10, and the refresh signal Add (I) is internally supplied in the subsequent precharge period or the like. Address bus IAdd
Unnecessary address information is not propagated to. Furthermore,
The control signal LCH (I) 2 is the control signal LCH of FIG.
As in (I), pulse driving is performed at the end of the operation period of each refresh operation, the operation of storing address information in each of the holding units 11 and 12 is performed, and unnecessary address information is stored in the subsequent precharge period or the like. It will not be done.

As described in detail above, according to the semiconductor memory device and the control method thereof according to the third embodiment,
During the precharge period, the address setting is not fixed and the unnecessary address is not input and the redundancy judgment operation is not performed for the address, and the unnecessary current consumption due to the unnecessary circuit operation can be suppressed. It is possible to effectively reduce the current consumption when the number of address bits and the redundant configuration increase as the capacity increases.

Since the storage operation of the address information in each of the holding sections 11 and 12 is also performed by the one-pulse operation, the storage operation is performed at an appropriate timing with a small voltage fluctuation and the like, so that the incorrect address information is stored. Can be prevented.

Here, the control signals LCH (O), LCH
The switching timing of (I), LCH (I) 1, LCH (I) 2 or the timing of pulse output is as follows: data access address bus Add (O), refresh address bus Add (I), internal address bus IAdd and redundancy. It is preferable that the timing is after the determination of the address information on the determination result bus RJ. Further, the switching timing of the control signal SW or the pulse output timing is the timing after the address information on the internal address bus IAdd and the redundancy judgment result bus RJ is determined, or the refresh address Add (to the holding units 11 and 12). I), redundancy judgment result RJ (I)
It is preferable that the timing is after the completion of storing the data. As a result, undefined address information before the address information is fixed or stored is not propagated.

The fourth embodiment shown in FIG. 16 includes a thinning decision circuit 40, a flip-flop circuit 42, and a thinning control circuit 44 in addition to the first embodiment (FIG. 1).
The refresh address Add is added to the thinning decision circuit 40.
(I) is input, and it is determined whether or not the refresh operation can be executed according to the data retention characteristic of the memory cell that is measured in advance. It is not necessary to perform the refresh operation every time for the memory cell having a good data retention characteristic, but it is sufficient to perform the refresh operation once for each predetermined number of refresh requests. The thinning-out determination circuit 40 is a circuit for determining whether or not execution is possible for this purpose.

The first determination result signal TO1 is input to the thinning-out control circuit 44 and at the same time the flip-flop circuit 42.
Is input to the input terminal D of. Flip-flop circuit 42
Is a D-type flip-flop, which takes in the first determination result signal TO1 by using the refresh request signal REQ (I) as a trigger and outputs it as the second determination result signal TO2 to the thinning control circuit 44. Refresh operation request signal REQ
For the output of (I), the refresh address Add
Since (I) outputs the refresh address Add (I) for the next refresh operation, the second determination result signal TO2 is the determination for the address Add (I) for the current refresh operation mode, and the first determination result signal TO1 is the next The address Add (I) is determined for the refresh operation mode.

The thinning-out control circuit 44, in addition to the first and second determination result signals TO1 and TO2, includes a mode determining section 62.
The control signals LCH1 and SW1 from are input. The control signals LCH1 and SW1 are the first and second determination result signals TO
1 and TO2, and output as control signals LCH2 and SW2. Address switching unit 10 and each holding unit 1
1, 12 and the switching units 13 and 14 are controlled.

FIG. 17 is a concrete example of the thinning control circuit 44. The first determination result signal TO1 is the inverter gate I9.
And the output of the inverter gate I9 is input to the control signal L.
It is input to the NAND gate NA1 together with CH1. The output of the NAND gate NA1 is inverted by the inverter gate I10 and output as the control signal LCH2. The second determination result signal TO2 is input to the inverter gate I11,
The output of the inverter gate I11 is input to the NAND gate NA2 together with the control signal SW1. Nand Gate NA2
Is inverted by the inverter gate I12 and output as the control signal SW2.

FIG. 18 shows operation waveforms when the refresh operation mode is continuous in the fourth embodiment. The refresh address counter 53 is incremented in accordance with the refresh request signal REQ (I),
The refresh addresses (# 100) to (# 102) are output. At the same time, the mode determination unit 62 outputs the control signal LC
H1 and SW1 are output. Control signal LCH in this case
1 and SW1 are signals similar to the control signals LCH and SW of the first embodiment. In the fourth embodiment, the control signal LCH
1 and SW1 are controlled by the thinning control circuit 44.

In the first refresh operation mode, the refresh address (# 100) is not the thinning target, so both the first and second determination result signals TO1 and TO2 are at the low level. From FIG. 17, NAND gate NA1,
Since NA2 functions as a logic inverting gate, the control signals LCH2 and SW2 are output as signals in phase with the control signals LCH1 and SW1, and a normal refresh operation and an operation of storing address information regarding the refresh address (# 100) are performed. Be done.

In cycle A which is the next refresh operation mode, it is determined that the refresh address (# 101) is the thinning address. First determination result signal TO1
Shifts to the high level, and the output of the NAND gate NA1 in FIG. 17 is fixed to the high level. Therefore, the control signal LCH
2 is fixed to the low level, and the operation of fetching the refresh address (# 101) by the address switching unit and the operation of storing it in the holding units 11 and 12 are not performed.
That is, the address information regarding the refresh address (# 100) is maintained in each of the holding units 11 and 12. At this time, since the second determination result signal TO2 is maintained at the low level, the refresh address (# 100) is read from each of the switching units 13 and 14, and the refresh operation is performed.

In cycle B which is the next refresh operation mode, it is determined that the refresh address (# 102) is not the thinning address. Although the first determination result signal TO1 transits to the low level, the second determination result signal T1
O2 transits to high level. Therefore, the output of the NAND gate NA2 in FIG. 17 is fixed to the high level. Therefore, the control signal SW2 is fixed to the low level, the address information is not read from the switching units 13 and 14, and the refresh operation is not performed. At this time, since the first determination result signal TO1 is maintained at the low level, the refresh address (# 10
The capturing operation of 2) and the storing operation in the holding units 11 and 12 are performed.

As described in detail above, according to the semiconductor memory device and the control method thereof according to the fourth embodiment,
Since the refresh operation mode that is the second operation mode is not performed on the refresh address Add (I) that is the second address that has been determined not to be executed, the refresh address Ad that precedes the refresh operation mode is not performed.
Storing d (I) in the internal address holding unit 11, redundancy judgment by the redundancy judgment unit 15, and refresh address A
The operation of storing the redundancy judgment result for dd (I) in the internal address redundancy judgment result holding unit 12 is prohibited, and the switching unit A (13) and the switching unit J (14) that are the first and second switching units are also selected. It can be prohibited, and current consumption due to unnecessary circuit operation can be reduced. It is possible to effectively reduce the current consumption when the number of address bits and the redundant configuration increase as the capacity increases.

Needless to say, the present invention is not limited to the above embodiment, and various improvements and modifications can be made without departing from the spirit of the present invention. For example, it is needless to say that the control for each bank shown in the first embodiment and the layout arrangement examples shown in the first and second embodiments can be similarly applied to other embodiments.

(Supplementary Note 1) A first operation mode in which a first address to be accessed is designated for each access to perform an access operation, and the first operation mode are executed asynchronously, and in accordance with a predetermined order. In a semiconductor memory device having a second operation mode in which a second address to be accessed is designated for each access and an access operation is performed, the semiconductor memory device is connected to an internal address bus and is controlled by a control signal prior to the next second operation mode. Next time the second
An address holding unit for storing the second address in the operation mode and a redundancy judgment result bus are connected, and the second next time is controlled by a control signal preceding the second operation mode next time.
A redundancy judgment result holding section for storing the redundancy judgment result of the second address in the operation mode, and a first switching for selecting the internal address bus or the address holding section at the time of access in the first or second operation mode. And a second switching unit for selecting the redundancy judgment result bus or the redundancy judgment result holding unit. (Supplementary Note 2) In Supplementary Note 1, in the second operation mode, after the selection of the first and second switching units, the storage operation in the address holding unit and the redundancy judgment result holding unit is performed. The semiconductor memory device described. (Supplementary Note 3) The semiconductor memory device according to Supplementary Note 1, wherein the first operation mode is a data input / output operation, and the first address is an external address input from the outside. (Supplementary Note 4) The semiconductor memory device according to Supplementary Note 1, wherein the second operation mode is a refresh operation, and the second address is an internal address generated internally. (Supplementary Note 5) At least one of the address holding unit and the redundancy judgment result holding unit is arranged such that the output signal path is shorter than the input signal path when the circuit is arranged. The semiconductor memory device according to attachment 1. (Supplementary Note 6) At least one of the first switching unit and the second switching unit is arranged such that an output signal path is shorter than an input signal path in circuit arrangement. The semiconductor memory device according to attachment 1. (Supplementary Note 7) A predecode unit for predecoding at least one of the first address and the second address is provided, and the predecoded address and the predecode are provided on the internal address bus and the redundancy determination result bus. 2. The semiconductor memory device according to appendix 1, wherein a redundancy determination result for the generated address is output. (Supplementary Note 8) The semiconductor memory device according to Supplementary Note 7, wherein the predecoding unit is arranged such that the output signal path is shorter than the input signal path when the circuit is arranged. (Supplementary Note 9) The memory cell region is divided into a plurality of banks, and at least one of the first switching unit and the second switching unit is provided for each bank and is provided in the activated bank. 2. The semiconductor memory device according to appendix 1, wherein the semiconductor memory device is activated accordingly. (Supplementary Note 10) The operation period of the first or second operation mode and the non-operation period from the end of the operation period to the start of the next operation period are defined as one unit, and the first cycle Alternatively, a semiconductor memory device in which a second operation mode is set is provided with an address switching unit that establishes an address path for outputting the first or second address to the internal address bus, and the address switching unit is 2. The semiconductor memory device according to appendix 1, wherein when the operation mode is switched between the first and second operation modes, the address path is switched only at the first switching timing after the start of the operation cycle. (Supplementary Note 11) The first switching timing is a timing after the first address input to the address switching unit is fixed when switching to the first operation mode, and the first operation timing is set to the second operation mode. 11. The semiconductor memory device according to appendix 10, wherein the timing is after the selection of the address holding unit and the redundancy judgment result holding unit by the first and second switching units when switching. (Supplementary Note 12) For each operation cycle configured with an operation period of the first or second operation mode and a non-operation period from the end of the operation period to the start of the next operation period as one unit, the first Alternatively, a semiconductor memory device in which the second operation mode is set is provided with an address switching unit that fetches and latches the first or second address and outputs the latched address to the internal address bus. 2. The semiconductor memory device according to appendix 1, wherein the first or second address is fetched and latched only at the first fetch timing after the start of the operation cycle. (Supplementary Note 13) The first fetch timing is a timing after the first address input to the address switching unit is fixed when the first address is fetched, and the second address fetch is performed. When the first
13. The semiconductor memory device according to appendix 12, wherein the timing is after the selection of the address holding unit and the redundancy judgment result holding unit by the second switching unit. (Supplementary Note 14) For each operation cycle configured with an operation period of the first or second operation mode and a non-operation period from the end of the operation period to the start of the next operation period as one unit, the first Alternatively, in the semiconductor memory device in which the second operation mode is set, the first and second switching units are provided after the operation cycle is started when the operation mode is switched between the first and second operation modes. 2. The semiconductor memory device according to appendix 1, wherein selection of the internal address bus or the address holding unit and the redundancy judgment result bus or the redundancy judgment result holding unit is switched only at a second switching timing. (Supplementary Note 15) The second switching timing is the first address and the redundancy determination result of the first address in the internal address bus and the redundancy determination result bus when switching to the first operation mode. 15. The semiconductor memory device according to appendix 14, characterized in that the timing is after determination, and is the timing after the start of the operation cycle when switching to the second operation mode. (Supplementary Note 16) The operation period of the first or second operation mode and the non-operation period from the end of the operation period to the start of the next operation period are set as one unit, and the first cycle Alternatively, in the semiconductor memory device in which the second operation mode is set, the first and second switching units include the internal address bus or the address holding unit, and the redundancy judgment result bus or the redundancy judgment result holding unit. First and second latch units for capturing and latching the output from the internal address bus or the address holding unit, and the redundancy judgment result bus or the only at the second capture timing after the start of the operation cycle. 2. The semiconductor memory device according to appendix 1, wherein the redundancy judgment result holding unit is selected. (Supplementary Note 17) The second fetch timing is the first address and the first address when fetching the first address and the redundancy judgment result of the first address in the internal address bus and the redundancy judgment result bus. It is the timing after the determination of the redundancy judgment result of the first address, and the operation is performed when the second address and the redundancy judgment result of the second address are fetched in the address holding unit and the redundancy judgment result holding unit. 17. The semiconductor memory device according to appendix 16, wherein the timing is after the start of the cycle. (Supplementary Note 18) An execution permission / inhibition determination unit that determines whether or not to execute the second operation mode is provided for each of the second addresses, and the second execution determination unit determines that the second execution mode has not been performed.
Regarding the address, the supply of the second address to the internal address bus is prohibited, the control signal is deactivated, and in the non-execution second operation mode, the first and second switching units 2. The semiconductor memory device according to appendix 1, wherein selection is prohibited. (Supplementary Note 19) A semiconductor memory device in which an external access operation mode performed based on an external access request from the outside and an internal access operation mode performed based on an internal access request automatically generated internally are executed asynchronously with each other. In the above, the adjustment unit for adjusting the external access request and the internal access request, and outputting an external operation mode signal or an internal operation mode signal according to the external or internal access operation mode, and the external or internal operation mode A mode determination unit that outputs at least two control signals, a first control signal that is controlled in advance and a second control signal that is controlled after the control of the first control signal, according to the signal; An external address controlled by a control signal and set in the external access operation mode, and a predetermined location An address switching unit that selects any address of the internal addresses generated in the internal access operation mode according to a fixed order and outputs the address to the internal address bus, and a redundancy determination result for the any address on the internal address bus. To the redundancy determination result bus, an address holding unit connected to the internal address bus and storing the internal address by the second control signal, and a redundancy determination result bus connected to the redundancy determination result bus. 2 a redundancy judgment result holding section for storing the redundancy judgment result by a control signal, a first switching section for selecting the internal address bus or the address holding section by the first control signal, and a first control signal by the first control signal. A second switching unit for selecting the redundancy judgment result bus or the redundancy judgment result holding unit. The semiconductor memory device according to claim. (Supplementary Note 20) The internal address and the redundancy determination result of the internal address held in the address holding unit and the redundancy determination result holding unit are the access targets in the next internal access operation mode. The semiconductor memory device according to attachment 19. (Supplementary Note 21) The mode determination unit further includes a third control signal that is controlled before the storage timing of the address control unit and the redundancy determination result storage unit by the second control signal, and the second control signal. 20. The semiconductor memory device according to appendix 19, wherein the third control signal controls the address switching unit instead of the signal. (Supplementary Note 22) The semiconductor memory device according to Supplementary Note 19, further comprising a predecoding unit that is connected between the address switching unit and the internal address bus and predecodes any one of the addresses. (Supplementary Note 23) A first predecoding unit that predecodes the external address and a second predecoding unit that predecodes the internal address are provided, and the address switching unit is predecoded by the first predecoding unit. 20. The semiconductor memory device according to appendix 19, wherein either the external predecode address or the internal predecode address predecoded by the second predecode unit is selected. (Supplementary Note 24) The external or internal access operation mode is configured such that the operation period of the external or internal access operation mode and the non-operation period from the end of the operation period to the start of the next operation period are set as one unit, and the external or internal A semiconductor memory device in which an access operation mode is set, wherein the second control signal or the third control signal is set only after the start of the operation cycle in which the operation mode is switched between the external or internal access operation modes. 22. The semiconductor memory device according to appendix 19 or 21, wherein the semiconductor memory device is switched and an address path in the address switching unit is switched. (Supplementary Note 25) The external or internal access operation mode is configured in such a manner that the external or internal access operation mode and the non-operation period from the end of the operation period to the start of the next operation period are set as one unit. In a semiconductor memory device in which an access operation mode is set, the address switching unit includes a latch unit, and the second control signal or the third control signal is output only after the start of the operation cycle. 22. The semiconductor memory device according to appendix 19 or 21, wherein either the external address or the internal address is taken into the latch unit and latched. (Supplementary note 26) The external or internal access operation mode is configured such that the operation period of the external or internal access operation mode and the non-operation period from the end of the operation period to the start of the next operation period are set as one unit, and the external or internal operation is performed. In a semiconductor memory device in which an access operation mode is set, the first control signal is switched only after the start of the operation cycle in which the operation mode is switched between the external or internal access operation modes, and the internal address is changed. 20. The semiconductor memory device according to appendix 19, wherein selection of the bus or the address holding unit and the redundancy judgment result bus or the redundancy judgment result holding unit is switched. (Supplementary note 27) The external or internal access operation mode is configured such that the operation period of the external or internal access operation mode and the non-operation period from the end of the operation period to the start of the next operation period are set as one unit, and the external or internal In a semiconductor memory device in which an access operation mode is set, the first and second switching units are provided from the internal address bus or the address holding unit, and the redundancy judgment result bus or the redundancy judgment result holding unit. First and second latch units that take in and latch the output are provided, and the first control signal is output only after the start of the operation cycle, and the internal address bus or the address holding unit and the redundancy judgment result bus are provided. 20. The semiconductor memory device according to appendix 19, wherein the redundancy judgment result holding unit is selected. (Supplementary note 28) The internal address, comprising: an execution propriety judging unit for judging propriety of execution of the internal access operation mode for each of the internal addresses, wherein the execution propriety judging unit judges non-execution of the internal access operation mode. With regard to the above-mentioned item 19, the first and second control signals or the first to third control signals are inactivated.
22. The semiconductor memory device described in 21. (Supplementary note 29) First to be accessed for each access
A first operation mode in which an access operation is performed by designating an address and the first operation mode are executed asynchronously, and a second address to be accessed is designated and accessed for each access in accordance with a predetermined order. In a method of controlling a semiconductor memory device having a second operation mode in which an operation is performed, the first address and a redundancy determination result of the first address, or a pre-stored result, is stored as an access target in the first or second operation mode. The access target selecting step of selecting the second address and the redundancy determination result of the second address, and the access target in the second operation mode next time after the selection of the second operation mode in the access target selecting step. As
A method of controlling a semiconductor memory device, comprising: an operation target holding step of previously holding the second address and a redundancy determination result of the second address. (Supplementary note 30) The semiconductor memory according to supplementary note 29, wherein the operation target holding step and the access target selection step preceding the operation target holding step are performed in the same second operation mode. Device control method. (Supplementary Note 31) There is a pre-decoding step of pre-decoding the second address to be accessed in the second operation mode next time, and in the operation target holding step, the second address and the redundancy of the second address are included. 30. The semiconductor memory device control according to appendix 29, characterized in that a predecoded address of the second address and a redundancy decision result for the predecoded address obtained in the predecoding step are held in place of the decision result. Method. (Supplementary Note 32) The operation period of the first or second operation mode and the non-operation period from the end of the operation period to the start of the next operation period are set as one unit and the first cycle Alternatively, in a method of controlling a semiconductor memory device in which a second operation mode is set, the supply of the first address to the access target selecting step or the supply of the second address to the operation target holding step is switched. The address supply step is performed, and only after the start of the operation cycle in which the operation mode is switched between the first and second operation modes, the selection switching in the access target selection step or the supply in the address supply step is performed. Supplementary Note 29 characterized by performing at least one of the switching
A method for controlling a semiconductor memory device according to claim 1. (Supplementary Note 33) The second address, which has an execution propriety determination step for determining propriety of execution of the second operation mode for each second address, and which is determined not to be executed by the execution propriety determination step, 30. The method of controlling a semiconductor memory device according to appendix 29, wherein the access target selecting step and the operation target holding step are prohibited.

[0124]

According to the present invention, the storage of the address information in the holding unit is performed at a timing when the ambient noise is small.
It is possible to perform the pulse operation once, to prevent erroneous information storage due to the influence of noise, and to limit the switching operation of the address information to the necessary minimum, thereby achieving a low current consumption operation and a refresh operation. It is possible to provide a semiconductor memory device capable of shortening the cycle and speeding up data access and improving the data transfer rate, and a control method thereof.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of a first embodiment.

FIG. 2 is a circuit block diagram of a specific example of the first embodiment.

FIG. 3 is an operation waveform diagram of the first embodiment.

FIG. 4 is a schematic diagram showing the effect of shortening the refresh operation time according to the first embodiment.

FIG. 5 is a circuit block diagram showing a modified example of the first embodiment.

FIG. 6 is a schematic diagram showing an example layout layout of the first embodiment.

FIG. 7 is a circuit block diagram of a first specific example of the second embodiment.

FIG. 8 is a circuit block diagram of a second specific example of the second embodiment.

FIG. 9 is a schematic diagram showing the effect of shortening the refresh operation time according to the second embodiment.

FIG. 10 is a schematic diagram showing an example layout layout of the second embodiment.

FIG. 11 is a circuit block diagram of a third embodiment.

FIG. 12 is a circuit block diagram of a specific example of the third embodiment.

FIG. 13 is an operation waveform diagram showing switching of operation modes in the third embodiment.

FIG. 14 is an operation waveform diagram (1) in the case where the refresh operation mode continues in the third embodiment.

FIG. 15 is an operation waveform diagram (2) in the case where the refresh operation mode continues in the third embodiment.

FIG. 16 is a circuit block diagram of a fourth embodiment.

FIG. 17 is a circuit diagram showing a specific example of a thinning control circuit.

FIG. 18 is an operation waveform diagram of the fourth embodiment.

FIG. 19 is a circuit block diagram of a conventional technique.

FIG. 20 is an operation waveform diagram of a conventional technique.

[Explanation of symbols]

10 address switching unit 11 internal address holding unit 12 internal address redundancy determination result holding unit 13, 13A to 13D switching unit A 14, 14A to 14D switching unit J 15 redundancy determination unit 20, PD predecoder 23 first predecoder 24 second Predecoder 30 Mode determination unit with history retention function 50 Control terminal, address terminal 52 Row address buffer 53 Refresh address counter 54 I / O control unit 56 Refresh timing clock unit 60 Access arbiter 62 Mode determination unit 64 Word line drive system circuit 66 Memory Cell array IAdd Internal address bus IAD Internal predecode address bus LAdd Holding address bus LJ Holding redundancy determination result bus MAdd Access target address bus MJ Access target redundancy determination result bus Add (I) Refresh Address Add (O) data access address LCH, LCH (O), LCH (I), LCH (I)
1, LCH (I) 2, SW control signal M (I) refresh operation mode signal M (O) data access operation mode signal REQ (I) refresh request signal REQ (O) external access request signal RJ (I), RJ ( O) Redundancy judgment result

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Satoru Kawamoto             1844-2 Kozoji-cho, Kasugai-shi, Aichi             Within Fujitsu VIS Ltd. F-term (reference) 5L106 AA01 CC02 CC11 CC17 CC22                       FF02 GG03                 5M024 AA04 AA22 AA50 BB22 BB39                       DD62 DD72 DD83 DD95 DD99                       EE05 EE17 EE29 EE30 JJ02                       KK22 MM12 MM15 PP01 PP02                       PP07 PP10

Claims (10)

[Claims] 1. A first access target for each access
A first operation mode for performing an access operation by designating an address and the first operation mode are executed asynchronously, and a second address to be accessed is designated and accessed for each access according to a predetermined order. In a semiconductor memory device having a second operation mode for performing an operation, an address connected to an internal address bus and storing the second address in the second operation mode next time by a control signal preceding the second operation mode next time A holding unit, and a redundancy judgment result holding unit that is connected to the redundancy judgment result bus and stores a redundancy judgment result of the second address in the second operation mode next time by a control signal preceding the second operation mode next time; When accessing in the first or second operation mode, the internal address bus or the address holding unit is selected. A semiconductor memory device comprising: a first switching unit that selects the redundancy determination result bus; and a second switching unit that selects the redundancy determination result holding unit. 2. A predecoding unit for predecoding at least one of the first address and the second address, wherein the predecoded address and the predecoded address are stored in the internal address bus and the redundancy judgment result bus. 2. The semiconductor memory device according to claim 1, wherein a redundancy determination result for the decoded address is output. 3. The operation cycle in which the operation period of the first or second operation mode and the non-operation period from the end of the operation period to the start of the next operation period are set as one unit A semiconductor memory device in which the first or second operation mode is set, comprising an address switching unit that establishes an address path for outputting the first or second address to the internal address bus, wherein the address switching unit includes: When the operation mode is switched between the first and second operation modes, only at the first switching timing after the start of the operation cycle,
2. The semiconductor memory device according to claim 1, wherein the address path is switched. 4. The operation cycle in which the operation period of the first or second operation mode and a non-operation period from the end of the operation period to the start of the next operation period are set as one unit A semiconductor memory device in which the first or second operation mode is set, comprising: an address switching unit that fetches and latches the first or second address and outputs the latched address to the internal address bus. 2. The semiconductor memory device according to claim 1, wherein the first or second address is fetched and latched only at a first fetch timing after the start of the operation cycle. 5. The operation cycle in which the operation period of the first or second operation mode and the non-operation period from the end of the operation period to the start of the next operation period are set as one unit A semiconductor memory device in which the first or second operation mode is set, wherein the first and second switching units include the first or second
When the operation mode is switched between the operation modes, the internal address bus or the address holding unit and the redundancy judgment result bus or the redundancy judgment result holding unit are selected only at the second switching timing after the start of the operation cycle. The semiconductor memory device according to claim 1, wherein switching is performed. 6. The operation cycle in which the operation period of the first or second operation mode and a non-operation period from the end of the operation period to the start of the next operation period are set as one unit A semiconductor memory device in which the first or second operation mode is set, wherein the first and second switching units include the internal address bus or the address holding unit, and the redundancy determination result bus or the redundancy determination result holding. A first latch unit and a second latch unit for latching and latching the output from the internal address bus or the address holding unit, and the redundancy judgment result bus only at the second latch timing after the start of the operation cycle. The semiconductor memory device according to claim 1, wherein the redundancy judgment result holding unit is selected. 7. An executability determination unit that determines whether or not the second operation mode can be executed for each of the second addresses, and the second address that has been determined not to be executed by the executability determination unit, The supply of the second address to the internal address bus is prohibited, the control signal is deactivated, and the selection of the first and second switching units is prohibited during the non-execution of the second operation mode. The semiconductor memory device according to claim 1, wherein: 8. A first access target for each access
A first operation mode in which an access operation is performed by designating an address and the first operation mode are executed asynchronously, and a second address to be accessed is designated and accessed for each access in accordance with a predetermined order. In a method of controlling a semiconductor memory device having a second operation mode in which an operation is performed, the first address and a redundancy determination result of the first address, or a pre-stored result, are stored as an access target in the first or second operation mode. An access target selecting step of selecting the second address and a redundancy determination result of the second address, and an access target in the second operation mode next time after the selection of the second operation mode in the access target selecting step Is stored in advance as the second address and the redundancy judgment result of the second address. Control method of a semiconductor memory device characterized by having a target holding step. 9. The operation cycle in which the operation period of the first or second operation mode and a non-operation period from the end of the operation period to the start of the next operation period are set as one unit A method of controlling a semiconductor memory device, wherein the first or second operation mode is set, wherein the first address is supplied to the access target selecting step or the second address is supplied to the operation target holding step. Switching the address supply step, and switching the selection in the access target selection step or supply in the address supply step only after the start of the operation cycle in which the operation mode is switched between the first and second operation modes. 9. The semiconductor memory according to claim 8, wherein at least one of switching among the two is performed. Storage device control method. 10. An execution permission / inhibition determination step of determining whether or not the second operation mode can be performed for each of the second addresses, wherein the second address is determined to be non-executed in the execution permission / inhibition determination step. 9. The method of controlling a semiconductor memory device according to claim 8, wherein the access target selecting step and the operation target holding step are prohibited.