WO2007017692A1

WO2007017692A1 - Fuse memory bitcell and array thereof

Info

Publication number: WO2007017692A1
Application number: PCT/GB2006/002984
Authority: WO
Inventors: Theo BAND; Leon Van Gorsel; Hasan Gul; Marlon Facey
Original assignee: Cavendish Kinetics Ltd
Priority date: 2005-08-10
Filing date: 2006-08-09
Publication date: 2007-02-15
Also published as: GB0516423D0

Abstract

A one time-programmable memory bitcell (9) comprises a transistor (13) and a fuse (12). The transistor is arranged to receive a first signal and, upon receipt of the first signal, to enable communication of a second signal to the fuse. Preferably, the input terminal of the transistor is connected to the source of the first signal, the output terminal of the transistor is connected to one terminal of the fuse the other terminal of the fuse is connected to the source of the second signal. The present invention also provides a fuse memory array and associated control circuit.

Description

FUSE MEMORY BITCELL AND ARRAY THEREOF

The present invention relates to a one time programmable fuse memory bitcell and array thereof. There are currently a wide variety of known non-volatile memory devices such as EPROM's and FLASH memory devices that are used to assist in the functions of various semiconductor products.

Most One Time Programmable (OTP) memory devices are limited by the timing and voltage requirements associated with their writing operation and the power consumption requirements associated with their reading operation. Thus, there exists a clear need for a One Time Programmable memory bitcell and associated memory array which has reduced power consumption and faster write speeds.

According to the present invention there is provided a one time-programmable memory bitcell which comprises: a transistor and a fuse, wherein the transistor is arranged to receive a first signal and, upon receipt of the first signal, to enable communication of a second signal to the fuse.

Preferably, the fuse is a double-clamped cantilever micro fuse. Preferably, the input terminal of the transistor is connected to the source of the first signal; the output terminal of the transistor is connected to one terminal of the fuse; and the other terminal of the fuse is connected to the source of the second signal. The present invention also provides a one time-programmable memory module which comprises: an array of the abovementioned one time-programmable memory bitcells; a write circuit arranged to blow, during a write operation, a predetermined selection of the fuses in the array by supplying the first signal for a predetermined time period and the second signal having a first amplitude for a predetermined period of time; and a read circuit comprising detection means arranged to detect, during a read operation, whether or not a fuse is blown by supplying the first signal for a predetermined time period and the second signal having a second amplitude for a predetermined amount of time. Preferably, the detection means comprises a plurality of sense amplifiers, each sense amplifier comprising a differential amplifier, a reference voltage generator and a latch; wherein each sense amplifier is arranged to detect the voltage across each fuse relative to a voltage generated by the reference voltage generator and to store the detected voltage values in the latch.

Preferably, the reference voltage generator is arranged to generate two different reference voltages.

As will be apparent to the skilled reader, the present invention provides several advantages over the prior art. The speed with which the memory bitcell can be programmed is much higher than any prior art bitcell. Furthermore, the memory bitcell of the present invention requires less current during write and read operations than prior art bitcells and can be implemented using standard CMOS technology.

Examples of the present invention will now be described with reference to the accompanying drawings, in which:

Figure 1 shows a representation of the bit notation used by a bitcell array in accordance with one embodiment of the present invention; Figure 2 shows a top level block diagram of a fuse memory control circuit in accordance with one embodiment of the present invention;

Figure 3 shows a table of the input and output signal of the top level block diagram of Figure 2;

Figure 4 shows a table containing a description of the components of Figure 2; Figure 5 shows a schematic diagram of a single memory bitcell in accordance with one embodiment of the present invention;

Figure 6 shows a table of the pinout of the memory bitcell of Figure 5;

Figure 7 shows a memory bitcell block diagram of the memory bitcell of Figure 5; Figure 8 shows a schematic diagram of a memory array in accordance with one example of the present invention;

Figure 9 shows a table representing the pinout of the memory array of Figure 8;

Figure 10 shows a block diagram of the memory array of Figure 8; Figure 11 shows a distribution of fuse reference levels used in accordance with the present invention;

Figure 12 shows the reference word line in accordance with one embodiment of the present invention; ... Figure 13 shows a table of the relationship between the SERSEL[n] signals and the number of fuses connected in series;

Figure 14 shows a table of the reference bitline locations in accordance with the present invention;

Figure 15 shows the column buffer transistor configuration in accordance with one embodiment of the present invention;

Figure 16 shows a schematic diagram of the write mode of a memory array in accordance with one embodiment of the present invention;

Figure 17 shows a schematic diagram of the read mode in accordance with one embodiment of the present invention; Figure 18 shows the truth table of the column driver sub-block of Figure 5;

Figure 19 shows the equations relating to the column driver sub-block of Figure 5;

Figure 20 shows a schematic diagram of a column driver sub-block in accordance with one embodiment of the present invention; Figure 21 shows the column groups a memory array in accordance with one embodiment of the present invention;

Figure 22 shows a table of an Input/Output bit to group remapping in accordance with one embodiment of the present invention;

Figure 23 shows a table of the column driver Input/Output in accordance with one embodiment of the present invention;

Figure 24 shows a block diagram of the column driver in accordance with one embodiment of the present invention;

Figure 25 shows a schematic diagram of the read configuration of the for one output data bit in accordance with one embodiment of the present invention; Figure 26 shows a table of the Input/Output signals of the sense amplifier of

Figure 2;

Figure 27 shows a block diagram of the sense amplifier of Figure 2;

Figure 28 shows a table of the Input/Output signals of the row decoder of Figure 2; Figure 29 shows a block diagram of the row decoder of Figure 2; Figure 30 shows a table of the Input/Output signals of the column decoder of Figure 2;

Figure 31 shows a block diagram of the column decoder of Figure 2;

Figure 32 shows a timing diagram of the read mode of a memory array in accordance with one embodiment of the present invention;

Figure 33 shows a timing diagram of the write mode of a memory array in accordance with one embodiment of the present invention;

Figure 34 shows a read/write control truth table of a control circuit in accordance with one embodiment of the present invention; and Figure 35 shows the Read/Write Control (rw_ctrl) state machine of a control circuit in accordance with one embodiment of the present invention.

The description will use the following conventions and notations. All power ports have the string VDD in their name. All ground ports have the string GND in their name. When buses are referred to, they will be referred to using the term "bus_name[n:m]" notation, where n is the Most Significant Bit (MSB) and m is the Least Significant Bit (LSB). For example, in reference to Figure 1 , where the bus notation [7:0] is used, 7 is the MSB, and 0 is the LSB of the bus. Individual bits will be referred to using the term "bus_name[x]", where x is in the range of [n:m]. Sub-block interface port names are in capitals. In the following description, a physical horizontal row is referred to as either a row, a wordline (WL) or x. A physical vertical column is referred to either by a column, a bitline (BL) or y.

The terms "blown fuse" and "not blown fuse" are used and in order for them to translate in terms of logic-Os and logic-1s, the bitline (BL) state during write is used as a reference. When a fuse is a "blown fuse", the bitline should be connected to the VDD voltage level, which can be represented by a logic-1. When a fuse is a "non-blown fuse", the bitline should be connected to the GND voltage level, which can be represented by a logic-0. Thus, a blown fuse, or the command to blow a fuse is represented by a logic-1. A non-blown fuse, or the command to not blow a fuse is represented by a logic-0.

In reference to Figure 2, every Disable Soft Address (DSA) bit on the "senseamp" sub-block 6 is connected to a DSA bit coming from the "coldrv" sub-block 5 and to the corresponding Bit Line Reference (BLREF) pin of the "fusearray" sub- block 2. In this case, 17 NMOS transistors are placed in parallel. 16 in the "coldrv" sub- block 5, and 1 in the "fusearray" sub-block 2. Only 1 of those 17 transistors can be active at any one time.

Figure 2 shows the six top-level sub-blocks of the memory device according to one embodiment of the present invention. The top-level input and output signals of the circuit shown in Figure 2 are shown in the table of Figure 3. A description of each sub- block is given in the table of Figure 4.

Now, with reference to Figure 5, the memory bitcell 9 in accordance with one embodiment of the present invention will now be described. The bitcell 9 is the basic element of the memory array. Each bitcell 9 consists of a fuse 12 (or micro fuse) and an N-type transistor 13.

Preferably, the fuse 12 is a micro-fuse as described in patent application number PCT/GB04/00655. The central fuse region (or fusible region) is provided suspended above the insulated substrate and supported at either end from the substrate. The centre region has dimensions which can be controlled to a high degree of accuracy such that the central fusible region can be destroyed by application of an appropriate control current in an very reliable and predictable way. The fuse is a double-clamped cantilever structure which does not touch the substrate along its length. Because the wire does not touch the substrate, the heat loss is via thermal conduction along the wire length, rather than out through the substrate. The heat is related to the resistance in the free standing wire. Because of simple thermal properties, the fuses can be designed to predictably fuse when a well defined voltage is applied to its terminals. There is also a well defined temperature dependence along the wire length, with the central portion being the hottest. Therefore, the temperature at the centre of the wire can be controlled with great accuracy. A consequence of this is that a very small region can be melted in a controllable fashion at the centre of the free standing double clamped cantilever. Because the melted region is small, there is a lower probability that the evaporated metal will short out the fused wire, or that the melted material will land somewhere else on the chip and cause damage. When the central part of the double cantilever has been melted away the two end parts remain free standing. This means that the broken fuse does not touch the surrounding insulator, which may have some evaporated metal on its surfaces. This helps in maintaining a well defined difference between the on and off resistance. The threshold for blowing the device is given by the voltage dropped along the wire which is a product of the wire dimensions and the wire resistivity. As these values are well controlled, the voltage for switching is easy to predicted with a high degree of accuracy. To read the state of the wire, the current through the wire is measured with a device to limit the voltage drop across the fuse. To blow the wire the current limiting device (i.e. transitor 13) is removed, thereby resulting in a voltage being dropped across the wire that is greater than the threshold for voltage for melting (fusing) the wire. Because the wire is not connected to the substrate along its length it has a very small specific heat which allows it to reach melting temperatures in a very short time. In should be noted that any other suitable fuse (or micro-fuse) could be used in the present invention. The fuse may be formed from any readily oxidisable metal such as, Titanium, Tungsten, Tantalum, Copper or Aluminium. In this embodiment, and in reference to Figure 5, the gate (i.e. input terminal) of the transistor 13 is connected to a horizontal wordline (WL) 11. The source (i.e. common terminal) of the transistor is connected to the ground and the drain (output terminal) to one end of the fuse 12. The other end of the fuse 12 is connected to the vertical bitline (BL) 10. To write to or read from the memory bitcell, both WL and BL must be enabled.

A write operation is performed by setting the BL voltage to the normal supply voltage (VDD) for a certain period of time (e.g. 10μs) and blowing the fuse 12, thereby setting its logic level to logic-1. Preferably, a transistor with dimensions W=10μ, and L=O.35μ is used. To read the information contained in the bitcell, the BL and WL are both enabled for a short period of time. However, during a read operation, the current flowing through the BL, and possibly through the fuse 12, is low enough not to blow the fuse 12. Figure 6 is a table of the pinout of the memory cell. A block diagram of a memory cell is shown in Figure 7. By combining multiple bitcells, an memory array can be built. This array can be expanded in both x and y directions, where x is in the vertical direction, and called a row, and y is in the horizontal direction and called a column.

With reference to Figure 8, an array is created by connecting memory bitcells in a row/column configuration. A total of 128 rows are created in the vertical direction, numbered from 0 up to and including 127. A total of 128 columns are created in the horizontal direction, numbered from 0 up to and including 127. Again, in reference to Figure 8, WL[O] is the bottom line and WL[127] is the top line whereas BL[O] is the far left-hand side and BL[127] is on the far right-hand side. This configuration produces a total of 128x128 = 16384 (16kbit) individually accessible bitcells. Figure 10 is a table of the pinout of the memory array. A block diagram of the memory array is shown in Figure 10.

To be able to read out data in a proper way, a reference is used. One input of the "senseamp" sub-block 6 is connected to..the. actual BL, and the other input is connected to this reference. To enable precise readouts, different reference levels are used.

Figure 11 indicates the use of the different reference levels. A non-blown fuse 12 will have a resistance of about 500Ω. A blown fuse 12 will have a resistance which should be close to infinite. For readout, ten fuses in series may be used for the reference, giving a reference of 5kΩ. Because the distribution curve for the resistances of the fuses is not shaped as a normal one, fuses with a bigger resistance than 500Ω in the non-blown state can be available (for example, 1 kΩ or more). In such a case, the margin with respect to the reference of 5kΩ is decreased. The same happens for blown fuses, where resistances can be farther from infinity than expected. For this reason a verify read is built in, with two different reference levels. One reference level is close to the resistance of a non-blown fuse (for example 2kΩ) and the other is close to the resistance of a blown fuse (for example 8kΩ). During the initial read out, when all fuses are not yet blown, the reference which is close to a non-blown fuse is used, thereby increasing the margin with respect to the reference of 5kΩ. When, after programming, the fuse is readout with a reference of, for example,

8kΩ, extra margin with respect to the reference of 5kΩ is created. This is also needed, because of the ageing effect of the fuses. Typically, non-blown fuses of 500Ω initially will slowly increase in value, which will decrease the margin with respect to the reference of 5kΩ, which is fixed. To create a good reference for the sense amplifiers, one additional horizontal

WL is used, which is not enabled via the rowdecoder. This WL contains 128 fuses, from which 8 groups of 16 in series connected fuses are created. Each of the 8 sense amplifiers is connected to its own reference supply. These 16 fuses connected in series are configured in such a way that only a defined number of fuses are placed in series. This gives the possibility of selecting between different reference levels. One part of a series 16 fuses is shown in Figure 12. During power down, the reference WL should be switched off. With a 10 bits bus called SERSEL (SERial tap SELect) a different number of fuses in series can be selected. The output BLREF is connected to the sense amplifier as a reference via an NMOS transistor, which is switched by RLE. As a reference, one additional WL is placed at the bottom of the array. The reference line is switched on and off using the RLE signal from the "rw_ctrP sub-block 3. An NMOS transistor in series with the reference line is used as shown in Figure 12. RLE shall only be switched on in READ mode and TEST mode (which is the loop-back mode). A 10 bit control bus called SERSEL[9:0] is provided to set the number of fuses which are connected in series, as stated in the table of Figure 13.

To make different reference selections available via external pins, 3 different read command pins are used: R, VRO, and VR1. During normal read out, which is enabled by pin R, 10 fuses are connected in series. However a different number is selectable, by changing the value of SERSEL.

During verify read "close to not blown", which is enabled by pin VRO₁ only three fuses are to be connected in series. During verify read "close to blown", which is enabled by pin VR1 , all 16 fuses are connected in series. Eight groups of 16 serial connected fuses are created. The fuse numbers used on the WL are stated in the table of Figure 14.

Every BL has the ability to be forced to GND or VDD, or have the ability to float during read mode. Therefore two transistors are connected in parallel to the BL, as shown in Figure 15. In parallel to the BL, an NMOS type RST transistor is provided order to connect the BL to ground level, or to isolate it from ground level. In parallel with the BL, a PMOS type DW transistor is provided to be able to isolate the BL from VDD, or to supply the BL with the required voltage to blow the fuse.

Also, a multiplexer is needed to multiplex 128 BLs to 8 data output bits in read mode. In write mode, 8 data input bits should be demultiplexed to 128 BLs. Based on whether the device is in read or write mode, the transistors which are connected to the BL are controlled in such a way that the BL is in a correct state for the read or write operations.

The write mode is shown in Figure 16. In this example, to blow the selected fuse, BL[O] should be set to VDD. This is done by activating DW[O] and deactivating

RST[O], and BLE[O]. By activating WL[O], the fuse will be blown. The non-selected BLs should be connected to ground. In the example of Figure 16, this is done by deactivating DW[1] and BLE[I], and activating RST[I].

The read mode is shown in Figure 17. In this case, to readout the selected fuse

BL[O] should be charged via BLE[O] to a reference voltage. This is done by deactivating

DW[O] and RST[O] and shortly activating BLE[O]. When WL[O] is activated the BL will discharge, or keep its charge based on the state of the fuse. The non-selected fuses, which, in the example of Figure 17, are connected to BL[1], should be connected to ground. This is done by deactivating DW[1] and BLE[I] and activating RST[I].

Based on the behaviour of the above circuit, a truth table can be generated as stated in the table of Figure 18. The inputs for the truth table are as follows. R is the read mode indicator. W is the write mode indicator. Both R and W or generated by the read_write control logic. Dl is the registered incoming data. CLE is the columnline enable and is generated by the "coldec" sub-block 6. The CLE signal is used to select or deselect a BL. The outputs RST, DW, and BLE are used to control the transistors which are connected to the BL. The "coldrv" sub-block 5 controls transistors which are attached to the BL.

Input signals RST, DW and BLE are controlled in accordance with the boolean equations found in the table of Figure 19. Based on these equations, a possible implementation of a control circuit is shown in Figure 20.

The column driver is pitch limited. This means that the width of each individual column buffer/driver has the same width as the bitcell.

Columns are placed from left to right in a vertical direction, counting from 0 on the left side up to 127 on the right side. The total number of 128 columns is divided in 8 groups of 16 columns each. Each of the 8 individual input and output data bits are connected via a multiplexing scheme to one of the 8 groups of 16 columns as stated in Figure 21. Each data input and output pair (DI/DSA) shall serve only one out of 8 groups of 16 columns as stated in the table of Figure 22.

Column drivers are numbered from 0 to 127 and are physically layed out from 0 on the left side, to 127 on the right side. Inside a group of 16 column drivers, only one column is active. The active column is selected with the CLE signal, which is generated by the "coldec" sub-block 6.

In a group of 16 column drivers, only one column is active at any one time. The active column is selected with the signal CLE. Selection is performed as stated below.

CLE[O] is active -> column 0 is activated. • CLE[I] is active -> column 1 is activated.

CLE[15] is active -> column 15 is activated. When all CLE[15:0] inputs are inactive, none of the columns shall be activated. By way of example, when, during read mode CLE[n] is active, DSA[m] is connected to columns [(m x 16) + n]. Where n ranges from 0 to 15 and m ranges from 0 to 7. When, for example, CLE[4] is active, DSA[O] is connected to column 4, DSA[I] is connected to column 20 and DSA[7] which is connected to column 116. In write mode, when CLE[n] is active the same scheme is used. In this case, columns [(m x 16) + n] are connected to Dl[m], where n ranges from 0 to 15, and m ranges from 0 to 7. The value of Dl[m] determines if the BL is activated or not depending if a fuse should be blown or not. When, for example, CLE[6] is active, and DI[2:0] is "111" and Dl[7:3] is "00000", where a 1 means "blow the fuse", and a 0 means "do not blow the fuse". In this particular, case columns 6, 22, and 38 are enabled to blow their connected fuses (based on WL activation).

Column driver inputs and outputs are defined in the table of Figure 23 and Figure 24 shows the block diagram of the column driver. To be able to describe the "senseamp" sub-block 6, additional information is needed about the read out of the memory array. Figure 25 shows the read configuration for one output data bit DO[O], which is connected to 16 BLs (i.e. BL[15:0]). Only one BL is connected to the sense amplifier. This is controlled by enabling only one out of 16 BLE transistors via BLE[15:0]. By way of example, if BL[O] is selected, DW[15:0] are disabled, RST[15:1] are enabled, and RST[O] is disabled. BLE[15:1] are disabled, and BLE[O] is enabled. This will cause all BLs to be connected to GND via the RST transistors, except for BL[O], which is connected to the sense amplifier via BLE[O]. In this condition, VREF will partially open transistor N1 , which will cause a small current to flow. This small current will charge capacitor CBL[O]. When the capacitor is charged, the current will decrease to zero. Before this can happen, WL[O] is activated, which will enable the capacitor to discharge via the fuse, if it is not yet blown. A constant current will flow, the value of which is determined by the total resistance in the line. This current will cause a voltage VBL. When the fuse is already blown, the current will go to zero, and VBL will be equal to zero.

On the reference side, the same happens. The reference voltage VREF will open N2 partly which will cause a small current to flow, when RLE, and SERSEL[2] are enabled. This current, the value of which is determined by the resistance in the line, will cause a voltage VRL, which will be transmitted to the sense amplifier. The complete readout configuration is shown in Figure 25. A sense amplifier is needed to detect the value of the contents in the bitcell. It comprises a differential amplifier and a latch which keeps the value stored until the next readout. The sense amplifier should detect a difference in voltage of at least 10OmV.

The sense amplifier is active during the activation of the PROBE signal coming from the "rw_ctrl" sub-block 3.

The "senseamp" sub-block 6 latches the sensed value at the falling edge of the

PROBE signal. The"senseamp" sub-block 6 has a calibration (NULL setting) option, which is activated by the signal NULLN, which is low active. The "senseamp" sub-block

6 also has a reset which will reset the latch stage of the sense amplifier by forcing the output to zero, called RST.

When RSTN is activated, the outputs of the "senseamp" sub-block 6 are to be set to logic-0. A built in loop back mode is available. This will enable the testing of the sense amplifier but also makes modelling during ATPG or functional testing easier.

The"senseamp" sub-block 6 has a loop back mode, which will select the registered input data Dl, instead of the BL voltage DSA. The result will be put on the output DO. For loop-back mode, the registered digital signal Dl is converted to an analog equivalent, which replaced DSA. During loop-back mode, the signal YEN shall be forced to 0. During loop-back mode, the signal PROBE shall be available

The "senseamp" sub-block 6 has a selection pin called LOOPB. When LOOPB is high, the loop back mode is be selected.

The reference voltage generator is part of the sense amplifier. It can be controlled via the GAIN pin. The reference voltage supply works with a single 3.3V input voltage. The reference voltage supply makes use of a reference voltage pin called GAIN to be able to bias the voltage generator. The reference voltage supply generates a reference voltage of 1.0V with a tolerance of ± 1%. The reference voltage supply is able to supply a current of 4mA to a capacitance of 3pF within 3ns, with a maximum overshoot of 10mV and a maximum voltage drop of 5mV. The reference voltage supply generates a stable voltage in a temperature range between -55^°C and 125^°C. The sense amplifier inputs and outputs are defined in the table of Figure 26. Figure 27 shows a block diagram of the "senseamp" sub-block 6.

The "rowdec" sub-block 4 is needed to translate address bits into WL selection bits. The row decoder shall decode 7 address bits to 128 WL selection bits, from which only one WL selection bit is active per selected address. Row decoding shall be performed as follows: A[6:0] is: 0000000 -> selected WL is: WL[O]. A[6:0] is: 0000001 -> selected WL is: WL[I].

• A[6:0] is: 1111111 -> selected WL is: WL[127].

The "rowdec" sub-block 4 has an active high enable, called LE. When the enable signal is inactive, all 128 WL selection bits shall be inactive. From a layout point of view, WL selection bit WL[O], are situated at the bottom right corner of the decoder and WL selection bit 127 is located at the top right corner of the decoder.

The "rowdec" sub-block 4 is also pitch limited. This means that the height of one row is determined by the height of the bitcell. The output driver is strong enough to drive a WL.

For test purposes, the row decoder is equipped with an OR-TREE. However this OR-TREE is physically part of the array, where it is connected at the end of each word line. The OR-TREE output shall directly be connected to the "rw_ctrl" sub-block

3. The "rowdec" inputs and outputs are defined in the table of Figure 29. Figure 30 shows the block diagram of the "rowdec" sub-block 4.

The "coldec" sub-block 6 is needed to translate address bits into BL selection bits. The "coldec" sub-block 6 decodes 4 address bits to 16 BL selection bits, from which only one BL selection bit is active per selected address. Column decoding is performed in the following way:

A[3:0] is: 0000 -> selected BL is: BL[O]. ^• A[3:0] is: 0001 -> selected BL is: BL[I].

A[3:0] is: 1111 -> selected BL is: BL[15J.

The "coldec" sub-block 6 has an active high enable, called LE. When the enable signal is inactive, all 16 BL selection bits shall be inactive. From a layout point of view, the BL selection bit BL[O] is situated at the bottom right corner of the decoder whereas the BL selection bit BL[15] is located at the top right comer of the decoder, ach output driver is strong enough to drive the logic which is connected to the BL. For test purposes, the "coldec" sub-block 6 is equipped with an OR-TREE. The "coldec" sub- block 6 inputs and outputs are defined in the table of Figure 30. Figure 31 shows the block diagram of the "coldec" sub-block 6.

The "rw_ctrl" sub-block 3 provides several control signals. Its main functions are registering data and address, determining the mode/state of the memory macro (e.g. read, write, test mode) and generating timing signals.

Figure 32 shows the timing diagram for a single read and multiple read actions.

Read mode is entered and a read cycle is started after a detection of R and CS at the rising edge of the clock. At the start of a read cycle, the address is registered. Data is available at the output one clock cycle after starting the read cycle. At activation of RSTN, the current read cycle is terminated.

Figure 33 shows the timing for a single write and multiple write actions. Write mode is entered and a write cycle is started after a detection of !R and W and CS at the rising edge of the clock. To finish a write cycle, CS and TW are active at the rising edge of the clock. At the start of a write cycle, both address and input data is registered. Before finishing a write cycle with a combination of CS and TW, a time of at least 10μs must be elapsed.

At activation of RSTN the current write cycle is terminated. RSTN or a combination of CS and TW can terminate the current write cycle. Any other combination shall not terminate the current write cycle. To enter or stay in the test mode CS, !R, !W and MODE are detected at the rising edge of the clock. During test mode, actually the loopback mode is activated in which the registered input data is connected to the input of the sense amplifiers at the output. It is to be noted that the "!" sign indicates that the inverted signal is used.

During loop-back mode, the PROBE signal is available. At the start of a test cycle, input data and address are registered.

The table of Figure 34 shows the truth table for the "rw_ctrl" sub-block 3. On the left side of the vertical double lines, the input conditions are shown. Starting from a given current state which is indicated in the heading of the right side of the table of

Figure 34, the next state is indicated on the right side of the table. The abbreviations are:

Idle mode IDLE I

Read mode READ R

Write mode WRITE W

Finish write mode FINWR FW • Test mode TEST T Figure 35 shows the state machine to which the read write controller will comply. The state machine of Figure 35 is based on the truth table of Figure 34.

Claims

1. A one time-programmable memory bitcell (9) comprising: a transistor (13); and a fuse (12); wherein the transistor is arranged to receive a first signal and, upon receipt of the first signal, to enable communication of a second signal to the fuse.

2. The one time-programmable memory bitcell (9) of claim 1 , wherein the fuse is a double-clamped cantilever micro fuse.

3. The one time-programmable memory bitcell (9) of any of claims 1 and 2, wherein: the input terminal of the transistor (13) is connected to the source of the first signal; the output terminal of the transistor is connected to one terminal of the fuse (12); and the other terminal of the fuse is connected to the source of the second signal.

4. A one time-programmable memory module comprising: an array of one time-programmable memory bitcells (9) according to any of the preceding claims; a write circuit arranged to blow, during a write operation, a predetermined selection of the fuses in the array by supplying the first signal for a predetermined time period and the second signal having a first amplitude for a predetermined period of time; and a read circuit comprising detection means arranged to detect, during a read operation, whether or not a fuse is blown by supplying the first signal for a predetermined time period and the second signal having a second amplitude for a predetermined amount of time.

5. The one time-programmable memory module according to claim 4, wherein the detection means comprises a plurality of sense amplifiers, each sense amplifier comprising a differential amplifier, a reference voltage generator and a latch; wherein each sense amplifier is arranged to detect the voltage across each fuse relative to a voltage generated by the reference voltage generator and to store the detected voltage values in the latch.

6. The one time-programmable memory module according to claim 5, wherein the reference voltage generator is arranged to generate two different reference voltages.