CN106782658A - It is applied to the E fuse circuits and data read method of FPGA circuitry - Google Patents
It is applied to the E fuse circuits and data read method of FPGA circuitry Download PDFInfo
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- CN106782658A CN106782658A CN201610991048.2A CN201610991048A CN106782658A CN 106782658 A CN106782658 A CN 106782658A CN 201610991048 A CN201610991048 A CN 201610991048A CN 106782658 A CN106782658 A CN 106782658A
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
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- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The present invention relates to a kind of E fuse circuits for being applied to FPGA circuitry, including：Write data circuit, data reading circuit and public circuit；Data read method includes that write operation premode data output end exports original state, default storage " 0 "；Write operation pattern：Data reading circuit does not work, and writes data circuit and public circuit is opened, and fuse is programmed；Read operation pattern：Write data division not work, data reading circuit and public circuit are opened, and data read-out end reads " 1 " or " 0 ".The present invention utilizes electromigration effect, and using electronic programmable fuse E fuse as memory cell, the E fuse memory cell structures comprising 3 metal-oxide-semiconductors and 1 E fuse can intactly complete write/read operation, be simple in structure and convenient in use.
Description
Technical field
The present invention relates to FPGA circuitry, specifically, relate to be applied to E-s of the FPGA using E-fuse fuse resistors
Fuse circuits and its data read method.
Background technology
With the raising of IC design level, the function of chip is stronger and stronger, integration density constantly being lifted,
The quantity of the transistor in integrated circuit also shows the trend of exponential increase, while the size of transistor also constantly reduces.
Wherein in chip internal, memory circuitry will account for the 90% of whole chip area.Static memory is also due to its low-power consumption, height
The features such as speed, processing compatibility are good, is widely used in mobile device, computer CPU etc., but due to chip design technology
Become increasingly complex, certainly will be the more defects of chip belt, reduce chip yield, averagely have 40% SOC because losing
Effect is thrown away.So, in order to improve the yield rate of chip, redundancy is also constantly developing, wherein five stand-by units are just
Yield rate can be brought up to 67% from 1%.
With developing rapidly for integrated circuit technology, integrated circuit feature size drastically reduces, and traditional fuse starts cruelly
Reveal its weak point：Area occupied is big；Laser fuse metalloid fuse also needs to special instrument and equipment to complete；Trim's
During often burn continuous fuse or burn out chip；The voltage deviation problem that trim post packages cause.
Can not be worked in the memory cell power up such as SRAM cannot meet the demand of electricity guiding on FPGA circuitry, and other are non-
Volatile memory needs to be modified existing process, and processing compatibility is bad.E-fuse fuse areas occupied are small, and upper electricity is
Can use, processing compatibility is good.Memory cell based on E-fuse fuses increasingly shows its advantage.
The content of the invention
For above-mentioned technical deficiency, it is an object of the invention to provide a kind of E-fuse circuits and its number for being applied to FPGA circuitry
According to output intent.
The technical solution adopted for the present invention to solve the technical problems is：A kind of E-fuse electricity for being applied to FPGA circuitry
Road, including：Write data circuit, data reading circuit and public circuit；
Write data circuit, input receives the signal WL of programming decoding circuit output, and output end is defeated with public circuit
Enter end connection；
The data reading circuit, input receives the signal RD of global control circuit output, and output end is defeated with public circuit
Enter end connection；
The public circuit, external input terminals receive the signal BL of global control circuit output, and input is used as E-fuse
The data output end of circuit, for exporting storage value.
Write data circuit uses PMOS P0；The grid of PMOS P0 is used to connect programming decoding electricity as input
The signal WL of road output；Source is connected with power supply；Drain terminal is connected with public circuit input.
The data reading circuit uses PMOS P1；The grid of PMOS P1 is used to connect global control electricity as input
The signal RD of road output；Source is connected with power supply；Drain terminal is connected with public circuit input.
Breadth length ratio of the breadth length ratio of the PMOS P1 less than PMOS P0.
The public circuit includes the electrical fuse and NMOS tube N0 that are linked in sequence；The anode of electrical fuse and PMOS P0
Drain terminal, the connection of P1 drain terminals, also as the data output end of E-fuse circuits；The negative electrode of electrical fuse connects with the drain terminal of NMOS tube N0
Connect；The grid of NMOS tube N0 is used to connect the signal BL of global control circuit output, source ground as external input terminals.
A kind of data read method of the E-fuse circuits for being applied to FPGA circuitry, comprises the following steps：
Write operation premode：Write data circuit input signal WL, data reading circuit input signal RD and public circuit input
When signal BL is invalid, data output end output original state, default storage " 0 "；
Write operation pattern：Write data circuit input signal WL effectively, RD is invalid for data reading circuit input signal, while public
When circuit input signal BL is effective, data reading circuit does not work, and writes data circuit and public circuit is opened, and is constituted with electrical fuse
Current path, fuse is programmed；
Read operation pattern：Write data circuit input signal WL invalid, data reading circuit input signal RD is effective, while public
Circuit input signal BL effectively, writes data division and does not work, and data reading circuit and public circuit are opened, and data read-out end reads
" 1 " or " 0 ".
The data read-out end reads " 1 " or " 0 " and comprises the following steps：
When data reading circuit and public circuit are opened, resistance when PMOS P1 is turned on is more than fuse initial value and less than electricity
Resistance after sub- fuse failure；Data read-out end reads " 1 " or " 0 " according to data read-out terminal voltage value.
The invention has the advantages that and advantage：
1. the present invention utilizes electromigration effect, using electronic programmable fuse E-fuse as memory cell, comprising 3
Metal-oxide-semiconductor and 1 E-fuse memory cell structure of E-fuse, can intactly complete write/read operation, with simple structure, use
The advantages of facilitating.
2. the present invention is using based on E-fuse structure alternative metals fuses, used as fuse, metal fuse blowout current is general all
Reach more than 100MA；And programming time is too long, typically more than 1 millisecond；Metal fuse needs trim, probe before packaging
Probe is easily encountered together, causes short circuit, burns circuit；And E-fuse outline programming voltages are low, program current is small, and in envelope
It is programmed after dress, prevents from burning out chip.
3. the memory cell opposing metallic fuse-wires structure area occupied based on E-fuse is small, low in energy consumption.
4. it is programmed after the memory cell encapsulation based on E-fuse, asking for voltage deviation is caused in the absence of trim post packages
Topic.
Brief description of the drawings
Fig. 1 is circuit theory diagrams of the invention.
Fig. 2 a are the top views of the electronic programmable fuse structure that the present invention is used.
Fig. 2 b are the profiles of the electronic programmable fuse structure that the present invention is used.
Specific embodiment
With reference to embodiment, the present invention is described in further detail.
E-fuse technologies compare with traditional fuse, with the following powerful advantage：With existing CMOS technology
It is completely compatible, extra processing step, compatible small size technique are not increased；Electronic programmable fuse (E-fuse) circuit is whole
Occupied area is greatly reduced in the chip of body, is widely used in embedded system；Electronic programmable fuse (E-fuse) is compiled
Voltage is smaller, and compiling electric current is also smaller than traditional fuse compiling electric current, and power consumption is relatively low；Programming makes the situ configuration of chip after encapsulation
Ability strengthens；Test is more convenient, it is only necessary to which making alive galvanization is all right.
E-fuse technologies have been widely used in redundant circuit to improve the problem of chip failure, can be used to compile in FPGA
The Redundancy Design of journey memory cell array.In general, the redundancy section in the circuit such as FPGA is connected by fuse, when quilt in circuit
Defect is detected, then fuse can just be operated instead of defective part circuit, realize that redundancy is acted on.The E- in FPGA
The effect of fuse technologies is exactly that they can be with specific accompanying software knot for each chip increases substantial amounts of miniature electric fuse
Close, and chip can be made to distribute itself internal circuit to tackle different calculating tasks, or increase the computing of chip frequently
Rate.Increasing these fuses in the chips need not increase cost, it is possible to control the speed of each circuit, such that it is able to manage circuit
Performance and power consumption.E-fuse thoroughly can also cut off chip in the case where not influenceing other parts normally to run, and some are cached
Or functional module, this feature makes the utilization rate of flaw chip be improved, or closes some function moulds of chip
Block realizes the effect of lower power consumption.So this series of function of E-fuse both contributes to fpga chip reparation, in other words
That is E-fuse can do aftermath around some defects of chip.
E-fuse technologies are a kind of technologies grown up according to polysilicon fuse characteristic, and it is entered based on electromigration principle
Row Fuse is programmed.Originally, the resistance very little of polysilicon fuse, when there is high current to flow continuously through polysilicon fuse, fuse starts
Experience burns the process being blown by being melt, and at the same time, the resistance of fuse can also be multiplied.Under normal circumstances, fusing
Permanent holding breaking state referred to as " is programmed fuse " by polysilicon fuse, storage binary number " 1 "；And the polycrystalline not burnt
Silicon fuse stores binary number " 0 " still in conducting state.
The area and power consumption of existing memory elementary cell are improved using E-fuse technologies, the present invention proposes one kind and is based on
The simple memory elementary cell of E-fuse technologies.Including：Electronic programmable fuse E-fuse；Write data circuit；Read data electricity
Road；Public circuit.
Electronic programmable fuse E-fuse, according to electromigration effect, open circuit is turned into using larger program current, using molten
The difference of resistance sizes represents " 1 ", " 0 " value of storage before and after disconnected, and resistance is 50~200 ohm before programming, is 5K after programming
~500K ohm；
Data circuit is write, PMOS P0 sources meet program voltage VDDQ, and drain terminal meets data read-out end DOUT, constitutes and write number
According to part；
Data reading circuit, PMOS P1 sources meet operating voltage VDDI, and drain terminal meets data read-out end DOUT, constitutes reading
According to part；
Public circuit, the source ground connection of NMOS tube N0, drain terminal connects the negative electrode of electrical fuse, and the other end of electrical fuse is also
It is that anode meets data read-out end DOUT, the two elements constitute the public circuit of E-fuse memory cell.
Data circuit is write, PMOS P0 sizes are that ditch is long 0.15 micron, and a width of 8~32 microns of ditch is allowed to conducting resistance very
It is small, can reach 200 ohm~1K ohm.
Public circuit, NMOS tube N0 sizes are that ditch is long 0.15 micron, and a width of 8~16 microns of ditch is allowed to conducting resistance very little,
Can reach 200 ohm.
Data reading circuit, PMOS P1 sizes are that ditch is long 0.15 micron, a width of 0.4 micron of ditch, conducting resistance 15K~30K
Ohms, between resistance value of the conducting resistance before and after the fusing of E-fuse fuse resistors.
E-fuse technologies are a kind of technologies grown up according to polysilicon fuse characteristic, and it is entered based on electromigration principle
Row Fuse is programmed.Originally, the resistance very little of polysilicon fuse, when there is high current to flow continuously through polysilicon fuse, fuse starts
Experience burns the process being blown by being melt, and at the same time, the resistance of fuse can also be multiplied.Under normal circumstances, fusing
Permanent holding breaking state referred to as " is programmed fuse " by polysilicon fuse, storage binary number " 1 "；And the polycrystalline not burnt
Silicon fuse stores binary number " 0 " still in conducting state.
The area and power consumption of existing memory elementary cell are improved using E-fuse technologies, the present invention proposes one kind and is based on
The simple memory elementary cell of E-fuse technologies.Including：Electronic programmable fuse E-fuse；Write data circuit；Read data electricity
Road；Public circuit.
The polysilicon fuse of electronic programmable fuse E-fuse is usually to make in shallow-trench isolation, and its bottom is that silica is exhausted
Edge layer.The part of fuse is polysilicon and silicide alloy two parts composition, and silicide alloy is ion implanting on the polysilicon
One layer of alloy of silicide is formed, its Main Function is to reduce resistance value and increase Ohmic contact between the two poles of the earth.Finally enter
The covering protection of row silicon nitride.
Write data circuit and program voltage VDDQ is connect by PMOS P0 sources, drain terminal connects data read-out end DOUT compositions.
Data reading circuit meets operating voltage VDDI by PMOS P1 sources, and drain terminal connects data read-out end DOUT compositions.
The source ground connection of NMOS tube N0, drain terminal connects the negative electrode of electrical fuse, and the other end i.e. anode of electrical fuse connect
Data read-out end DOUT, the two elements constitute the common part of E-fuse memory cell.
Fig. 2 a-2b are the top view and profile of the electronic programmable fuse structure that the present invention is used.Such as Fig. 2 a-2b institutes
Show, electronic programmable fuse E-fuse (electrically programmable fuse), be located at two electrodes between very
One section of short polysilicon of minimum widith, as shown in Figure 2 a, electronic programmable fuse is compatible with standard CMOS process, is set in domain
The area of general negative electrode and anode is more much larger than metallic bond in meter, like the shape of " bone ".Theoretical, the E-fuse according to electromigration
Anode connects program voltage, and after minus earth, two electrode potentials are different between electrodes to form an electric current for stabilization, work as unit
The electric current that area cross-section passes through under the collective effect of electronics and electrostatic force, produces one when i.e. current density reaches certain numerical value
To the electron wind violence of anode movement, promote atom to be migrated along electron motion direction, atom cavity is formed, due to silication
The resistivity of thing alloy, so the current density of silicide alloy layer is very big, forms electric current office much smaller than the resistivity of polysilicon
The aggregation in portion, the local joule heating effect causes that electromigration occurs in this layer first.Fuse shows as permanent electricity high
Resistance, so the fuse of programming is needed in E-fuse circuits turns into open circuit by larger program current.E-fuse circuits are exactly to transport
The difference of resistance sizes represents " 0 " " 1 " value of storage before and after row programming, and resistance is hundreds of ohm before programming, is several K after programming
Ohm.
Fig. 1 is the original of the design that specifically show a kind of E-fuse circuit structures for being applied to FPGA circuitry of the invention
Reason figure.E-fuse units can be operated under three kinds of mode of operations (WL, RD be " 1 " it is invalid, " 0 " effectively；BL is that " 0 " is invalid, " 1 "
Effectively)：
Write operation premode：WL, RD and BL are invalid before programming, i.e., WL, RD are " 1 ", and BL is " 0 ", and electrical fuse initially hinders
Value very little, the original state default storage " 0 " of E-fuse memory cell.
Write operation pattern：When write operation, effectively, RD is invalid for WL, while BL is effectively, i.e. WL is " 0 ", and RD is " 1 ", and BL is
" 1 ", reads data division and does not work, and P0 and N0 are opened, and electronic programmable fuse Efuse constitute together it is big from VDDQ to GND
Current path, under high current effect, E-fuse electronic programmable fuses are programmed.
Read operation pattern：When read operation, WL is invalid, and effectively, while BL is effectively, i.e. WL is " 1 " to RD, and RD is " 0 ", and BL is
" 1 ", writes data division and does not work, and P1 and N0 is opened, because P1 is designed to the less transistor of breadth length ratio, size, during conducting
Resistance can be equivalent to more than electrical fuse initial value but less than the resistance of resistance after electrical fuse fusing, therefore can at data read-out end
" 1 " or " 0 " is read according to the ratio between resistance.
Then the logic reading circuit for being connect by data output end DOUT, the logical value that will be stored in memory cell is read.
" 0 ", " 1 " is just read separately below to be illustrated：
When reading, if be not selected before the unit carrying out programming, E-fuse electronic programmable fuses are not
It is blown, its resistance opens resistance much smaller than P1, according to Ohm's law, then the performance of DOUT output voltages is " 0 ".
When reading, if be selected before the unit carrying out programming, E-fuse electronic programmable fuses are blown,
Its resistance opens resistance much larger than P1, and according to Ohm's law, then the performance of DOUT output voltages is " 1 ".
According to above-mentioned implementation method, employ using the E-fuse electronic programmable fuses of electromigration effect, one
Write data unit, reading data unit and storage organization put together, and complete an E-fuse for the write/read operation of binary code
Memory cell.
Claims (7)
1. a kind of E-fuse circuits for being applied to FPGA circuitry, it is characterised in that including：Write data circuit, data reading circuit and public affairs
Use circuit；
Write data circuit, input receives the signal WL of programming decoding circuit output, output end and public circuit input
Connection；
The data reading circuit, input receives the signal RD of global control circuit output, output end and public circuit input
Connection；
The public circuit, external input terminals receive the signal BL of global control circuit output, and input is used as E-fuse circuits
Data output end, for exporting storage value.
2. a kind of E-fuse circuits and its state output method for being applied to FPGA circuitry according to claim 1, it is special
Levy is that write data circuit uses PMOS P0；The grid of PMOS P0 is used to connect programming decoding circuit as input
The signal WL of output；Source is connected with power supply；Drain terminal is connected with public circuit input.
3. a kind of E-fuse circuits and its state output method for being applied to FPGA circuitry according to claim 1, it is special
Levy is that the data reading circuit uses PMOS P1；The grid of PMOS P1 is used to connect global control circuit as input
The signal RD of output；Source is connected with power supply；Drain terminal is connected with public circuit input.
4. a kind of E-fuse circuits and its state output method for being applied to FPGA circuitry according to claim 3, it is special
It is breadth length ratio of the breadth length ratio of the PMOS P1 less than PMOS P0 to levy.
5. a kind of E-fuse circuits and its state output method for being applied to FPGA circuitry according to claim 1, it is special
Levy is that the public circuit includes the electrical fuse and NMOS tube N0 that are linked in sequence；The anode of electrical fuse leaks with PMOS P0
End, the connection of P1 drain terminals, also as the data output end of E-fuse circuits；The negative electrode of electrical fuse connects with the drain terminal of NMOS tube N0
Connect；The grid of NMOS tube N0 is used to connect the signal BL of global control circuit output, source ground as external input terminals.
6. a kind of data read method of the E-fuse circuits for being applied to FPGA circuitry, it is characterised in that comprise the following steps：
Write operation premode：Write data circuit input signal WL, data reading circuit input signal RD and public circuit input signal
When BL is invalid, data output end output original state, default storage " 0 "；
Write operation pattern：Write data circuit input signal WL effectively, RD is invalid for data reading circuit input signal, while public circuit
When input signal BL is effective, data reading circuit is not worked, and writes data circuit and public circuit is opened, and electric current is constituted with electrical fuse
Path, fuse is programmed；
Read operation pattern：Write data circuit input signal WL invalid, data reading circuit input signal RD is effective, while public circuit
Input signal BL effectively, writes data division and does not work, and data reading circuit and public circuit are opened, data read-out end read " 1 " or
“0”。
7. a kind of data read method of E-fuse circuits for being applied to FPGA circuitry according to claim 6, its feature
It is that data read-out end reading " 1 " or " 0 " comprises the following steps：
When data reading circuit and public circuit are opened, resistance when PMOS P1 is turned on is more than fuse initial value and molten less than electronics
Resistance after silk fusing；Data read-out end reads " 1 " or " 0 " according to data read-out terminal voltage value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610991048.2A CN106782658A (en) | 2016-11-08 | 2016-11-08 | It is applied to the E fuse circuits and data read method of FPGA circuitry |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610991048.2A CN106782658A (en) | 2016-11-08 | 2016-11-08 | It is applied to the E fuse circuits and data read method of FPGA circuitry |
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| CN106782658A true CN106782658A (en) | 2017-05-31 |
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| CN201610991048.2A Pending CN106782658A (en) | 2016-11-08 | 2016-11-08 | It is applied to the E fuse circuits and data read method of FPGA circuitry |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112003606A (en) * | 2020-07-27 | 2020-11-27 | 北京炎黄国芯科技有限公司 | E-fuse programming and reading circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007017692A1 (en) * | 2005-08-10 | 2007-02-15 | Cavendish Kinetics Ltd | Fuse memory bitcell and array thereof |
| CN101556828A (en) * | 2008-02-13 | 2009-10-14 | 美格纳半导体有限会社 | Unit cell of nonvolatile memory device and nonvolatile memory device having the same |
| CN102347310A (en) * | 2010-07-30 | 2012-02-08 | 索尼公司 | Semiconductor device and method of driving the same |
| CN102738114A (en) * | 2011-04-11 | 2012-10-17 | 台湾积体电路制造股份有限公司 | Non-salicide polysilicon fuse |
-
2016
- 2016-11-08 CN CN201610991048.2A patent/CN106782658A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007017692A1 (en) * | 2005-08-10 | 2007-02-15 | Cavendish Kinetics Ltd | Fuse memory bitcell and array thereof |
| CN101556828A (en) * | 2008-02-13 | 2009-10-14 | 美格纳半导体有限会社 | Unit cell of nonvolatile memory device and nonvolatile memory device having the same |
| CN102347310A (en) * | 2010-07-30 | 2012-02-08 | 索尼公司 | Semiconductor device and method of driving the same |
| CN102738114A (en) * | 2011-04-11 | 2012-10-17 | 台湾积体电路制造股份有限公司 | Non-salicide polysilicon fuse |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112003606A (en) * | 2020-07-27 | 2020-11-27 | 北京炎黄国芯科技有限公司 | E-fuse programming and reading circuit |
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Application publication date: 20170531 |