WO2007017388A1

WO2007017388A1 - Method and device for analyzing processes in a computer system having a plurality of execution units

Info

Publication number: WO2007017388A1
Application number: PCT/EP2006/064694
Authority: WO
Inventors: Reinhard Weiberle; Bernd Mueller; Ralf Angerbauer; Eberhard Boehl; Yorck Collani; Rainer Gmehlich
Original assignee: Robert Bosch Gmbh
Priority date: 2005-08-08
Filing date: 2006-07-26
Publication date: 2007-02-15
Also published as: EP1917596A1; DE102005037232A1; JP2009506408A; CN101243411A

Abstract

The invention relates to a method and a device for analyzing processes in a computer system having a plurality of execution units that can be configured in at least two different modes in the computer system. At least two execution units operate in a performance mode as a first mode and at least one second mode is provided as the comparative mode. For analyzing and/or influencing states and operations in all execution units, analytical units, especially debug support units, are used. The invention is characterized in that the device comprises at least one analytical unit more than the maximum number of execution units that independently operate in the performance mode.

Description

R. 312750

Method and device for analyzing processes in a computer system with several execution units

State of the art

Transient errors, caused by alpha particles or cosmic rays, are increasingly becoming a problem for semiconductor integrated circuits. With decreasing feature widths, decreasing voltages, and higher clock frequencies, the likelihood that a charge change caused by an alpha particle or cosmic rays will distort a logic value in an integrated circuit increases. A wrong calculation result can be the result. In safety-relevant systems, in particular in motor vehicles, it is therefore necessary to reliably detect defective faults.

For safety-relevant systems, such. As an ABS control system in a motor vehicle, in which malfunctions of the electronics must be detected safely, usually redundancies are used for error detection in the eit- speaking control devices such systems. For example, in known ABS systems, the complete microcontroller is duplicated in each case, the entire ABS functions being redundantly calculated and checked for conformity. If a discrepancy of the results occurs, the ABS system is switched off.

A microcontroller consists on the one hand of memory modules (eg RAM, ROM, cache), one processor (CPU, core) and of input / output interfaces, so-called peripherals (eg A / D converter, CAN -Interface). Since memory elements can be effectively monitored with check codes (parity or ECC), and peripherals are often application-specific as part of a string. sor or actuator signal paths are monitored, there is another redundancy approach in the sole doubling of the cores of a microcontroller.

Such microcontrollers with at least two integrated cores are also known as dual-core architectures. Both cores execute the same program segment redundantly and in isochronous mode (lockstep mode), the results of the two cores are compared, and an error is then detected in the comparison for consistency. This configuration of a dual-core system can be called a comparison mode.

Dual-core architectures are also used in other applications to increase performance, ie to increase performance. Both cores execute different programs, program segments, and commands, which can improve performance, so this configuration of a dual-core system can be called a performance mode. This system is also referred to as a symmetric multiprocessor system (SMP). An extension of these systems is software switching between these two modes of access to a specific address and specialized hardware devices. In comparison mode, the output signals of the cores are compared with each other. In performance mode, the two cores work as a symmetric multiprocessor (SMP) system and execute different programs, program segments, or commands. When developing software for a μC, it is necessary to be able to accurately track the effects of certain program steps and to use test modes to detect errors in the SW during development. Debug concepts are used. In the prior art, there are debug concepts for software development for the previously introduced dual-core architectures, which run either purely in Lockstep or purely in SMP operation.

For a switchable system, no debug concept is known in the prior art. However, as the switchover has to be taken into account especially during test or debugging, it is necessary to develop a dedicated debug concept for a switchable system.

Advantages of the invention

An advantage according to claim 1 is that in a computer system having multiple execution units or components operating in at least two different modes in the system are configurable, which differ in that in the one mode, at least two components in a performance mode by these components process different input signals to different output signals and process in an at least second mode, these components in a comparison mode equal input signals to the same output signals, and in that for analyzing and / or influencing the states and processes in all execution units or component analysis units, in particular debug support units, more analysis units are present than execution units or components in a performance mode can operate independently of each other and thus different modes of the system are better observable and influenceable.

A further advantage of the system is that in this case all execution units or components which do not cooperate with other execution units or components in a comparison mode in at least one first mode of the particular computer system are each assigned an analysis unit which monitors states and processes in this execution unit or component and / or can influence.

An additional advantage is that, in the case that in at least a second mode of the computer system, at least two execution units or components work together as a temporary subsystem in a compare mode and that subsystem is associated with a further analysis unit, observe the states and operations in that subsystem, and / or influence.

A further advantage is that observation and / or influencing of the states and sequences of all execution units of the subsystem, which cooperates in a comparison mode, can take place synchronously by the analysis unit.

A further advantage results from the fact that additional means are included which enable activation and / or deactivation of analysis units depending on the operating modes of the printer system and / or other predefinable conditions. - A -

A further advantage is that in the system at least one mode signal, preferably a core mode signal, can cause a change of activity of at least one of the analysis units.

It is also advantageous that control signals of at least one analysis unit can be used to switch over the activity of at least one further analysis unit.

It is furthermore advantageous that in a system with an active comparison mode of a subsystem, the analysis unit assigned to the subsystem is active and the analysis units of the execution units or components assigned to the subsystem are not active. Furthermore, it is also advantageous that in the system additionally the states or individual input signals of the execution units or components of the comparison means can be influenced by at least one analysis unit and the states or output signals of these influenced units can be observed by this or another analysis unit.

Further advantages and advantageous embodiments will become apparent from the features of the claims and the description.

characters

FIG. 1 shows a multiprocessor system with two execution units G 140a and

G 140b and the associated analysis units, in particular debug support units GlOOa and GlOOb and the debug support unit Gl 10.

FIG. 2 shows a multiprocessor system with two execution units G 140a and

G 140b and the associated analysis units, in particular debug support units GlOOa and GlOOb and the debug support unit Gl 10. Further included is a debug support management unit G 170 and a switching and comparison unit G200. FIG. 3 shows a multiprocessor system with two execution units G 140a and

G 140b and the associated debug support units GlOOa and GlOOb and the debug support unit Gl 10. Further included is a debug support management unit G 170 and a switching and comparison unit G200. The system works here in a performance mode.

FIG. 4 shows a multiprocessor system with two execution units G 140a and

G 140b and the associated debug support units GlOOa and GlOOb and the debug support unit Gl 10. Further included is a debug sub support management unit G 170 and a switching and comparison unit G200. The system works here in a comparison mode.

FIG. 5 shows a general case of the switching and comparison component, also for use with more than two execution units.

FIG. 6 shows the general form of the mode signal.

Description of the exemplary embodiments

An execution unit can in the following designate both a processor / core / CPU, as well as an FPU (Floating Point Unit), DSP (Digital Signal Processor), coprocessor or ALU (Arithmetic Logical Unit). Furthermore, a component is understood to be a unit of at least one execution unit which are interconnected in a fixed manner and consequently work together in a fixed mode.

A debug support unit is understood as a unit which can influence an execution unit, a component or a subsystem of a plurality of execution units or components and comparators by suitable signals and by other suitable signals information about states and / or processes of the execution units, components, comparators or subsystems returned directly or indirectly and so that they are observable by the debug support unit. A general case of the switching and comparison component, also for use in processor systems having more than two execution units, is shown in FIG. Of the n execution units to be considered, n signals N 140,..., Nl 4n go to the switching and comparison component N100. This can generate up to n output signals N160, ..., N16n from these input signals. In the simplest case, the "pure performance mode", all signals N14i are directed to the corresponding output signals N16i. In the opposite limit case, the "pure comparison mode", all signals N140, ..., N14n are directed to only one of the output signals N16i ,

This figure shows how the various conceivable modes can arise. For this purpose, the logical component of a switching logic Nl 10 is included in this figure. This first determines how many output signals there are. Furthermore, the switching logic Nl 10 determines which of the input signals contribute to which of the output signals. An input signal can contribute to exactly one output signal. In other words, in mathematical form, a function is defined by the switching logic, which assigns an element of the set {N160, ..., N16n} to each element of the set {N140, ..., N14n}.

The processing logic N 120 then determines to each of the outputs N16i how the inputs contribute to that output signal. By way of example, to describe the various possible variations, it is assumed without loss of generality that the output N 160 is generated by the signals N141, ..., N 14m. If m = 1, this simply means that the signal is switched through, if m = 2 then the signals N141, N 142 are compared. This comparison can be performed synchronously or asynchronously, it can be performed bitwise or only on significant bits or even with a tolerance band. If m> = 3, there are several possibilities.

A first possibility is to compare all signals and to detect an error in the presence of at least two different values, which can be optionally signaled.

A second possibility is to make a k out of m selection (k> m / 2). This can be realized by using comparators. Optionally, an error signal can be generated if one of the signals is detected as deviating. A possible As different error signal can be generated when all three signals are different.

A third possibility is to supply these values to an algorithm. This may be, for example, the formation of an average, a median, or the use of a Fault Tolerant Algorithm (FTA). Such an FTA is based on sweeping out extreme values of the input values and prioritizing one way of averaging over the remaining values. This averaging can be done over the entire set of residual values, or preferably over a subset that is easy to form in HW. In this case, it is not always necessary to actually compare the values. For example, averaging only adds and divides, FTM, FTA, or median require partial sorting. If necessary, an error signal can optionally also be output at sufficiently large extreme values

These various possibilities of processing a plurality of signals into one signal are referred to as comparison operations for the sake of brevity.

The task of the processing logic is thus to determine the exact shape of the comparison operation for each output signal - and thus also for the associated input signals. The combination of the information of the switching logic Nl 10 (i.e., the above mentioned function) and the processing logic (i.e., the determination of the comparison operation per output signal, i.e., per function value) is the mode information and sets the mode. This information is of course multivalued in the general case, i. not just a logical bit. Not all the theoretically conceivable modes are meaningful in a given implementation, it will be preferred to limit the number of allowed modes. It should be emphasized that in the case of only two execution units, where there is only one compare mode, all the information can be condensed to only one logical bit.

Switching from a performance mode to a comparison mode is characterized in the general case by the fact that execution units that are displayed in the performance mode on different outputs are mapped in the compare mode to the same output. This is preferably realized in that there is a subsystem of execution units in which in the performance mode all input signals N14i which are to be executed in the subsystem have to be switched directly to corresponding output signals N16i, while they are all mapped to an output in comparison mode. Alternatively, such switching can also be realized by changing pairings. It is represented by the fact that in the general case one can not speak of the performance mode and the equilibrium mode, although in a given form of the invention one can limit the set of allowed modes such that this is the case. However, one can always speak of switching from the performance to the comparison mode (and vice versa).

The error logic N130 collects the error signals and can optionally passively switch outputs N16i, for example, by interrupting them via a switch.

The mode signal is shown in a general form in FIG. The signals and components N10, N120, N130, N140, N141, N142, N143, N14n, N160, N161, N162, N163, N16n of the switching and comparison component N200 have the same meaning as in the switching and comparison component N100 in FIG FIG. 5. In addition, the mode signal Nl 50 and the error signal N 170 are shown in this figure. The optional error signal is generated by fault circuit logic N130, which collects the error signals, and is either a direct forwarding of the single error signals or a bundling of the error information contained therein. The mode signal Nl 50 is optional, but its use outside of this component can be used to advantage in many places. The combination of the information of the switching logic NI 10 (ie the above mentioned function) and the processing logic (ie the determination of the comparison operation per output signal, ie per function value) is the mode information and sets the mode. Of course, in the general case this information is multivalued, ie not representable only via a logical bit. Not all theoretically conceivable modes are meaningful in a given implementation, it will be preferable to restrict the ZaIi of the allowed modes. The mode signal then brings the relevant mode information to the outside. An HW implementation is preferably shown so that the externally visible mode signal can be configured. Preferably, the processing logic and circuitry are also configured to be configurable. Preferably, these configurations are coordinated. Alternatively, one can give only or additionally changes of the mode signal to the outside. This has advantages especially in a two-configuration. The following mainly describes a system with two execution units. FIG. 1 shows a two-processor system. If the two-processor system is in a performance mode, different instructions, program segments or programs are calculated on the various execution units G 140a and G 140b in accordance with this mode. The coupling between the processors is given only loosely. In this case, the execution units G140a and G140b are preferably "debugged" via the debug support units GlOOa and GOOOOb and via the debug interfaces G 120a and G 120b, where the execution unit G 140a is debugged via the debug interface G120a and the debug support unit GlOOa. " debugged ". The execution unit G140b is "debugged" via the debug interfaces G 120b and the debug support units GlOOb This means that via these units and via other communication devices not shown, the internal states, in particular internal registers of the execution units, an external program (a so-called "debugger"), which is processed on a so-called host computer, are transmitted. This is done in accordance with the nature of "debugging" during execution of programs on the "debug" execution units G140a, G140b. The debugger, in accordance with the general operation of a "debugger", besides monitoring states, is also capable of determining the internal states of the "debug" execution units G 140a and G 140b via the interfaces G 120a and G 120b as well as the debugger. Support units GlOOa and GlOOb to change, stop this, or after a stop, this again to start again.

In the compare mode, the execution units G 140a and G 140b in a preferred variant process the same commands clock-synchronously or with a defined clock offset. The output signals of execution units G 140a and G 140b are compared in accordance with the comparison mode. If these signals differ, an error is detected. In this mode, if there is a change in the internal states or execution units G 140a and G 140b are stopped via one of the debug support units GlOOa and GlOOb, an error is detected by the comparator (not shown in the figure). In this case, it is preferable to "debug" the execution units G 140a and G 140b via the debug support units G10 and the debug interfaces G130a and G130b, with the execution unit G140a via the debug interface G130a, and the execution unit G 140b via the Debug interfaces G 130b from debug support units Gl 10 "Debug". The debug support unit Gl 10 is in capable of simultaneously displaying the states of the two execution units G140a and G140b. It can also change states at the same time, stop or restart the execution units. In this case, the execution units G 140a and G 140b also behave synchronously during an intervention for debugging reasons, so that there is no difference that the comparator recognizes.

This suggestion is based on the conceptual idea that in a two-processor system, which can switch between a performance and a comparison mode during operation, there are three separate units to be "debugged." In performance mode, execution units G 140a and Eq 40b are to be regarded as separate execution units, in the compare mode the synchronous operation of these two execution units is to be treated as a logical execution unit Gl 50. According to this concept, a separate debug support unit Gl 10 is used for the logical execution unit G 150. These debug support units Gl 10 is able to simultaneously influence the two physical execution units G 140a and G 140b via the debug interface G130a and G130b and to make the states of these available to an external program ("debugger").

In a generalization of the example of Figure 1, each of the execution units G 140a and G 140b may also be implemented as a component that includes a plurality of execution units that are fixedly interconnected and cooperate with each other in a particular mode (eg, a compare mode). This component does not fundamentally differ from an execution unit with respect to the input and output signals, but optionally outputs only additional signals, such as an error or several status signals, and possibly has additional input signals for test purposes. Such a component can also replace an execution unit in all following variants.

In an extension, as shown in the drawings Figure 2, Figure 3, Figure 4, in addition to the debug support unit Gl 10, a debug support management unit G 170 is proposed. FIG. 2 shows the general case, in FIG. 3 the expression in the performance mode is shown in detail, in FIG. 4 the expression in the comparison mode is shown in detail. The Debug Support Management Unit G 170, by hardware, depending on the mode in which the system operates, ensures that only the debug support units are used, which are also useful in this mode. The debug

Support management unit G 170 uses a core mode signal Gl 80 (corresponding to Nl 50 of FIG. 6) supplied by a switching and comparing unit G200 (corresponding to N200 of FIG. 6).

In a preferred implementation, debug support control unit G 170 in performance mode will only allow debugging of execution units G 140a and G 140b using debug support units GlOOa and GlOOb and debug interfaces G120a, G190a and G120b, G190b.

In comparison mode, debug support management unit G 170, on the other hand, allows debugging of logic execution unit G150 only via debug support unit Gl10. Logical execution unit G150 consists of execution units G 140a and G 140b only the debug interfaces G 160 and G 190a for debugging execution unit G 140a, and it uses only the debug interfaces G 160 and G 190b for debugging execution unit G140b.

For the proposed multiprocessor system, a debug mechanism and a debug hardware is proposed, which makes it possible to debug the execution units according to the requirements resulting from the mode (performance or comparison mode). Debugging solutions for a SMP system are known in which the execution units always fulfill different tasks separately from one another, and solutions for systems in pure comparison mode are also known.

The invention described here differs from the prior art in that the debugging mechanisms and the debug hardware and the switching of the execution units in operation are adapted between a performance mode and a comparison mode.

Claims

claims

1. An apparatus for analyzing processes in a computer system having a plurality of execution units which are configurable in at least two different modes in the computer system, wherein at least two execution units operate in a performance mode as a first mode and at least one second mode is provided as a comparison mode and that analysis units, in particular debug support units, are used to analyze states and processes in all execution units, characterized in that the device contains at least one analysis unit more than the maximum number of execution units which operate independently in the performance mode.

2. Device according to claim 1, characterized in that all Ausführungsseiiiieiten which do not cooperate in at least a first mode with other execution units in a comparison mode, each having an analysis unit is assigned, which can observe and / or influence the states and processes in this execution unit.

3. Device according to claim 1, characterized in that the device is designed such that work in at least a second mode of the computer system at least two execution units as a temporary subsystem in a comparison mode and this subsystem is associated with a further analysis unit, the states and procedures observe and / or influence in this subsystem.

4. Device according to one of claims 1 to 3, characterized in that the device is designed such that by at least one mode signal, in particular core mode signal, a switching of the activity of at least one analysis unit takes place.

5. Device according to one of claims 1 to 3, characterized in that the device is designed such that by control signals of at least one analysis unit, a switching of the activity of at least one other analysis unit takes place.

6. The device according to claim 3, characterized in that the device is designed such that a synchronous observation and influencing of the states and processes of all execution units of the subsystem, which cooperates in a comparison mode, by the analysis unit is possible.

7. Device according to one of claims 1 to 3, characterized in that additional means are included, which enable activation and / or deactivation of analysis units depending on the operating modes of the computer system and / or further specifiable conditions.

8. The device according to claim 3, characterized in that the device is configured such that in a comparison mode of a subsystem, the subsystem associated with the analysis unit is active and the analysis units of the subsystem associated execution units are not active.

9. Device according to claim 4 or 5, characterized in that additionally states or individual input signals of the execution units and / or the comparison means can be influenced by at least one analysis unit and the states or output signals of these influenced units can be observed by this or another analysis unit.

10. Computer system with a device according to one of claims 1 to 9.

11. A method for analyzing processes in a computer system having a plurality of execution units that can be configured in at least two different modes in the computer system, wherein at least two execution units operate in a performance mode as a first mode and at least one second mode is provided as a comparison mode and that for the observation and / or influencing of states and processes in all execution units analysis units, in particular debug Support units, characterized in that the device contains at least one analysis unit more than the maximum number of Ausfüh- tion units that operate independently of each other in the performance mode, the analysis units can observe and / or influence the states and processes in the execution units.

12. The method according to claim 11, characterized in that all execution units, which do not cooperate with other execution units in a comparison mode in at least one first mode, are each assigned an analysis unit which can observe and / or influence the states and processes in this execution unit.

13. The method according to claim 11, wherein in at least one second mode of the computer system, at least two execution units work together as a temporary subsystem in a compare mode, and that subsystem is assigned a further analysis unit which monitors the states and processes in that subsystem and / or can influence.

14. The method according to any one of claims 11 to 13, characterized in that by at least one mode signal, in particular core mode signal, a switching of the activity of at least one analysis unit takes place.

15. The method according to any one of claims 11 to 13, characterized in that by control signals of at least one analysis unit, a switching of the activity of at least one other analysis unit takes place.

16. The method according to claim 13, characterized in that an observation and / or influencing of the states and processes of all execution units of the subsystem, which cooperates in a comparison mode, takes place synchronously by the analysis unit.

17. The method according to any one of claims 11 to 13, characterized in that an activation and / or deactivation of analysis units is carried out depending on the operating modes of the computer system and / or other predetermined conditions

18. The method according to claim 17, characterized in that the activation and / or deactivation is carried out by means implemented in hardware, which are part of the computer system.

19. Method according to claim 13, characterized in that in a comparison mode of a subsystem, the analysis unit assigned to the subsystem is active and the analysis units of the execution units assigned to the subsystem are not active.

20. The method according to claim 14 or 15, characterized in that additionally states or individual input signals of the execution units and / or the comparison means are influenced by at least one analysis unit and the states or output signals of these influenced units are observable by this or another analysis unit.