JP2009506408A - Method and apparatus for analyzing a process in a computer system having a plurality of execution units - Google Patents

Abstract

Apparatus and method for analyzing processing in a computer system having a plurality of execution units, wherein the execution units are configurable in at least two different drive modes in the computer system, wherein at least two execution units are in a first mode As a comparison mode, at least one second mode is provided as a comparison mode, and an analysis unit, in particular a debug support unit, is used to analyze the state and processing in all execution units. In the apparatus and method, the apparatus comprises at least one analysis unit that is greater than the maximum number of execution units that work independently of one another in performance mode.

Description

(Background technology)
Transient errors caused by alpha particles and cosmic rays are becoming a problem for integrated semiconductor circuits. Due to the reduced structure width, reduced voltage, and increased clock frequency, the voltage peaks caused by alpha particles and cosmic rays increase the probability that the logic value of the integrated circuit will be distorted. As a result, an erroneous calculation result may be generated. Thus, this type of error must be reliably detected, particularly in safety-related systems such as vehicles.

  Redundancy is used in, for example, a vehicle ABS control system where an electronic circuit malfunction must be reliably detected. For example, in the known ABS system, each complete microcontroller is duplicated, and all ABS functions are calculated redundantly and checked against each other. If the result is inconsistent, the ABS system is stopped.

  The microcontroller includes a storage module (for example, RAM, ROM, cache), a core, an input / output interface, and so-called peripheral devices (for example, an A / D converter, a CAN interface). Since storage elements are efficiently monitored by check code (parity or ECC) and peripheral devices are monitored as part of the sensor signal path or actuator signal path in an application specific manner, future redundancy efforts will be This is related to the unique duplication of the microcontroller core.

  This type of microcontroller with at least two integrated cores is also known as a dual core architecture. The two cores execute the same program segment redundantly and in clock synchronization (lockstep mode), the results of the two cores are compared, and an error is found in the comparison of matches. Such a dual-core system configuration is also referred to as a comparison mode.

  Dual core architectures are also used in other applications to improve performance, that is, to improve performance. Since the performance improvement is realized by the two cores executing different programs, different program segments, and different commands, such a setting of the dual core system is also referred to as a performance mode. This type of system is also referred to as a symmetric multiprocessor system (SMP). An evolution of this type of system consists in switching between the two modes by software using access to special addresses and dedicated hardware devices. In the comparison mode, the core output signals are compared with each other. In performance mode, the two cores work as a symmetric multiprocessor system (SMP) and execute different programs, different program segments or different commands. When developing software for a microcontroller (μC), it is necessary to accurately track the effects of a given program step and use a test mode to recognize errors in the software (SW) during development. And the debugging concept is used for that. As a conventional technique, there has been known a debugging concept for software development that is applied to a dual core architecture and that is executed in pure lockstep or pure SMP driving as has been introduced.

  As a prior art, a debugging concept applied to a switchable system is not known. However, especially during testing or error recognition, switching must be considered, so it is necessary to develop a debugging concept that applies to a switchable system.

(Advantages of the invention)
The advantage of the invention according to claim 1 is that it has a plurality of execution units or components, and the plurality of execution units or components can be set to at least two different drive modes (Betriebsmodi) in the computer system (konfigurierbar), In one mode, at least two execution units or components work in performance mode by processing various input signals into various output signals, and in at least one second mode, the same input signal is Analytical units, especially debug support units, work in comparison mode by processing to the same output signal and analyze and / or adjust (Beeinflussung) the state and processing (Ablaeufen) in all execution units or components Used in the computer system There are more analysis units than execution units or components that can work independently of each other in the performance mode, so that the various modes of the system are better monitored (beobachtbar) and adjustable (beeinflussbar) is there.

  Another advantage is that at least one first mode monitors and / or monitors the status and processing in an execution unit or component for all execution units or components that do not cooperate with other execution units or components in comparison mode. Alternatively, an adjustable analysis unit is associated with each.

  Another advantage is that in at least one second mode of the computer system, at least two execution units or components cooperate in comparison mode as a temporary partial system, with respect to the partial system and the state in the partial system and Another analysis unit capable of monitoring and / or adjusting the process is to be associated.

  Another advantage is that synchronized analysis and / or adjustment of the status and processing of all execution units in the partial system, which cooperate in the comparison mode, is performed by the analysis unit.

  Another advantage is that additional means are provided that allow the analysis unit to be activated and / or deactivated according to the drive mode of the computer system and / or other pre-settable conditions.

  Furthermore, it is advantageous that the activity (Aktivitaet) of at least one analysis unit is switched by at least one mode signal, preferably a core mode signal.

  Furthermore, it is advantageous that the activity of at least one other analysis unit is switched by a control signal of at least one analysis unit.

  Furthermore, in the comparison mode of the partial system, an analysis unit associated with the partial system is activated (aktiv), and an analysis unit of a plurality of execution units or components associated with the partial system is deactivated (nicht aktiv) It is effective to be done. Also, additional states or each input signal of a plurality of execution units or components and / or comparison means can be adjusted by at least one analysis unit, and the state or output signal of the unit to be adjusted is the analysis unit or It is advantageous to be able to be monitored and / or adjusted by other analysis units.

  Other advantages and preferred embodiments will be apparent from the claims and the description.

(Description of Embodiment)
In the following, an execution unit is a processor, core, CPU, FPU (Floating Point Unit), DSP (Digital Signal)
Processor, coprocessor or ALU (Arithmetic Logical Unit). Furthermore, a component means a unit consisting of at least one execution unit that is connected to each other in a defined manner and thus cooperates in a defined mode.

  A debug support unit can be an execution unit, a component, or a partial system consisting of multiple execution units or components, and a comparator that can be adjusted (beeinflussen) with an appropriate signal. A unit that indirectly or directly collects information about the state and / or processing (Ablaeufe) of the vessel or sub-system, so that these can be monitored by the debug support unit.

  A general switching and comparison component is shown in FIG. 5 for use in a processor system having more than two execution units. N input signals N140,..., N14n from n execution units to be considered are routed to the switching and comparison component N100. This component can generate output signals N160,..., N16n from these input signals to n. In the simplest case, in the “pure performance mode” all input signals N14i are routed to the corresponding output signal N16i. In contrast, in the “pure comparison mode” all input signals N140,..., N14n are routed to one of the output signals N16i.

  FIG. 5 shows a method for forming various possible modes. Therefore, in FIG. 5, a switching logic N110 is provided as a logical component. This switching logic first determines the number of output signals. Furthermore, the switching logic N110 determines the relationship between the input signal and the output signal. In this case, the input signal can be involved in one output signal. Therefore, when expressed in a mathematical form, the switching logic defines a function (Funktion) that associates each element of the set {N140,..., N14n} with each element of the set {N160,.

  Thereafter, processing logic N120 determines how the input signal is involved in each output signal N16i. For example, to describe the possibilities of various variants, assume that the output signal N160 is generated by the input signals N141,..., N14m without compromising universality. When m = 1, it simply means a signal passing connection, and when m = 2, the input signals N141 and N142 are compared. This comparison can be performed synchronously or asynchronously, and can be performed on a bit-by-bit basis or significant bits only, or with tolerance. If m> = 3, there are multiple possibilities.

  The first possibility is to compare all signals and detect an error when there are at least two different values, and the error can be selectively notified.

  The second possibility is to make a selection from m to k (k> m / 2). This can be achieved by using a comparator. Optionally, an error signal can be generated if one of the signals is recognized as having a deviation. If all three signals are different, different error signals can also be generated.

  A third possibility is to supply these values to the algorithm. This means, for example, the generation of an average value, a median value, and the use of an algorithm (FTA) that allows errors. This type of FTA is based on rejecting extreme values of input values and performing a kind of averaging process on the remaining values. This averaging process may target all of the remaining values or some values that are easily generated in hardware (HW). In this case, it is not always necessary to actually compare the values themselves. When the average value is generated, for example, addition and division may be performed, and when the FTM, FTA, or median value is generated, a partial classification process is required. Again, if the extreme value is very large, an error signal may be selectively output.

  The various possibilities of processing a plurality of signals as described above into one signal are abbreviated as comparison operations.

  The task of the processing logic is therefore to accurately determine the mode of the comparison operation for each output signal—and for the accompanying input signal. The mode information for determining the mode is composed of a combination of information of the switching logic N110 (the function (Funktion) described above) and the processing logic (for determining the comparison operation for each output signal, and hence for each function value (Funktionswert)). This information is generally multilevel and cannot be represented by one logical bit. In any implementation, not all theoretically envisioned modes are important and preferably the number of modes allowed is limited. It should be emphasized that if there are two execution units and thus only one comparison mode, the mode information can be represented by one logical bit.

  Switching from performance mode to comparison mode is generally characterized in that execution units that are mapped to different outputs in performance mode are mapped to the same output in comparison mode. This is because there is a partial system of execution units in which in the performance mode all input signals N14i to be considered by the partial system are directly routed to the corresponding output signal N16i, and in the comparison mode It is preferably realized by mapping to one output. This type of switching may alternatively be realized by changing the pairing. In the embodiment of the present invention, the allowed modes are limited to the performance mode and the comparison mode, but in a general case, the allowed modes are not limited to these modes. However, even in the general case, switching from the performance mode to the comparison mode (or from the comparison mode to the performance mode) occurs.

  The error switching logic N130 collects error signals, and can selectively switch the output signal N16i selectively, for example, by interrupting with a switch.

  FIG. 6 shows the mode signal in a general format. The signals and components N110, N120, N130, N140, N141, N142, N143, N14n, N160, N161, N162, N163, N16n of the switching and comparison unit N200 are the same as those of the switching and comparison component N100 shown in FIG. It is. Further, FIG. 6 shows a mode signal N150 and an error signal N170. The selective error signal is generated by an error switching logic N130 that aggregates error signals, and directly leads each error signal to the next, or aggregates error information included in each error signal. The mode signal N150 is optional and can be used effectively outside this component. The mode information for determining the mode is a combination of information of the switching logic N110 (the function described above) and the processing logic (determining the comparison operation for each output signal and thus for each function value). This information is generally multivalued and cannot be represented by only one logical bit. In a given implementation, not all theoretically assumed modes are important, and preferably the number of modes allowed is limited. In this case, the mode signal brings important mode information to the outside. The hardware (HW) implementation is preferably configured such that a mode signal visible externally can be set. Preferably, the processing logic and the switching logic are formed so as to be set similarly. Preferably, these configurations are harmonized with each other. Alternatively, the change of the mode signal can be provided externally, either alone or supplementarily. This has an advantage especially in a dual configuration.

  In the following, a system having two execution units will be mainly described. FIG. 1 shows a dual processor system. When the dual processor system is in performance mode, different commands, program segments or programs are executed on different execution units G140a, G140b. The coupling between the processors is in a loose state. In this case, the execution units G140a, G140b are preferably “debugged” by the debug support units G100a, G100b via the debug interfaces G120a, G120b. Here, the execution unit G140a is “debugged” by the debug support unit G100a via the debug interface G120a. The execution unit G140b is “debugged” by the debug support unit G100b via the debug interface G120b. This means that these units and other components not shown convey the internal state of the execution unit, especially the internal registers, to an external program (so-called “debugger”) that is processed on the so-called host computer. Yes. This is done during processing of the program on the execution units G140a, G140b to be “debugged” based on the characteristics of “debugging”. Based on the general functions of the “debugger”, the debugger monitors the internal state of the execution units G140a and G140b to be “debugged” by the debug support units G100a and G100b via the interfaces G120a and G120b. You can change them, stop them, or restart them after stopping.

  In the comparison mode, the execution units G140a and G140b process the same command in clock synchronization or with a predetermined clock offset in a preferred modification. The output signals of the execution units G140a and G140b are compared according to the comparison mode. If these signals are different, an error is recognized. In this mode, when the internal state is changed or the execution units G140a and G140b are stopped by one of the debug support units G100a and G100b, an error is recognized by a comparator (not shown). In this case, preferably, the “debugging” of the execution units G140a and G140b is performed by the debug support unit G110 via the debug interfaces G130a and G130b. In this case, the execution unit G140a is “debugged” by the debug support unit G110 via the debug interface G130a and the execution unit G140b via the debug interface G130b. For this reason, the debug support unit G110 can display the states of the two execution units G140a and G140b at the same time. The debugging support unit can simultaneously change the internal state and stop or restart the execution unit. In this case, since the execution units G140a and G140b act synchronously even during the intervention for debugging purposes, there is no difference recognized by the comparator.

  Therefore, this proposal is based on the concept that three units to be “debugged” each become a problem in a dual processor system capable of switching between the performance mode and the comparison mode when driven. In this case, in the performance mode, the execution units G140a and G140b are handled as separate execution units, and in the comparison mode, the synchronized driving of these two execution units is handled as one logical execution unit G150. Based on this concept, another debug support unit G110 is used for the logical execution unit G150. In this case, the debug support unit G110 can simultaneously adjust the two physical execution units G140a and G140b via the debug interfaces G130a and G130b and provide these states to an external program (“debugger”).

  In the general example shown in FIG. 1, each of the execution units G140a and G140b can be formed as a component having a plurality of execution units, and the plurality of execution units are fixedly connected to each other. Cooperate with each other in a mode (eg, comparison mode). This component is in principle indistinguishable from the execution unit in terms of input / output signals and in some cases only outputs additional signals, such as error signals or multiple status signals, and in some cases additional test signals. Input signal. This type of component can be replaced with an execution unit in the following modifications.

  In the expansion shown in FIGS. 2, 3, and 4, a debug support management unit G170 is proposed in addition to the debug support unit G110. In this case, FIG. 2 shows a general case, FIG. 3 shows a case in the performance mode in detail, and FIG. 4 shows a case in the comparison mode in detail.

  The debug support management unit G170 ensures that only the debug support unit that is significant in the mode is used according to the mode in which the system is working, via hardware. For this purpose, the debug support management unit G170 uses a core mode signal G180 (corresponding to N150 in FIG. 6) supplied from the switching and comparison unit G200 (corresponding to N200 in FIG. 6).

  In a preferred implementation, the debug support management unit G170 allows only “debugging” of the execution units G140a, G140b in the performance mode. For this purpose, the debug support management unit uses the debug support units G100a and G100b and the debug interfaces G120a and G190a and G120b and G190b.

  On the other hand, the debug support management unit G170 permits only “debugging” of the logical execution unit G150 by the debug support unit G110 in the comparison mode. In this case, the logical execution unit G150 includes execution units G140a and G140b. In this case, the debug support unit G110 uses only the debug interfaces G160 and G190a to debug the execution unit G140a, and uses only the debug interfaces G160 and G190b to debug the execution unit G140b.

  In a multiprocessor system, a debugging mechanism and debugging hardware are proposed that allow debugging of execution units depending on the characteristics of the mode (performance mode or comparison mode). A debugging method for an SMP system in which a plurality of execution units are separated to process different tasks is known. Similarly, a debugging method for a system that functions in a pure comparison mode is also known.

  In this case, the above-described invention is different from the prior art in that the debugging mechanism and the debugging hardware can be adapted to the drive switching of the execution unit between the performance mode and the comparison mode.

It is a block diagram showing a multiprocessor system having two execution units G140a and G140b, attached analysis units, in particular, debug support units G100a and G100b, and a debug support unit G110. FIG. 2 is a block diagram showing a multiprocessor system having two execution units G140a and G140b, attached analysis units, in particular, debug support units G100a and G100b, and a debug support unit G110, and includes a debug support management unit G170, a switching and comparison unit G200. It is shown. FIG. 3 is a block diagram showing a multiprocessor system having two execution units G140a and G140b, attached debug support units G100a and G100b, and a debug support unit G110, and shows a debug support management unit G170 and a switching and comparison unit G200. Yes. The system is working in performance mode. FIG. 3 is a block diagram showing a multiprocessor system having two execution units G140a and G140b, attached debug support units G100a and G100b, and a debug support unit G110, and shows a debug support management unit G170 and a switching and comparison unit G200. Yes. The system is working in comparison mode. FIG. 6 is a block diagram illustrating a general switching and comparison component for using more than two execution units. It is a block diagram which shows a mode signal in a general format.

Claims (20)

An apparatus for analyzing processing in a computer system having a plurality of execution units, wherein the execution units can be set in at least two different drive modes in the computer system, and at least two execution units are in a first mode. And at least one second mode is provided as a comparison mode, and an analysis unit, in particular a debug support unit, is used to analyze the state and processing in all execution units, In the device,
An apparatus for analyzing processing in a computer system having a plurality of execution units, comprising at least one analysis unit that is greater than a maximum number of execution units that work independently from each other in the performance mode.   In each of the at least one first mode, an analysis unit that can monitor and / or adjust the state and processing in the execution unit is associated with each execution unit that does not cooperate with other execution units in the comparison mode. The apparatus of claim 1, wherein the apparatus is configured to be configured.   In at least one second mode, at least two execution units can cooperate in a comparison mode as a temporary partial system and can monitor and / or adjust the status and processes in the partial system with respect to the partial system. The apparatus according to claim 1, wherein the apparatus is configured to be associated with another analysis unit.   Device according to any of the preceding claims, characterized in that the activity of at least one analysis unit is switched by at least one mode signal, in particular a core mode signal.   The device according to claim 1, wherein the activity of at least one other analysis unit is switched by a control signal of at least one analysis unit.   6. The synchronization unit is configured to allow synchronized monitoring and / or adjustment of the status and processing of all execution units in the partial system working in comparison mode. 3. The apparatus according to 3.   An additional means is provided for enabling the analysis unit to be activated and / or deactivated according to the driving mode of the computer system and / or other presettable conditions. Item 4. The apparatus according to any one of Items 1 to 3.   In the partial system comparison mode, the analysis unit associated with the partial system is activated, and the analysis unit of the execution unit associated with the partial system is deactivated. The apparatus according to claim 3.   The additional state or each input signal of the execution unit and / or the comparison means is adjustable by at least one analysis unit, and the state or output signal of the adjusted unit is the at least one analysis unit or 6. Device according to claim 4 or 5, characterized in that it can be monitored by another analysis unit.   A computer system comprising the apparatus according to claim 1. A method for analyzing processing in a computer system having a plurality of execution units, wherein the execution units can be set to at least two different drive modes in the computer system, and at least two execution units are in a first mode. As a comparison mode, and at least one second mode is provided as a comparison mode, and a plurality of analysis units, in particular debugging aids, to monitor and / or adjust the state and processing in all execution units In the method, wherein a unit is used,
More than the maximum number of the execution units working independently of each other in the performance mode, the analysis unit being able to monitor and / or adjust the status and processes in the execution units A method for analyzing processing in a computer system having a plurality of execution units, characterized in that the apparatus is used.   In at least one first mode, an analysis unit that can monitor and / or adjust the status and processes in the execution unit is associated with each execution unit that does not cooperate with other execution units in the comparison mode. The method of claim 11, wherein:   In at least one second mode, at least two execution units cooperate in comparison mode as a temporary partial system and can monitor and / or adjust the status and processes in the partial system relative to said partial system The apparatus according to claim 11, wherein other analysis units are associated.   14. Method according to any of claims 11 to 13, characterized in that the activity of at least one analysis unit is switched by at least one mode signal, in particular a core mode signal.   14. The method according to any of claims 11 to 13, characterized in that the activity of at least one other analysis unit is switched by a control signal of at least one analysis unit.   14. The method according to claim 13, characterized in that monitoring and / or adjustments relating to the state and processing of all execution units in the partial system that cooperate in comparison mode are performed synchronously by the analysis unit.   14. Activation and / or deactivation of an analysis unit is performed according to the drive mode and / or other presettable conditions of the computer system. Method.   18. A method according to claim 17, characterized in that the activation and / or deactivation is performed by means implemented in hardware and part of a computer system.   14. The analysis unit associated with the partial system is activated and the analysis unit of the execution unit associated with the partial system is deactivated in the comparison mode of the partial system. The method described in 1.   Additional states or each input signal of the execution unit and / or the comparison means are adjusted by at least one analysis unit, and the state or output signal of the adjusted unit is monitored by the analysis unit or other analysis units 16. Method according to claim 14 or 15, characterized in that it is possible.

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