WO2007017363A1 - Procede et dispositif de commutation dans un systeme de calcul comprenant au moins deux unites d'execution au moyen d'informations binaires dans un registre - Google Patents

Procede et dispositif de commutation dans un systeme de calcul comprenant au moins deux unites d'execution au moyen d'informations binaires dans un registre Download PDF

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Publication number
WO2007017363A1
WO2007017363A1 PCT/EP2006/064511 EP2006064511W WO2007017363A1 WO 2007017363 A1 WO2007017363 A1 WO 2007017363A1 EP 2006064511 W EP2006064511 W EP 2006064511W WO 2007017363 A1 WO2007017363 A1 WO 2007017363A1
Authority
WO
WIPO (PCT)
Prior art keywords
register
switching
bit
mode
bit information
Prior art date
Application number
PCT/EP2006/064511
Other languages
German (de)
English (en)
Inventor
Reinhard Weiberle
Bernd Mueller
Eberhard Boehl
Yorck Collani
Rainer Gmehlich
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Publication of WO2007017363A1 publication Critical patent/WO2007017363A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components

Definitions

  • the invention relates to a method and a device for switching between at least two operating modes of a microprocessor having at least two execution units for processing program segments according to the preambles of the independent claims.
  • Dual-core or multi-core architectures are also used in other applications to increase performance, ie to increase performance. Both cores run different program segments, which can achieve a performance improvement compared to the comparison mode or a single core system. This configuration is called
  • This system is also referred to as a symmetrical multiprocessor system (SMP) in a special form with the same cores.
  • SMP symmetrical multiprocessor system
  • Modes of accessing a specific address and specialized hardware devices In comparison mode, the output signals of the cores are compared with each other. In performance mode, the two cores work as a symmetric multiprocessor (SMP) system and execute different programs, program segments, or commands.
  • SMP symmetric multiprocessor
  • the object of this invention is therefore not to cause the switching by a special instruction or the access to a specific address, but to cause a switching when certain bits are manipulated or written in one or more internal registers of the processor. If there is a register in the processor, regardless of the possibility of switching between a performance mode and a comparison mode, in which not all bits are assigned a meaning, no special instructions are required in the instruction set. An example of this is the processor status register, which is commonly available in each processor and for each execution unit of a processor stands. Instructions with which this register can be read and set are then present in the instruction set. Therefore, no new instructions for a processor need to be defined to toggle between performance mode and compare mode.
  • the switching is triggered by at least one bit information in a register.
  • the bit information is advantageously generated by a command already present in an instruction set of the computer system.
  • the bit information is generated by setting at least one bit in a register.
  • the bit information is generated by deleting at least one bit in a register.
  • the bit information is generated in a register located in the execution unit.
  • a predeterminable data word is written into the register and the bit information is generated in that at least one predeterminable bit corresponds to a specifiable information.
  • at least one specifiable bit in the predefinable data word is set / deleted.
  • the switching is characterized in that a register is included and second means are included, which trigger the switching by at least one bit information in this register.
  • the register is located within an execution unit.
  • the register is the processor status register or the instruction register or the instruction counter register.
  • FIG. 1 shows a system G60 with two execution units GlOa and GlOb, which each contain a register Gl Ia or Gl Ib with the width k + 1.
  • FIG. 2 shows such a register Gl 1 in an execution unit GlO
  • the invention relates to a multi-processor system (G60) shown in FIG. 1 with at least two execution units (GlOa, GlOb), a comparison unit (G20), a switching unit (G50) and a unit for
  • the switching unit (G50) has at least two outputs to two system interfaces (G30a, G30b). Registers, memories or peripherals such as digital outputs, D / A converters and communication controllers can be controlled via these interfaces.
  • This multiprocessor system can be operated in at least two modes of operation, a compare mode (VM) and a performance mode (PM).
  • the comparison unit (G20) is deactivated.
  • the deactivation can be realized in various ways:
  • a comparison by the unit G20 is not performed.
  • the switching unit (G50) is configured in this operation mode so that each execution unit is connected to a system interface (G30a, G30b).
  • the output signals of the execution units (GlOa, GlOb) are compared in the comparison unit (G20). If there is a difference, an error is detected and suitable measures can be taken.
  • the switching unit (G50) is configured in a variation such that only one signal is connected to the system interfaces (G30a, G30b). In another configuration, the switching unit only causes the compared and thus the same signals to be connected to the system interfaces (G30a, G30b).
  • the switchover request detection (G40) detects a switchover to the other mode regardless of the currently active mode.
  • FIG. 2 shows an execution unit GlO.
  • Gl 1 is a register with k + 1 bits in an execution unit GlO.
  • commands with which the bits in this
  • Register could be manipulated or written directly or indirectly.
  • one or more bits are reserved in the register GIII for triggering the switchover.
  • the unit G40 detects a switchover request when the reserved bits in the register Gl 1 are set to a specific bit pattern.
  • the mode of the processor thus depends on which bit pattern these reserved bits are set in the register GI l.
  • one or more bits are reserved in the register GI 1 for triggering the switching.
  • the unit G40 detects a switchover to the comparison mode when the register GI 1 is written with a value at which the correspondingly reserved bits are assigned a specific bit pattern.
  • the unit G40 detects a switchover to the performance mode when the register GI 1 is written with a value in which the corresponding reserved bits are assigned a specific bit pattern.
  • the bit pattern for switching to the comparison mode need not necessarily be different from the bit pattern for switching in the performance mode.
  • the bit patterns can be identical or different.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

L'invention concerne un procédé de commutation dans un système de calcul comprenant au moins deux unités d'exécution, selon lequel la commutation est effectuée entre au moins deux modes de fonctionnement, un premier mode de fonctionnement correspondant à un mode de comparaison et un deuxième mode de fonctionnement correspondant à un mode de performance. L'invention est caractérisée en ce que la commutation est déclenchée par au moins une information binaire dans un registre.
PCT/EP2006/064511 2005-08-08 2006-07-21 Procede et dispositif de commutation dans un systeme de calcul comprenant au moins deux unites d'execution au moyen d'informations binaires dans un registre WO2007017363A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE200510037260 DE102005037260A1 (de) 2005-08-08 2005-08-08 Verfahren und Vorrichtung zur Umschaltung bei einem Rechnersystem mit wenigstens zwei Ausführungseinheiten mittels Bitinformationen in einem Register
DE102005037260.0 2005-08-08

Publications (1)

Publication Number Publication Date
WO2007017363A1 true WO2007017363A1 (fr) 2007-02-15

Family

ID=37433850

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2006/064511 WO2007017363A1 (fr) 2005-08-08 2006-07-21 Procede et dispositif de commutation dans un systeme de calcul comprenant au moins deux unites d'execution au moyen d'informations binaires dans un registre

Country Status (2)

Country Link
DE (1) DE102005037260A1 (fr)
WO (1) WO2007017363A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6615366B1 (en) * 1999-12-21 2003-09-02 Intel Corporation Microprocessor with dual execution core operable in high reliability mode
US6640313B1 (en) * 1999-12-21 2003-10-28 Intel Corporation Microprocessor with high-reliability operating mode
DE10349581A1 (de) * 2003-10-24 2005-05-25 Robert Bosch Gmbh Verfahren und Vorrichtung zur Umschaltung zwischen wenigstens zwei Betriebsmodi einer Prozessoreinheit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6615366B1 (en) * 1999-12-21 2003-09-02 Intel Corporation Microprocessor with dual execution core operable in high reliability mode
US6640313B1 (en) * 1999-12-21 2003-10-28 Intel Corporation Microprocessor with high-reliability operating mode
DE10349581A1 (de) * 2003-10-24 2005-05-25 Robert Bosch Gmbh Verfahren und Vorrichtung zur Umschaltung zwischen wenigstens zwei Betriebsmodi einer Prozessoreinheit

Also Published As

Publication number Publication date
DE102005037260A1 (de) 2007-02-15

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