WO2007001255A1

WO2007001255A1 - Integrated relaxation voltage controlled oscillator and method of voltage controlled oscillation

Info

Publication number: WO2007001255A1
Application number: PCT/US2005/021089
Authority: WO
Inventors: Robert Dixon; Liviu Chiaburu
Original assignee: Freescale Semiconductor, Inc.
Priority date: 2005-06-15
Filing date: 2005-06-15
Publication date: 2007-01-04
Also published as: EP1894299A1; JP2008544641A; JP4902648B2

Abstract

Method and apparatus are provided for integrated relaxation voltage controlled oscillation. An oscillation circuit for transmitting a clock signal is provided comprising a current source (12) having a first input configured to receive a first reference potential and having a second input configured to receive a signal having a pre-determined period, and a voltage controlled oscillator (VCO) (14) coupled to the current source. The current source comprises a first capacitance (CY) and is configured to generate a reference current directly proportional to the first capacitance. The VCO has an input configured to receive the reference current. The VCO comprises a second capacitance (CX) and is configured to generate the clock signal having a period directly proportional to a ratio of the second capacitance to the first capacitance.

Description

INTEGRATED RELAXATION VOLTAGE CONTROLLED OSCILLATOR AND METHOD OF VOLTAGE CONTROLLED OSCILLATION

FIELD OF THE INVENTION

[0001] The present invention generally relates to oscillators, and more particularly relates to oscillation circuits and methods for generating a clock signal having an oscillation frequency with increased reliability.

BACKGROUND OF THE INVENTION

[0002] Oscillators are widely used to generate periodic waveforms (e.g., waveforms occurring at a frequency of oscillation) for a variety of applications. The frequency of oscillation for an oscillator circuit is typically a function of an oscillator capacitor utilized therein, and the performance of this oscillator capacitor may be influenced by the manufacturing process and by environmental temperatures. For example, a capacitor may have variations in performance due to variations in physical dimensions that may have occurred during fabrication.

[0003] One approach to compensate for possible process variations of the oscillator capacitor is to use a Resistor-Capacitor (RC) oscillator. The RC oscillator achieves process compensation using a voltage divider in a current generator circuit that tracks the process variations of the RC oscillator. A similar approach to process compensation is used in a Voltage Controlled Oscillator (VCO) having circuitry that tracks the difference between a stable and process independent current and a current that varies with the process. Each of these approaches typically assumes that different components are affected by the process in a similar manner. In actuality, different components generally have process variations that poorly track one another, and thus any conventional process compensation is available for a limited and narrow frequency range.

[0004] To expand the frequency range of process compensation in these approaches, a digital phase locked loop has been used to generate a range of frequencies. In practice, the operating frequency range of the VCO is typically larger than the expanded frequency range due to process-related variations of the oscillator capacitor. To account for such larger operating frequency range, the digital-to-analog converter of the digital phase locked loop operates with a greater voltage range having increased voltage steps, and the increased voltage steps reduce the accuracy of any generated frequency from the VCO. To further address this reduced accuracy, the resolution of the digital-to-analog converter may be increased using a more complex circuit design that occupies a greater area and operates with greater power consumption.

[0005] Accordingly, an oscillator circuit is desired having low sensitivity to process variations and temperature. Li addition, a method of voltage controlled oscillation is desired having low sensitivity to process variations and temperature. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and

[0007] FIG. 1 is a schematic diagram of an integrated relaxation voltage controlled oscillator in accordance with an exemplary embodiment of the present invention;

[0008] FIG. 2 is a circuit diagram of the current generator shown in FIG. 1;

[0009] FIG. 3 illustrates waveforms useful in explaining the operation of the current generator shown in FIGS. 1 and 2;

[0010] FIG. 4 is a circuit diagram of the voltage controlled oscillator shown in FIG. 1 ; and

[0011] FIG. 5 is a flow diagram of an exemplary embodiment of a method of voltage controlled oscillation in accordance with the present invention. DETAILED DESCRIPTION

[0012] The following detailed description of the invention is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the invention or the following detailed description.

[0013] Referring to the drawings, FIG. 1 is a schematic diagram of an integrated relaxation voltage controlled oscillator 10 in accordance with an exemplary embodiment of the present invention. The integrated relaxation voltage controlled oscillator 10 comprises a dynamic current generator 12 having first and second inputs, and a voltage controlled oscillator (VCO) 14 having a first input coupled to an output of dynamic current generator 12. The first input of dynamic current generator 12 is configured to receive a first reference potential (e.g., a bandgap voltage) (V_REF), and the second input of dynamic current generator 12 is configured to receive a signal having a pre-determined period (To) or frequency (e.g., a clock signal). Dynamic current generator 12 comprises a capacitance (Cy) and is configured to generate a reference current (I_REF) based on capacitance (Cy), predetermined period (T₀), and first reference potential (VR_EF) and having the relationship

IREF = (CY/ T₀) X V_REF .

VCO 14 is configured to receive the reference current (I_REF) from dynamic current generator 12 via the first input and receive a second reference potential (VIN) via a second input of VCO 14. VCO 14 comprises a capacitance (Cx) and is configured to generate a signal having an oscillation period (T) based on capacitance (Cχ)₅ second reference potential (VI_N), and reference current (I_REF) and having the relationship

Substituting the relationship for reference current (I_REF),

T = 2 x (T₀Z VREF) X (C_x Z Cy) Z lREF .

[0014] From this relationship for oscillation period (T) of the signal generated by VCO 14, the integrated relaxation voltage controlled oscillator 10 is generally process independent and temperature tolerant. For example, variation of the clock signal having pre-determined period (T₀) is typically minimized by a controlled selection of the input timing device or circuit, variation in first reference potential (V_REF) is typically minimized using a generally stable bandgap voltage, variation in second reference potential (V_IN) is typically minimized through a controlled selection of supply voltage devices or circuits, and process variations in capacitances (Cx and Cy) are minimized or offset in the relationship for oscillation period (T).

[0015] FIG. 2 is a circuit diagram of the dynamic current generator 12 shown in FIG. 1. Dynamic current generator 12 comprises a current mirror circuit 20 having a source terminal configured to couple to a third reference potential (Vcc) and having first and second drain terminals, a gain transistor 22 having a drain terminal coupled to the first drain terminal of current mirror circuit 20, an amplifier circuit 24 having a first input configured to receive the first reference potential (V_REF) and having an output coupled to a gate of gain transistor 22, and a switched capacitor network 26 coupled between a second input of amplifier circuit 24 and the second drain terminal of current mirror circuit 20. Capacitance (Cy) has a first electrode coupled to the second drain terminal of current mirror circuit 20 and a second electrode configured to receive a fourth reference potential (e.g., ground). Dynamic current generator 12 is configured to generate reference current (I_REF) at a third drain terminal of current mirror circuit 20.

[0016] In an exemplary embodiment, current mirror circuit 20 comprises a first transistor 30 having a gate and the first drain terminal, a second transistor 32 having a gate coupled to both the gate and the first drain terminal of first transistor 30 and having the second drain terminal, and a third transistor 34 having a gate coupled to the gates of first transistor 30 and second transistor 32 and the first drain terminal of first transistor 30 and having the third drain terminal. Additionally, each of first, second, and third transistors 30, 32, 34 of current mirror circuit 20 has a source terminal configured to receive third reference potential (Vcc). First, second, and third transistors 30, 32, 34 may be bipolar transistors, such as Bipolar Junction Transistors (BJT), P-channel Metal Oxide Semiconductor (PMOS) transistors, N- channel Metal Oxide Semiconductor (NMOS) transistors, and the like, and are preferably PMOS transistors. In addition to producing reference current (I_REF) at the third drain terminal of current mirror circuit 20, dynamic current generator 12 produces reference current (IR_EF) at the second drain terminal of current mirror circuit 20. [0017] Gain transistor 22 has a source terminal configured to receive fourth reference potential (e.g., ground). Gain transistor 22 may be a bipolar transistor, PMOS transistor, NMOS transistor, and the like, and is preferably a NMOS transistor although other types of bipolar transistors may be used.

[0018] Amplifier circuit 24 comprises a differential amplifier 36 having the first and second inputs and the output, and an integration capacitor 38 having a first electrode coupled to both the gate of gain transistor 22 and the output of differential amplifier 36 and having a second electrode coupled to the second input of differential amplifier 36.

[0019] Switched capacitor network 26 comprises a first switch 40 (PlB) having a first terminal coupled to the second drain terminal of current mirror circuit 20 and having a second terminal configured to receive fourth reference potential (e.g., ground), a second switch 42 (Pl) having a first terminal coupled to the second drain terminal of current mirror circuit 20 and having a second terminal, an error transfer capacitor 44 having a first electrode coupled to the second terminal of second switch 42 and having a second electrode configured to receive fourth reference potential (e.g., ground), and a third switch 46 (P2) having a first terminal coupled to the first electrode of error transfer capacitor 44 and a second terminal coupled to the second input of differential amplifier 36.

[0020] FIG. 3 illustrates waveforms useful in explaining the operation of the dynamic current generator 12 shown in FIGS. 1 and 2. Referring to FIGS. 2 and 3, first switch 40 (PlB), second switch 42 (Pl), and third switch 46 (P2) open and close upon receiving a logic one signal (e.g., V_HI) and a logic zero signal (e.g., V_LOW), respectively. Second switch 42 (Pl) is configured to couple/uncouple the first and second terminals of second switch 42 (Pl) at a frequency having pre-determined period (T₀) and further configured to couple/uncouple the second drain terminal of current mirror circuit 20 and the first electrode of error transfer capacitor 44 at a frequency having pre-determined period (To). For example, first switch 40 (PlB) uncouples the second drain terminal of current mirror circuit 20 from fourth reference potential (e.g., ground) at time t_\ and couples the second drain terminal of current mirror circuit 20 from fourth reference potential at time t₂. Second switch 42 (Pl) couples the first and second terminals of second switch 42 (Pl) at time ti and uncouples the first and second terminals of second switch 42 (Pl) at time t₂. Pre-determined period (T₀) represents the integration cycle. [0021] FIG. 4 is a circuit diagram of the voltage controlled oscillator 14 shown in FIG. 1. In addition to capacitance (Cx), VCO 14 comprises a switch network 50 having an output an input coupled to the output of dynamic current generator 12, and an inverter network 52 having an output and having an input coupled to the output of switch network 50. Capacitance (Cx) has a first electrode coupled to the input of inverter network 52 and has a second electrode coupled to the output of the inverter network 52. Switch network 50 is configured to receive reference current (IRE_F) and comprises a first switch 54 (Φ₂) and a second switch 56 (Φi). First switch 54 (Φ₂) has a first terminal configured to receive reference current (I_RE_F) and has a second terminal coupled to the input of inverter network 52, and second switch 56 (Φ^ has a first terminal coupled to the input of inverter network 52 and has a second terminal coupled to the output of dynamic current generator 12. First switch 54 (Φ₂) is configured to couple/decouple the first and second terminals of first switch 54 (Φ₂) at a switching frequency based on oscillation period (T). Second switch 56 (Φ]) is configured to couple/decouple the first and second terminals of second switch 56 (Φ^ at the same frequency as first switch 54 (Φ₂) such that second switch 56 (Φ]) couples the first and second terminals of second switch 56 (Φι) when first switch 54 (Φ₂) decouples the first and second terminals of first switch 54 (Φ₂). Similarly, second switch 56 (Φ]) decouples the first and second terminals of second switch 56 (Φ_\) when first switch 54 (Φ₂) couples the first and second terminals of first switch 54 (Φ₂).

[0022] Switch network 50 provides reference current (IR_EF) to inverter network 52 at the switching frequency based on oscillation period (T). Inverter network 52 comprises a first inverter 60 having an input coupled to the first electrode of capacitance (Cx) and having an output, a second inverter 62 having an output and having an input coupled to the output of first inverter 60, a third inverter 64 having an output and having an input coupled to the output of second inverter 62, and a fourth inverter 66 having an output coupled to the second electrode of capacitance (Cx). First, second, and third inverters 60, 62, 64 each has a first reference input configured to receive third reference potential (Vcc) and has a second reference input configured to couple to fourth reference potential (e.g., ground). Fourth inverter 66 has a first reference input coupled to second reference potential (VIN) and has a second reference potential coupled to the fourth reference potential (e.g., ground). In an exemplary embodiment, first, second, third, and fourth inverters are configured with Complementary Metal-Oxide Semiconductor (CMOS) transistors. [0023] FIG. 5 is a flow diagram of an exemplary embodiment of a method of voltage controlled oscillation in accordance with the present invention. Referring to FIGS. 1 and 5, the method begins at 100. Dynamic current generator 12 generates reference current (I_RE_F) at step 105. Dynamic current generator 12 comprises capacitance (Cy). VCO 14 generates and transmits a clock signal at step 110. VCO comprises capacitance (Cx), and the clock signal has a period directly proportional to a ratio of capacitance (Cx) to capacitance (Cy).

[0024] An oscillation circuit for transmitting a clock signal is provided comprising a current source having a first input configured to receive a first reference potential and having a second input configured to receive a signal having a pre-determined period, and a voltage controlled oscillator (VCO) coupled to the current source. The current source comprises a first capacitance and is configured to generate a reference current directly proportional to the first capacitance. The VCO has an input configured to receive the reference current. The VCO comprises a second capacitance and is configured to generate the clock signal having a period directly proportional to a ratio of the second capacitance to the first capacitance.

[0025] The current source further comprises a current mirror, a gain transistor, an amplifier, and a switched capacitor network. The current mirror has a source terminal configured to couple to a second reference potential and having first, second, and third drain terminals. The current source is configured to generate the reference current at the first drain terminal, and the first capacitance is coupled to the second drain terminal. The gain transistor has a fourth drain terminal coupled to the third drain terminal, a gate, and a source terminal configured to couple to a third reference potential. The amplifier has a first input configured to couple with the first reference potential, a second input, and an output coupled to the gate of the gain transistor. The switched capacitor network is coupled between the second input of the amplifier and the second drain terminal. The current mirror comprises a first transistor having a gate and the first drain terminal, a second transistor having a gate and the second drain terminal, and a third transistor having a gate coupled to the gate of the first transistor and having the third drain terminal. The amplifier comprises an integration capacitor coupled between the gate of the gain transistor and the second input of the amplifier. The first capacitance has a first electrode coupled to the second drain terminal and a second electrode configured to couple with the third reference potential. The switched capacitor network comprises a first switch, a second switch, an error transfer capacitor, and a third switch. The first switch has a first terminal coupled to the second drain terminal and having a second terminal coupled to the third reference potential. The second switch has first and second terminals, and the first terminal of the second switch is coupled to the second drain terminal. The error transfer capacitor has first and second electrodes. The first electrode of the error transfer capacitor is coupled to the second terminal of the second switch, and the second electrode of the error transfer capacitor is coupled to the third reference potential. The third switch has first and second terminals. The first terminal of the third switch is coupled to the first electrode of the error transfer capacitor and the second terminal of the second switch, and the second terminal of the third switch is coupled to the second input of the amplifier. The second switch is configured to couple/decouple the first and second terminals of the second switch at a first pre-determined period and further configured to couple/decouple the second drain terminal and the first electrode of the error transfer capacitor at the first pre-determined period. The first switch is configured to couple the second drain terminal to the third reference potential when the second switch decouples the first terminal of the second switch from the second terminal of the second switch, and decouple the second drain terminal from the third reference potential when the second switch couples the first terminal of the second switch with the second terminal of the second switch.

[0026] The VCO further comprises a switch network and an inverter network. The switch network has an output and has an input coupled to the output of the current generator and is configured to receive the reference current. The inverter network has an output and has an input coupled to the output of the switch network. The second capacitance has a first electrode coupled to the input of the inverter network and has a second electrode coupled to the output of the inverter network. The switch network comprises a first switch and a second switch. The first switch has a first terminal configured to receive the reference current and has a second terminal coupled to the input of the inverter network, and the second switch has a first terminal coupled to the input of the inverter network and has a second terminal coupled to the current source. The first switch is configured to couple the first terminal of the first switch with the second terminal of the first switch at a predetermined frequency. The second switch is configured to couple the first terminal of the second switch with the second terminal of the second switch when the first switch decouples the first terminal of the first switch from the second terminal of the second switch, and decouple the first terminal of the second switch from the second terminal of the second switch when the first switch couples the first terminal of the first switch with the second terminal of the first switch. The inverter network comprises a first inverter having an input coupled to the first electrode of the second capacitance and having an output, a second inverter having an output and having an input coupled to the output of the first inverter, a third inverter having an output and having an input coupled to the output of the second inverter, and a fourth inverter having an output coupled to the second electrode of the second capacitance. Each of the first inverter, the second inverter, and the third inverter has a first reference input coupled to a second reference potential and has a second reference input coupled to a third reference potential. The fourth inverter has a first reference input coupled to a fourth reference potential and has a second reference potential coupled to the third reference potential. Each of the first inverter, the second inverter, the third inverter, and the fourth inverter comprises a complementary metal-oxide semiconductor transistor.

[0027] A method for voltage controlled oscillation is provided comprising generating a reference current from a current generator comprising a first capacitance, and generating a clock signal from a voltage controlled oscillator comprising a second capacitance. The clock signal has a period directly proportional to a ratio of the second capacitance to the first capacitance. The reference current generating step comprises generating the reference current based on a pre-determined time reference (T₀), a first reference voltage (V_REF), and the first capacitance (C_Y). The reference current generating step comprises generating the reference current (I_REF) such that

IREF = (C_Y/ T₀) X VREF •

The reference current generating step comprises converting a first reference voltage to the reference current via a current mirror. The reference current has a frequency based on a predetermined time reference, and the clock signal generating step comprises periodically charging/discharging the second capacitance at the frequency of the reference current. The clock signal generating step comprises generating the clock signal based on the second capacitance (Cx), a first reference voltage (V_IN), and the reference current (IR_EF)- The clock signal generating step comprises generating the clock signal having the period (T) such that

T = I X (T₀ Z VREF) X (CX Z CY) Z IREF .

[0028] While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the exemplary embodiment or exemplary embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope of the invention as set forth in the appended claims and the legal equivalents thereof.

Claims

CLAIMS What is claimed is:

1. An oscillation circuit for transmitting a clock signal, the oscillation circuit comprising: a current source having a first input configured to receive a first reference potential and having a second input configured to receive a signal having a pre-determined period, said current source comprising a first capacitance and configured to generate a reference current directly proportional to said first capacitance; and a voltage controlled oscillator (VCO) coupled to said current source and having an input configured to receive said reference current, said VCO comprising a second capacitance and configured to generate the clock signal having a period directly proportional to a ratio of said second capacitance to said first capacitance.

2. An oscillation circuit according to claim 1, wherein said current source further comprises: a current mirror having a source terminal configured to couple to a second reference potential and having first, second, and third drain terminals, said current source configured to generate said reference current at said first drain terminal, said first capacitance coupled to said second drain terminal; a gain transistor having a fourth drain terminal coupled to said third drain terminal, a gate, and a source terminal configured to couple to a third reference potential; an amplifier having a first input configured to couple with said first reference potential, a second input, and an output coupled to said gate of said gain transistor; and a switched capacitor network coupled between said second input of said amplifier and said second drain terminal.

3. An oscillation circuit according to claim 1, wherein said current source comprise a current mirror having a source terminal configured to couple to a second reference potential, said current mirror comprising: a first transistor having a gate and a first drain terminal, said current source configured to generate said reference current at said first drain terminal; a second transistor having a second drain terminal, said first capacitance coupled to said second drain terminal; and a third transistor having a gate coupled to said gate of said first transistor.

4. An oscillation circuit according to claim 1, wherein said current source comprises an amplifier having a first input configured to couple with said first reference potential, a second input, and an output coupled to said gate of said gain transistor, said amplifier comprising an integration capacitor coupled between said gate of said gain transistor and said second input of said amplifier.

5. An oscillation circuit according to claim 1, wherein said current source comprises a current mirror having a source terminal configured to couple to a second reference potential and having first, second, and third drain terminals, and wherein said first capacitance has a first electrode coupled to said second drain terminal and a second electrode configured to couple with a third reference potential.

6. An oscillation circuit according to claim 2, wherein said switched capacitor network comprises: a first switch having a first terminal coupled to said second drain terminal and having a second terminal coupled to said third reference potential; a second switch having first and second terminals, said first terminal of said second switch coupled to said second drain terminal; an error transfer capacitor having first and second electrodes, said first electrode of said error transfer capacitor coupled to said second terminal of said second switch, said second electrode of said error transfer capacitor coupled to said third reference potential; and a third switch having first and second terminals, said first terminal of said third switch coupled to said first electrode of said error transfer capacitor and said second terminal of said second switch, said second terminal of said third switch coupled to said second input of said amplifier.

7. An oscillation circuit according to claim 6, wherein said second switch is configured to couple/decouple said first and second terminals of said second switch at a first pre-determined period and further configured to couple/decouple said second drain terminal and said first electrode of said error transfer capacitor at said first pre-determined period.

8. An oscillation circuit according to claim 7, wherein said first switch is configured to: couple said second drain terminal to said third reference potential when said second switch decouples said first terminal of said second switch from said second terminal of said second switch; and decouple said second drain terminal from said third reference potential when said second switch couples said first terminal of said second switch with said second terminal of said second switch.

9. An oscillation circuit according to claim 1, wherein said VCO further comprises: a switch network having an output and having an input coupled to said output of said current generator and configured to receive said reference current; an inverter network having an output and having an input coupled to said output of said switch network, said second capacitance having a first electrode coupled to said input of said inverter network and having a second electrode coupled to said output of said inverter network.

10. An oscillation circuit according to claim 1 , wherein said VCO further comprises a switch network having an output and having an input coupled to said output of said current generator and configured to receive said reference current, said switch network comprising: a first switch having a first terminal configured to receive said reference current and having a second terminal coupled to said input of said inverter network; and a second switch having a first terminal coupled to said input of said inverter network and having a second terminal coupled to said current source.

11. An oscillation circuit according to claim 10, wherein said first switch is configured to couple said first terminal of said first switch with said second terminal of said first switch at a pre-determined frequency.

12. An oscillation circuit according to claim 10, wherein said second switch is configured to: couple said first terminal of said second switch with said second terminal of said second switch when said first switch decouples said first terminal of said first switch from said second terminal of said second switch; and decouple said first terminal of said second switch from said second terminal of said second switch when said first switch couples said first terminal of said first switch with said second terminal of said first switch

13. An oscillation circuit according to claim 9, wherein said inverter network comprises: a first inverter having an input coupled to said first electrode of said second capacitance, a first reference input coupled to a second reference potential, a second reference input coupled to a third reference potential, and an output; a second inverter having an input coupled to said output of said first inverter, a first reference input coupled to said second reference potential, a second reference input coupled to said third reference potential, and an output; a third inverter having an input coupled to said output of said second inverter, a first reference input coupled to said second reference potential, a second reference input coupled to a third reference potential, and an output; and a fourth inverter having an input coupled to said output of said third inverter, a first reference input coupled to a fourth reference potential, a second reference potential coupled to said third reference potential, and an output coupled to said second electrode of said second capacitance.

14. A method for voltage controlled oscillation comprising the steps of: generating a reference current from a current generator comprising a first capacitance; and generating a clock signal from a voltage controlled oscillator comprising a second capacitance, the clock signal having a period directly proportional to a ratio of the second capacitance to the first capacitance.

15. A method according to claim 14, wherein said reference current generating step comprises generating the reference current based on a pre-determined time reference (To), a first reference voltage (V_REF), and the first capacitance (Cy).

16. A method according to claim 15, wherein said reference current generating step comprises generating the reference current (IR_EF) such that

IREF = (C_Y/ TO) X VREF .

17. A method according to claim 14. wherein said reference current generating step comprises converting a first reference voltage to the reference current via a current mirror.

18. A method according to claim 14, wherein the reference current has a frequency based on a pre-determined time reference, and wherein said clock signal generating step comprises periodically charging/discharging the second capacitance at the frequency of the reference current.

19. A method according to claim 14, wherein said clock signal generating step comprises generating the clock signal based on the second capacitance (Cx), a first reference voltage (Ym), and the reference current (IREF)-

20. A method according to claim 19, wherein said clock signal generating step comprises generating the clock signal having the period (T) such that

T = 2 x (T₀/ V_REF) X (C_X Z C_Y) Z IRE_F .