WO2006138492A3 - Post & penetration interconnection - Google Patents

Post & penetration interconnection Download PDF

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Publication number
WO2006138492A3
WO2006138492A3 PCT/US2006/023364 US2006023364W WO2006138492A3 WO 2006138492 A3 WO2006138492 A3 WO 2006138492A3 US 2006023364 W US2006023364 W US 2006023364W WO 2006138492 A3 WO2006138492 A3 WO 2006138492A3
Authority
WO
WIPO (PCT)
Prior art keywords
electrically conductive
chip
conductive contact
contact
chips
Prior art date
Application number
PCT/US2006/023364
Other languages
French (fr)
Other versions
WO2006138492A2 (en
Inventor
John Trezza
John Callahan
Gregory Dudoff
Original Assignee
Cubic Wafer Inc
John Trezza
John Callahan
Gregory Dudoff
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/329,556 external-priority patent/US7767493B2/en
Priority claimed from US11/329,576 external-priority patent/US7989958B2/en
Application filed by Cubic Wafer Inc, John Trezza, John Callahan, Gregory Dudoff filed Critical Cubic Wafer Inc
Priority to JP2008517112A priority Critical patent/JP5253158B2/en
Priority to CN2006800294579A priority patent/CN101253601B/en
Priority to KR1020077029402A priority patent/KR101419548B1/en
Publication of WO2006138492A2 publication Critical patent/WO2006138492A2/en
Publication of WO2006138492A3 publication Critical patent/WO2006138492A3/en

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    • H01S5/00—Semiconductor lasers
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    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/0201—Separation of the wafer into individual elements, e.g. by dicing, cleaving, etching or directly during growth

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing Of Electrical Connectors (AREA)
  • Wire Bonding (AREA)

Abstract

A method of physically and electrically joining two chips to each other involves aligning an electrically conductive contact of a first chip with a corresponding electrically conductive contact on a second chip, the electrically conductive contact of the first chip being a rigid material and the electrically conductive contact of the second chip being a material that is malleable, bringing the aligned electrically conductive contact of the first chip into contact with the corresponding electrically conductive contact on the second chip, elevating the contact of the chips to a temperature that is below a liquidus temperature for both the rigid material and the material that is malleable while applying pressure to the chips so as to cause the rigid material to penetrate the malleable material and form an electrically conductive connection, and, following the forming of the electrically conductive connection, cooling the contacts to an ambient temperature.
PCT/US2006/023364 2005-06-14 2006-06-14 Post & penetration interconnection WO2006138492A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2008517112A JP5253158B2 (en) 2005-06-14 2006-06-14 Post and penetration interconnection
CN2006800294579A CN101253601B (en) 2005-06-14 2006-06-14 Post and penetration interconnection
KR1020077029402A KR101419548B1 (en) 2005-06-14 2006-06-14 Post and penetration interconnection

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US69075905P 2005-06-14 2005-06-14
US60/690,759 2005-06-14
US11/329,556 US7767493B2 (en) 2005-06-14 2006-01-10 Post & penetration interconnection
US11/329,481 2006-01-10
US11/329,576 US7989958B2 (en) 2005-06-14 2006-01-10 Patterned contact
US11/329,576 2006-01-10
US11/329,481 US8154131B2 (en) 2005-06-14 2006-01-10 Profiled contact
US11/329,556 2006-01-10

Publications (2)

Publication Number Publication Date
WO2006138492A2 WO2006138492A2 (en) 2006-12-28
WO2006138492A3 true WO2006138492A3 (en) 2007-03-29

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PCT/US2006/023364 WO2006138492A2 (en) 2005-06-14 2006-06-14 Post & penetration interconnection

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Country Link
JP (1) JP5253158B2 (en)
KR (1) KR101419548B1 (en)
WO (1) WO2006138492A2 (en)

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US7850060B2 (en) 2007-04-05 2010-12-14 John Trezza Heat cycle-able connection
US7748116B2 (en) 2007-04-05 2010-07-06 John Trezza Mobile binding in an electronic connection
EP1978559A3 (en) * 2007-04-06 2013-08-28 Hitachi, Ltd. Semiconductor device
KR100975652B1 (en) * 2007-10-05 2010-08-17 한국과학기술원 via using Zn or Zn alloys and its making method, 3D chip stack packages using therof
CN103050420A (en) * 2008-06-05 2013-04-17 丘费尔资产股份有限公司 Constraint to components with high migration rate in electric connection
KR102190382B1 (en) 2012-12-20 2020-12-11 삼성전자주식회사 Semiconductor package
KR102544296B1 (en) * 2018-09-13 2023-06-16 쑤저우 레킨 세미컨덕터 컴퍼니 리미티드 A VERTICAL-CAVITY SURFACE-EMITTING LASER DEVICE and APPARATUS HAVING THE SAME

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US5814889A (en) * 1995-06-05 1998-09-29 Harris Corporation Intergrated circuit with coaxial isolation and method
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US20050146049A1 (en) * 2003-12-24 2005-07-07 Agency For Science, Technology And Research RF and MMIC stackable micro-modules

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WO2006138492A2 (en) 2006-12-28
JP2008544528A (en) 2008-12-04
JP5253158B2 (en) 2013-07-31
KR20080018896A (en) 2008-02-28
KR101419548B1 (en) 2014-07-25

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