KR101419548B1 - Post and penetration interconnection - Google Patents

Abstract

A method of physically connecting two chips to each other includes aligning an electrically conductive contact of a first chip with a corresponding electrically conductive contact on a second chip, the electrically conductive contact of the first chip being a rigid material, The electrically conductive contact of the material is a flexible material for a rigid material; Contacting the aligned electrically conductive contacts of the first chip to corresponding electrically conductive contacts on the second chip; The contact of the first and second chips is raised to a temperature at least below the liquefaction temperature of the rigid material while applying sufficient pressure to the first and second chips to allow the rigid material to penetrate the malleable material and form an electrically conductive connection therebetween step; And cooling the contacts of the first and second chips to ambient temperature after formation of the electrically conductive connection.

Electrically conductive contacts, chips, rigid materials

Description

POST AND PENETRATION INTERCONNECTION < RTI ID = 0.0 >

The present invention relates to semiconductors, and more particularly to electrical connections for devices.

It is difficult to make an electrical contact that extends all the way through the electronic chip (by forming an electrical conductor via). b) the width of the vias is large; c) the vias are separated by a large distance, that is, several times the width of the vias, in the case of a very shallow vias, i.e. a depth considerably less than 100 microns Or, it is almost impossible to have precision as well as bulk, or controlled repeatability. This difficulty is exacerbated if the via is close enough to generate signal crosstalk or if the chip passing through the via has charge. Because the conductors in the vias can not be allowed to operate as short circuits or carry charge other than the charge of the relevant part of the chip. In addition, existing conventional processes are not suitable for use in forming integrated circuit (IC) chips (i.e., including active semiconductor devices). Because these processes can damage the chip, they increase the cost and reduce the ultimate yield. In addition to the above-mentioned problems, capacity and resistance problems arise when the material passing through the via has a charge or the frequency of the signal to be transmitted through the via is very high, for example, when it exceeds 0.3 GHz.

Indeed, the use of non-scaleable large packaging, the fact that assembly costs do not scale similar semiconductors, that chip cost is proportional to area, and that high performance processes are very expensive, This requires a high-performance process, that the current process is limited in voltage and other technologies, that the chip designer is limited to one process and one material for the design, the high-power pad driver (through the package) The need for chip-to-chip connectivity, even small changes or even minor design errors, necessitates the manufacture of one or more completely new masks for the new chip, making a complete new chip requires millions of dollars in mask costs alone, It is difficult or complicated to test the chip, Many problems remain in semiconductor technology, including the difficulty of testing chip combinations before packaging.

Therefore, there is a need for a technique that can handle one or more of the problems described above.

Summary of the Invention

A chip-to-chip electrical contact having a via penetrating the wafer, a third chip formed in advance, and a process for easily forming a doped semiconductor substrate. The features described herein are indicative of improvements in the general field of helping the approach and bonding the chips together.

One form is a method of physically electrically connecting two chips to each other, the method comprising: aligning an electrically conductive contact of a first chip with a corresponding electrically conductive contact on a second chip, the electrically conductive contact of the first chip having a rigidity Wherein the electrically conductive contact of the second chip is a flexible material for the rigid material; Contacting the aligned electrically conductive contacts of the first chip to corresponding electrically conductive contacts on the second chip; The contact of the first and second chips is raised to a temperature at least below the liquefaction temperature of the rigid material while applying sufficient pressure to the first and second chips to allow the rigid material to penetrate the malleable material and form an electrically conductive connection therebetween step; And cooling the contacts of the first and second chips to ambient temperature after formation of the electrically conductive connection.

Another aspect includes selecting one of a metal or alloy as a rigid material, wherein the metal or alloy has a melting temperature that is at least 50 < 0 > C higher than the melting temperature of the flexible material.

Another aspect is a method of manufacturing a semiconductor device, comprising: after the cooling, raising the first and second chips to a separation temperature that is at least less than the liquefaction temperature of the rigid material; And separating the first chip from the second chip to separate the electrically conductive contact of the first chip from the corresponding electrically conductive contact of the second chip.

Another aspect includes attaching an electrically conductive contact of the first chip to a relatively flexible electrically conductive contact of a new chip different from the second chip.

Another form is a first chip having an electrical contact formed thereon, the electrical contact of the first chip comprising a rigid material; And a second chip having an electrical contact formed thereon, wherein the electrical contact of the second chip comprises a flexible material with respect to the rigid material, and wherein the electrical contacts of the first and second chips include a post and a through- And the chip unit is connected to each other by using the same.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features described herein are some of the many advantages and features that are available from the exemplary embodiments and are disclosed for purposes of understanding the invention. It should be understood that they are not to be construed as limitations on the invention as set forth in the claims or as a limitation on the equivalents of the claims. For example, some of these advantages are incompatible in that they can not co-exist in a single embodiment. Likewise, certain advantages are applicable to one aspect of the invention, but not to others. Thus, a summary of features and advantages should not be taken to be regarded as a departure from the equivalents. Other advantages and features of the present invention will become apparent from the following detailed description, drawings and claims.

1 is a simplified side view of a portion of a chip including a plurality of active electronic devices;

Fig. 2 is a plan view of the upper surface of the specific region of Fig. 1; Fig.

Figure 3 is a simplified cross-sectional view of a portion of Figure 1;

4 is a plan view of the top surface of the particular region of FIG. 1 after forming the trench shown in the side view in FIG. 3;

Figure 5 is a simplified cross-sectional view of a portion of Figure 1 as a result of subsequent processing;

FIG. 6 is a top plan view of the top surface of the particular region of FIG. 1 after filling the trench with the electrically insulating material shown in the side view in FIG. 5;

Figure 7 is a simplified cross-sectional view of a portion of Figure 1 as a result of sequential processing;

8 is a plan view of the top surface of the particular region 124 of FIG. 1 after creating the via trench.

Figure 9 is a simplified cross-sectional view of a portion of Figure 1 as a result of sequential processing;

10 is a plan view of the top surface of the particular region of FIG. 1 after metallization of the via trench.

Figure 11 is a simplified cross-sectional view of a portion of Figure 1 as a result of any subsequent processing;

FIG. 12 is a top plan view of the top of a particular region of FIG. 1 after the optional voiding of the remaining void material. FIG.

Figure 13 is a simplified cross-sectional view of a portion of Figure 1 as a result of any other processing.

Fig. 14 is a top plan view of the top surface of the particular area of Fig. 1 after optional addition of the remaining voiding material. Fig.

Figure 15 is a simplified cross-sectional view of a portion of Figure 1 as a result of sequential processing.

Figure 16 is a simplified cross-sectional view of a portion of Figure 1 after thinning the substrate to remove bottom metal;

Figure 17 is a simplified cross-sectional view of a portion of Figure 5 as a result of processing of another variant.

FIG. 18 is a top view of a cross section taken at the bottom of the specific region of FIG. 1 after the formation of the via trench. FIG.

Figure 19 is a simplified cross-sectional view of a portion of Figure 5 as a result of further processing in a manner described in connection with Figure 9;

Figure 20 is a simplified cross-sectional view of a portion of Figure 5 as a result of any further processing in the manner described in connection with Figure 11;

Figure 21 is a simplified cross-sectional view of a portion of Figure 5 as a result of any further processing in the manner described in connection with Figure 13;

FIG. 22 is a simplified cross-sectional view of a portion of FIG. 5 as a result of thinning the substrate to expose the bottom metal in a manner described in connection with FIG. 15 in another variation of FIG.

Figure 23 is a simplified cross-sectional view of a portion of Figure 5 as a result of thinning the substrate to remove the bottom metal in the manner described in connection with Figure 16 for another variation of Figure 17;

24 is a simplified representation of the dual conductor deformation after metallization of the sidewalls;

25 is a simplified representation of a dual conductor deformation after filling a trench with an electrically insulating material 500;

26 is a simplified representation of a via trench created by removing all the islands of semiconductor material;

27 is a simplified representation of a via trench created by removing only the inner island of a semiconductor material;

28 is a simplified representation of an example of dual conductor deformation;

29 is a simplified representation of another example of dual conductor deformation;

30A and 30B are views each showing the use of any additional thermally generated dielectric or insulator in the approach of FIGS. 28 and 29;

31 shows in simplified form an example of 3-conductor deformation;

32 is a simplified cross-sectional view of a portion of another chip embodiment similar to the implementation of Figs. 9-16 except that voids remaining after metallization are not filled.

Figure 33 is a simplified cross-sectional view of a portion of another chip embodiment similar to Figure 23 except that voids remaining after metallization are not filled.

Figures 34 and 35 are cross-sectional views, respectively, of the chips of Figures 32 and 33 after hybridization to each other.

Figure 36 illustrates an embodiment of Figure 34 after selective coating of an insulator or conformal coating.

37 is a view showing a representative example of a section of an annular trench;

Figure 38 is a simplified schematic diagram of a general process for preparing a wafer for stack.

Figures 39-41 illustrate a portion of an exemplary chip that is processed to create a through-chip connection using later variations of the processes described herein to be stacked together to form a chip unit.

Fig. 42 is a diagram showing in a simplified form the process for rear-front deformation; Fig.

Figure 43 shows in simplified form the process for capacitive coupling deformation;

Figure 44 shows in simplified form the process for pre-connection deformation;

45 and 46 illustrate exemplary tack and lysis parameters in simplified form;

47 illustrates a simplified example including a "minimum" contact;

48 illustrates a simplified example including an extended contact;

49 shows a portion of a stack of semiconductor chips having through-chip connections described herein.

Figure 50 shows a portion of a simplified stack of chips shown in Figure 49 stacked using post and through connection approaches.

51 is a simplified representation of voids in the metallization film by a preformed post;

52 is a simplified view of the chip of FIG. 51 after being coupled to an electronic chip; FIG.

Figures 53 to 71 show simplified variations of basic contact formation and coupling approach.

72-87 illustrate another simplified variation of the basic contact formation and coupling approach;

Figs. 88-91 illustrate in simplified, parallel form a first portion of two further deformation approaches, which later form a stiff post on the rear side of the daughter wafer. Fig.

92 is a cross-sectional photograph of an exemplary oblique via;

93 is a photograph of an exemplary via having a depth of 100 microns and a diameter of 20 microns.

94 is a cross-sectional photograph of a chip in which a sharp via is formed;

Figures 95 to 102 show a second part of two further variants of Figures 88 to 91 in simplified parallel form.

Figures 103 to 125 illustrate in simplified, parallel form a modified process for preparing a wafer for attachment to another element.

Figures 126-139 show in simplified form another modified process for preparing a wafer for attachment to another element.

140 is a simplified representation of a daughter wafer contact and a mother wafer contact immediately prior to the tack condition;

Figure 141 is a simplified representation of the contact of Figure 140 after the dissolving process is completed;

142 shows a profile of a soft contact;

Figures 143a-143p illustrate a representative example of some of the myriad possible mother contact profiles.

144 is a photograph showing another example of the profile of the soft contact.

145 is a photograph showing a profile of a rigid contact designed to penetrate the soft contact of FIG. 144;

146 is a simplified representation of another contact example profile;

147 through 152 are diagrams illustrating a modified process implementing the concept of well attachment.

153 to 156 are diagrams showing, in a simplified form, the types of reverse well variants;

157A-157B are longitudinal cross-sectional photographs of a via set of 25 micron diameter, each extending to a depth of 155 microns, and a 15 micron diameter, extending to a depth of 135 microns.

Figure 158 is a photograph of a via different from Figures 157A and 157B that are not filled with all the way to the floor.

Figures 159 through 167 illustrate another variation of a Class II-type stiff well attachment.

Figures 168-170 illustrate another variation of a well attachment approach where chips are attached to each other by separate remote contacts.

Figures 171a and 171b illustrate the accuracy of other remote contact variations.

172 illustrates a cross-section of an exemplary coaxial contact;

Figs. 173 to 175 are views showing examples of use of coaxial contacts. Fig.

176 through 179 are diagrams illustrating two examples of sealing using the contacts described herein.

180 is a chart summarizing other approaches that form other variations using rigid / soft contact paradigms;

FIGS. 181 and 182 are charts summarizing other approaches that form a via deformation. FIG.

Figures 183-195 detail the process flow for a particular example involving metal deposition on a daughter wafer.

Figures 196 to 205 detail the process flow for a specific example involving metal plating on a daughter wafer.

206 shows mother board electroless plating deformation in a simplified form;

Figure 207 is a simplified representation of a thin dielectric deformation of a mother wafer;

208 is a diagrammatic representation of a thick dielectric deformation of a mother wafer in a simplified form;

Figure 209 illustrates an exemplary, typical dimension for a mother wafer contact having a 14 micron wide contact pad spaced at a pitch of 50 microns prior to barrier deposition.

210 is a view of the contact of Figure 209 after barrier and cap deposition.

FIG. 211 is a diagram illustrating the general dimensions of a mother wafer contact having 8 micron wide contact pads spaced at 25 micron pitch.

212 shows an exemplary, typical dimension of a daughter wafer contact having a 14 micron wide contact pad spaced at a 50 micron pitch, produced by deposition.

Figure 213 is an exemplary, typical view of a daughter wafer contact having an 8 micron wide contact pad spaced at 25 micron pitch, produced by deposition.

214 is an illustration of an exemplary, typical dimension of a plated deformed mother wafer contact having a 14 micron contact pad spaced at 50 micron pitch before self-aligned seed etching is performed.

215 is a view of the contact of FIG. 214 after self-aligned seed etching is performed; FIG.

216 shows the use of an inner via as part of the heating pipe arrangement;

Figure 217 shows a separate and connected variant in simplified parallel form.

Figure 218 shows yet another separating and connecting variant in simplified, parallel form.

Figure 219 shows a representative example of a conventional microprocessor chip and its respective components in a simplified form;

220 is a simplified representation of a method by which another microprocessor may be constructed from the elements of the microprocessor of FIG. 219 to provide a smaller space and a distance between substantially reduced elements;

FIG. 221 shows a direct comparison between the space of the chip of FIG. 219 and the space of the chip of FIG. 220;

Figure 222 shows a functional packaging variant;

Figure 223 is a diagram showing a concrete example of a modification of the packaging of Figure 222;

Figures 224 to 231 are diagrams illustrating a brief overview of routingless processing variants.

Figures 232 through 235 are diagrams illustrating other routing less processing variants in a simplified form;

Figure 236 shows in simplified form the use of non-wired optical connections between two chips;

Figure 237 illustrates the use of a variation of the heat pipe configuration to pass light from the laser-bearing chip to the photodetector-bearing chip, even when two different chips are interposed between the laser-bearing chip and the photodetector- Fig.

Figure 238 shows a tacking and melting process approach in a simplified form;

Figure 239 shows a functional layer of a daughter contact in a simplified form;

240 is a simplified representation of a functional layer of a mother contact;

FIG. 241 is a view showing, in a simplified form, a material constitution example of a functional layer of a daughter contact; FIG.

242 is a view showing, in a simplified form, a material configuration example of a functional layer of a mother contact;

Figures 243a, 243b and 243c are photographs of the combined mother and daughter contacts.

Figures 244 and 245 show single pin holes per chip in simplified form;

Figures 248 and 249 are diagrams illustrating other pore approaches in simplified form;

250 to 254 show another pore approach in simplified form;

Hereinafter, the detailed operation and structure of the present invention will be described in detail with reference to the accompanying drawings. It is to be noted that, in the drawings, reference numerals and like components are denoted by the same reference numerals and signs as possible even if they are shown in different drawings.

First, the term "wafer ", as used in the present invention, is used herein to refer to a chip, a " die ", and a" wafer ", unless the context clearly and exclusively mentions only the entire wafer Quot; and "including, " and the like. For example, the entire wafer may be an 8-inch or 12-inch wafer, a chip or die "chip-to-wafer ", a" wafer- quot; wafer scale "processing. In addition, a substantial reference to a "wafer or chip" or a "wafer or die" to be used below is intended to encompass the use of the term "wafer or die" It should be regarded as a duplication of terms.

In general, a particular implementation, which will be described below, allows for the formation of a connection between two or more wafers, each wafer being a fully-formed electron according to a simple controlled fashion. an electronic device, an active optical device, and an electro-optic device. By this control method, a via is deepened, a high repeatability, a controlled capacitance and a resistance, Or electrical insulation between the substrate (through the vias -) becomes possible.

According to embodiments of the present invention, electrically conductive vias may be formed. Although the depth-to-width ratio of the chips is generally used in a ratio of 5: 1 to 10: 1, the vias of the present invention have a width of about 15 microns or less, a depth of about 50 microns or more, The ratio of depth to width of the chip is set at a ratio of 30: 1 and 3: 1. In addition, the present invention has the advantage that the chip portion through which the via is electrically activated.

In particular, the present invention provides an electrical access through a doped semiconductor portion of a wafer using a passage. At the location of the passageway, the sidewalls insulate the doped semiconductor from the electrical conductor, which propagates through the passageway.

In addition, the present invention is applicable to narrow passages (i. E., About 15 microns or less) that allow tight control of the thickness of the isolating material and the electrical conductor to maintain constant and acceptable capacitance and resistance. ).

The present invention is also suitable for forming a contact having a circular diameter of between 0.1 micron and 15 microns, wherein the contact has an upper end and a lower end, wherein the upper end has no limit, The invention can further improve the general degree of integration, and the bottom portion is implemented with photolithographic techniques that are presently available. That is, the inventive advancement in the photolithographic technology of the present invention makes it possible to further reduce the current limit as a smaller definition.

Also, solder contacts are several hundreds of thousands of microns in length, or wirebond contacts are thousands of microns in length and often require a pad driver for impedance drive between chips. The present invention utilizes very short length contacts (less than 10 microns), which has the effect of further lowering the parasitic electrical effect between the chips.

The contacts of the present study are spaced from each other by three or less of the contact size between contacts and have a width of mellalleable material prior to integration with complementary contacts. The complementary contact, for example, if the initial contact height is 8 microns, the spacing between contacts is up to about 25 microns.

The invention resides in allowing stacking on a separation spacing of about 20 microns or less. Although about one micron spacing is implemented in the present invention, spacing of typically less than 10 microns is common. In general, the minimum spacing is determined by the topology of the closest surface between the two wafers connected to each other, and the two wafers contact each other at their highest height and the inter-pad distance represents the maximum height spacing.

The present invention can form contacts on a pitch of less than 50 microns. In the present invention, a pitch of 7 microns in size is implemented, but usually a pitch of 25 microns or less is used. Is limited to the function of currently available photo etch techniques. Here, the pitch can be made smaller.

Some variants have the following characteristics:

The potential for millions of contacts per cm < ² >; Simultaneous electrical, mechanical and thermal attachments; Attachment with low strength but high strength (1000 kg / cm ² ) connection (high strenghth connection); Connections with economies of scale; Accommodated non-planar wafers; Most processing performed on wafer scale (eg, 10 "GaAs on 12" wafers), chip-to-chip, chip-to-wafer, A wafer-to-wafer based process, an electrically grounded process, and a linearized device (i.e., a device-bearing chip) into a third-party supplied chip A connection used; a formation of vias before a plurality of chips are connected to one another; a capability to test or, if necessary, re-operate the chip combination before it is permanently connected; (E.g., GaAs-to-InP, InP-to-Si, GaAs-to-Si, SiGe-to-SiGe-to-Si and other insulating wafers made of ceramics, LCP or glass) The ability to form a chip-sized package with the benefit of economics; A plurality of voltages, techniques, and techniques are provided to enable individual chips to be used most suitably for a particular design, with a total circuit set that enables low-speed functions that make them unnecessary, , And the ability to be designed to have materials that do not take into account the technologies required for other aspects of the design, enhanced off-chip communication, increased modularity of the design at the chip level, Where the chip level allows the core design to be produced in multiple products without consuming the redundant non-recurring engineering costs remaining, and enables speed matching as a technology type Low-speed circuits no longer need to be produced at high cost, and the technology is implemented in terms of speed.

Overall, the present invention is directed to improving the ability to form chip-to-chip connections using through-wafer electrical contacts. The through-wafer electrical contact can be used as a doped substrate, but it will not short out the substrate, so it will have charge opposite to that of the substrate. In addition, such "through-wafer" studies are available for wafers composed of semiconductors, insulators such as ceramics, and conductive or non-conductive materials.

In addition, using current devices (with an aspect ratio of 30: 1) to etch semiconductor materials, vias vias of narrow cross section (i.e., width of 15 microns, in some cases less) A process is performed for vias whose depth extends from 50 microns to 500 microns. In addition, the process allows close control of capacitance and resistance. For example, the vias formed through the process carry high speed electrical signals (i.e., frequencies above 0.3 GHz) or optical signals in some implementations.

Also, embodiments of the present invention enable the formation of concentric vias, and if they are conductive, each can carry different signals and charges. Further, embodiments of the present invention include an inner via in a concentric via, wherein the inner via in the concentric via is a cooling system in which the inner via is used as a heat pipe arrangement To be used as a part. Still other embodiments enable the use of a stacking method in which a plurality of chips are stacked and electrically interconnected based on chips and chips, chips and wafers, or wafers and wafers.

Advantageously, in fact, all the stacking processes and variants described below require only a new stacked piece to be aligned at the bottom of the piece. This is in sharp contrast with the prior art, in which all the pieces in the stack must be aligned together, and then the conductive material is inserted into the stack to form a trans-stack connection.

The present study allows all the pieces in the stack to be precisely aligned to each other piece, rather than to the generally directly disposed bottom piece. In addition, this study enables uniform implementation using uniaxial, coaxial, and triaxial connections, which could not be achieved in normal alignment methods.

The various methods described above are merely presented as examples using all examples of wafers composed of semiconductor materials. The semiconductor material may be, for example, silicon (Si), silicon-germanium (SiGe), gallium-arsenic (GaAs) Pads, modulators, and laser detectors).

The first embodiment of the present invention includes a two-etch process. Here, there is a need for the wafer to be etched for the purpose of a semiconductor material (i. E., A doped semiconductor with or without some or all of its associated substrate) in the two-etch process.

This embodiment process begins with a device-bearing-wafer of semiconductor material. At least one of the trench portions with the correct width is etched to a desired depth so that in the case of a semiconductor wafer, the trench extends into the wafer substrate and forms a perimeter with respect to the semiconductor material portion.

In particular, the shape of the protrusions may be a closed shape, so that the outer wall / inner wall of the trench need not have the same shape. The ultimate capacitance and resistance of the via connection are controllable through the selection of the shape of the inner / outer protrusions of the trench and their separation distance. The depth of the trench is generally greater than 50 microns (in some cases, more than 500 microns). However, since the trenches do not propagate through the entire substrate of the wafer, the bounded semiconductor pieces do not fall out. The trench is filled with electrically insulating material.

At least the bound semiconductor piece portion is etched leaving a hole with a cross section that is narrower than that bounded by the outer trench walls so that a via formed by etching the semiconductor via is bound by an insulating material , And is bound by a perimeter ring protruding from the central semiconductor piece at a depth, and the remainder is a substrate. The holes are metallized so that an electrical connection is made between the top of the wafer and the bottom of the hole. The backside of the wafer (i.e., the substrate) is thinned to expose the metallized portion at the bottom of the hole such that the hole is in contact with the substrate side contact or portion thereof (hereinafter the broad term "contact" Quot;).

Typically, although in some embodiments metallization extends to only a sufficient depth when the substrate is sufficiently thinned, it will be at least metallized to the highest depth of the surface portion defining the hole. In this regard, if the process for performing the metallization fails to perform the metallization to the full depth at which the metallization extends to where the thinning stops, the contact may be formed. For example, in the present embodiment, if the vias extend to a substrate having an overall length of about 600 microns, the metallization will result in a total depth of about 300 microns (i.e., 300 microns less than the via itself) Is not adversely affected to the depth at which the substrate is thinned (allowing the wafer or chip to be metallized without reducing it to an unacceptable range).

Through the above-described embodiments, variants, permutations and combinations, the connection points can be brought closer to the on-chip device. By making the connection points closer to the on-chip device, it is possible to further facilitate chip-to-chip connections to the vertical direction (i.e., through-chip stacking), reduce the distance between the connection points, Thereby reducing the need for use of wire bonds for chip-to-chip connections.

In addition, the present invention facilitates the formation of sub-component specialty designs so that they can be mixed and matched with one another in the manufacturing process. That is, the third dimension makes the chipset material, geometry, and product more readily available.

In addition, the present invention has the potential to enable mixing at different speeds or material technology types and to reduce manufacturing costs as well as mix-match of main or sub-component designs. Chip-to-chip connections are formed using optical rather than electrical connections between chips.

The contents of the present invention are more beneficial through optical use of chip-chip connections, thereby reducing the stresses of chips connected to each other and reducing the risk of chip damage.

The above-described features will be described with reference to specific drawings and by way of a number of examples, which are for illustrative purposes only and are not to be construed as limiting the scope of the invention, but are also applicable to other examples. In some instances, it may be exaggerated or distorted overall from an intended point of view to aid in the presentation and understanding of the present invention.

Furthermore, according to the present invention described above, specific devices on a chip are arranged independently of each other. Thus, references to a particular type of device (e.g., a laser of the first example) are arbitrary and have nothing to do with the aspects to be described below, unless the electrical contact is a part of a device that needs to be made. That is, the present invention, which will be described below, applies equally to all devices and circuit elements in which contacts are formed.

1 is a simplified side view showing a portion 100 of a chip 102 including a plurality of solid state electronic devices, e.g., resistors, capacitors, transistors, diodes, lasers, photodetectors, or any combination thereof. The portion 100 shown in Figure 1 is for illustrative purposes only and includes an upper mirror 106, an underlying active region 108, and a bottom mirror 110 disposed on the substrate 112 Laser 104 which has a height 114 as much as a few microns from the top outer surface 116 of the non-device portion near the device 104 of the chip 102.

As shown, the laser 104 is a conventional vertical cavity surface emitting laser (VCSEL). The upper mirror 106 is electrically connected to a predetermined element on the side 118 of the substrate opposite the side 120 on which the laser 104 is provided such that it is within the specified region 124, Lt; RTI ID = 0.0 > 122 < / RTI >

The terms " top " and " bottom " as used hereinbefore are customary in the sense that the laser or photodetector is initially referred to as the above- Refers to the portion closest to the substrate regardless of whether it is emitted toward the substrate 112 or from the substrate 112 (or in the case of a photodetector, regardless of the direction in which the light is received).

Figure 2 is a top view of the top surface 116 of the particular region 124 of Figure 1 before the process begins.

Hereinafter, a basic process for forming a through-chip contact will be described with reference to FIGS. 1 and 2.

Figure 3 shows a simplified cut-away view showing part 100 of Figure 1 as a result of the following processing.

First, the semiconductor material 122 is etched to a depth at which the trench 302 is partially formed in the substrate 112, preferably using an anisotropic etch process (to form a relatively straight trench sidewall 304) And the trench 302 is formed. The total depth of the trenches 302 may be greater than 100 microns and may extend from 500 to 600 microns or greater as the case may be. However, the trench 320 must stop forming before the substrate 112 is fully pierced, or in many cases, lose its ability to implement the invention. Trench 302 is in the form of a ring that takes a closed form while forming a cross-section in a plane parallel to the plane of the substrate. By using such an annular trench 302, the island 306 of semiconductor material 122 remains and is at least in place by the undamaged top 308 of the substrate 112. It should be noted that although the " annulus " for describing the trench 302 at this time is shown in a circular shape, this is merely to simplify the explanation. It is to be understood that the terms " annular " and " annulus " as used herein are not intended to be limited to any particular or particular form, nor that the outer periphery need not take the same form as the inner core. As long as the trench takes a closed form and forms an " island " within it, the term trench as used in the present invention may be considered as an annular trench or a ring. That is, the terms " annular " and " annulus " as used herein are intended to encompass a closed inner and outer main shape including a closed (regular or non- regular) polygon, or other closed inner and outer main shapes, And any combination of inner and outer main shapes. These terms are also intended to encompass fixed widths and varying widths in accordance with the requirements or as required in certain cases.

FIG. 4 is a plan view showing the top surface 116 of the specific region 124 of FIG. 1 after forming the trench 302 shown in the side view of FIG. In Fig. 4, the annular characteristics of the trenches 302 can be clearly seen. The trench 302 has a closed inner periphery 312 and a periphery 314 and a width 310 and surrounds the island 306 to form an island 306 therein from the semiconductor material 122.

FIG. 5 is a simplified cut-away view showing part 100 of FIG. 1 as a result of subsequent processing as follows.

At least the trench 302 is coated with a dielectric or other electrically insulating material 500 and optionally the insulating material 500 may be applied to cover a portion of the outer surface 116 to a predetermined thickness . Alternatively, if heat transfer is a concern, a good heat transfer material having electrical insulation may be used as the electrical insulating material 500. [

The effect obtained by the above-mentioned method can be found by comparing it with the related art. First, as a general matter, it is very difficult to uniformly apply the dielectric material, especially when the thickness is uniform. Second, this problem becomes more severe when the dielectric is to be applied to a non-planar surface and becomes more severe when it is to be applied on a vertical wall such as the vias described in the present invention. Thus, these schemes have no meaningful ability to control uniformity in that other schemes form the holes and make the walls of the holes formed precisely coated with the dielectric and have conductivity. The lack of uniformity of these schemes, especially when the associated signal frequencies are very high, for example, in excess of 0.3 GHz, will have a dramatic effect on capacitance and impedance and thus have a dramatic effect on performance. In contrast, according to the schemes described in the present invention, the size of the trench 302 can be precisely controlled to the precision of the trench 302 itself, so that the capacitance and resistance can be precisely controlled. Since the inner and outer peripheral walls of the trench 302 are covered with the portion covered by the insulating material 500, the thickness and uniformity of the covered portion are defined by the inner and outer circumferential walls of the trench 302, Is defined. Therefore, it is only necessary to confirm whether the trench 302 is filled, which is a low-cost process with very low precision. Unlike the prior art, precision is not required during application of the dielectric.

Figure 6 illustrates a top view of the particular area 124 of Figure 1 after filling the trench 302 with the electrically insulating material 500 and optionally (optionally) partially covering the top outer surface 116, as shown in the side view of Figure 5, FIG.

Figure 7 is a simplified cut-away view showing part 100 of Figure 1 as a result of the following process:

When the electrically insulating material 500 is solidified (by curing or hardening treatment or other treatments), the island 306 of semiconductor material within the annulus 704 of the insulating material 500 may have a particularly desirable implementation (E.g., to a depth similar to the trench 302) (i. E., The trench extends further into the substrate to some extent, preferably the substrate 112) So that the via trench 702 is formed. The depth 502 of the via trench 702 may be further extended to a sufficient depth so as to reach substantially the same distance as the trench 302 into the substrate 112 during processing, It may be longer or shorter than the depth of the trench 302. In addition, the innermost wall of the annulus 704 defining the boundary of the island 306 determines the shape and outline of the via trench 702 formed by the removal process, which will then become a dielectric. Thus, it is not generally affected by the etching process and does not require strict control in the width and depth direction of the removal of the island 306 of semiconductor material, Can be removed. Of course, other suitable processes, such as laser ablation, laser drilling, or some combination thereof, may be used to augment removal of the island 306, or else the removal of the island 306 may be accomplished.

Subsequent to the process of this example, when the via trench 702 is formed, the sidewall 706 will be the insulating material 500 and the bottom 708 will be defined by the substrate 112, The portions 708 as well as the side walls 706 of the via trenches 702 will all be electrically nonconductive.

8 is a plan view showing the top surface 116 of the specific region 124 of FIG. 1 after the via trench 702 is formed in the annulus 704 of the electrically insulating material 500 shown in the side view of FIG. 7 .

Figure 9 is a simplified cut-away view showing part 100 of Figure 1 as a result of the following process:

The via trenches 702 may be formed using at least a trench sidewall surface 706, for example, using physical or chemical deposition techniques, such as sputtering, evaporation, plating, or other metal deposition techniques, And becomes electrically conductive by metallizing the longitudinal portion (i.e., along its depth). That is, in this metallization process, a conductive solid, a conductive epoxy or a reflowable material (e.g., a suitable temperature conductive liquid material such as solder) may be used. This metallization process may be used to form a continuous electrically conductive connection at least from the via bottom 708 to the top surface 116 (in many cases, to the device when the device is part of the chip where the via is formed) It will be used generally. 9 shows an electrical trace 902 formed by this process that extends from a contact 904 on the top mirror 106 of the laser 104 to a bottom portion 708 of the via trench 702. In this example, Fig. As shown, the entire sides of the sidewalls 706 and bottoms 708 of the via trenches 702 are fully coated with metal.

As described above, the width and length of the insulating ring can be controlled strictly, such as the thickness of the conductor formed by the metal treatment, so that a constant capacitance can be achieved for the metallized surface. The insulative material 500 also electrically insulates the contacts 904 from the semiconductor material 122 through which they pass and thus can cause electrical shorts of the contacts to other devices or conductors, ≪ / RTI >

Figure 10 is a top view of the top surface 116 of the particular region 124 of Figure 1 after metallization of the via trench 702 shown in the side view of Figure 9 and formation of the wires 902 to the device contact 904. [ to be.

Figures 11-14 illustrate additional and optional treatments that may be useful or desirable for some implementations. The system shown in FIG. 11 or 12 is independent of the system shown in FIG. 13 or 14. As a result, according to the specific embodiment, the method shown in Figs. 11 and 12 or the method shown in Figs. 13 and 14 can be used separately and these two methods can be used together in each order.

Several effects can be achieved through one or both of these selective methods. First, filling the void with material adds mechanical strength and increases structural strength, thereby reducing potential stress. Secondly, the use of solder, epoxy, or other bonding material can help in the final connection of the chip to other devices, particularly when the process of bonding the chip to another chip involves bonding . Third, by injecting material into the void space, the risk of unwanted material entering it can be reduced. Finally, the possibility of damaging the metallized portions in the via trenches by the implant material is reduced or eliminated, especially when metallized less than all sidewalls. Further, by changing the thickness of the insulating part and the metal, the coefficient of thermal expansion (CTE) of the wafer can be balanced to coincide with the coefficient of thermal expansion of the wafer. For example, an oxide (with a thermal expansion coefficient of 1 ppm) can be used with copper (with a thermal expansion coefficient of 17 ppm) to match the thermal expansion coefficient of the silicon (with a thermal expansion coefficient of 2.5 ppm).

Of course, since both of these are optional, they may not be adopted altogether while the present invention is being used. However, these two processes are exemplified in Fig. 11 through Fig. 14 for the sake of complete understanding.

Fig. 11 is a simplified cut-away view showing part 100 of Fig. 1 as a result of the following optional treatment.

After the metallization is completed, if the remaining empty space 1100 is not left empty for use as described below, the remaining empty space 1100 is filled with a predetermined material (in this case, for example, the bonding material 1102) ) Partially or totally. Depending on the particular implementation that will be using these variations, the bonding material 1102 may be conductive or non-conductive. E., An electrically conductive material, such as solder, metal, or alloy, which may be applied, for example, through electroless plating or electroplating, or deposited by evaporation or sputtering, or may be an electrically conductive material such as glue or an oxide such as epoxy or silicon dioxide Or may be a non-conductive joint material such as a non-conductive material.

12 shows the top surface 116 of the particular region 124 of FIG. 1 after selectively implanting the bonding material 1102 into the remaining empty space 1100 of the via trench 702 shown in the side view of FIG. FIG.

Fig. 13 is a simplified cut-away view showing part 100 of Fig. 1 as a result of the following optional processing.

If the empty space is not completely filled by the metallization process instead of or in addition to the above-described process, if there is an empty space 1100 remaining after the metallization process is completed, for example, with the simple finish material 1302 partially or entirely It can also fill. According to a particular embodiment using this variant, the finishing material 1302 may be an insulator, conductive epoxy, conductive solid, or reflowable material, such as the insulating material 500 that was initially used to fill the trench 302 Conductors may be used, or a conformal coating may be used. Further, when the finishing material 1302 is used, it is not necessary to inject the finishing material into the empty space 1100 alone. 13, when the finishing material 1302 is an electrically insulating material and the bonding material 1102 is used, the finishing material 1302 can be injected onto the top of the bonding material 1102 after formation of the bonding material 1102, May extend out of the void 1100 to cover and protect portions and / or portions 1304 of the wires 902 extending to the contacts 904, or may be implanted to planarize the wafer even in the absence of voids. have. For example, the finishing material 1302 may be planarized to planarize the wafer so that the entire surface can be an oxidizing material that can be used to bond to other devices such as wafers or individual chips.

14 illustrates a side view of the bonding material 1102 in which a sufficient amount of a finishing material 1302 covering and protecting at least a portion 1304 of the wire 902 is selectively inserted into the empty space 1100 left over the bonding material 1102, And then the upper surface 116 of the specific region 124 of FIG.

Referring back to the basic process, FIG. 15 is a simplified cut-away view showing part 100 of FIG. 1 as a result of the following process:

When the metallization process shown in Figs. 9 and 10 is completed, a non-device (not shown) of the substrate 112 (whether using either or both of the two options shown in Figs. 11-14) The backside portion 118 is provided with at least a bottom metallization 1502 using chemical processing such as etching, mechanical processing such as polishing, chemical mechanical processing (CMP), or any combination thereof. (Not shown) of the device contact 122 from the doped semiconductor material 122 (in the case of the bottom mirror 110 of the laser 104) without having to perform a special post- The electrical contact 1504 is formed in the rear portion 118 of the substrate 112 that is electrically connected to the substrate 904.

Instead of this treatment, thinning may be performed until the bottom metallization 1502 is removed (regardless of whether it is filled) or until the void space 1100 itself is exposed. Fig. 16 is a simplified cut-away view showing a part of Fig. 15 after the process of thinning the substrate to remove the lower metallization; Preferably, if at least the method of FIGS. 11 and 12 is used, the empty space 1100 will be filled with the adhesive material 1102. Thus, as shown in Fig. 16, thinning the rear portion 118 of the substrate 112 until the bottom metallization 1502 of Fig. 15 is removed can still serve as part of the rear side electrical contact The bonding material 1102 can be exposed while the " claw portion " of the metal contact 1602 remains unchanged. Therefore, if the bonding material 1102 is electrically conductive (for example, solder), both the bonding portion 1102 and the bonding portion 1102 function as a contact. On the other hand, if the bonding material 1102 is not electrically conductive, then the bonding material 1102 may be bonded to the bonding material 1102 while the ring portion 1602 functions as a contact and provides an electrically conductive path from the back portion 118 to the device contact 904. [ So that the chip can be bonded to other devices.

15 or 16 to protrude beyond the bottom of the wafer for use as a contact in post and through mode, either alone or in combination with the tack and fuse method described in the present invention. It can also be thinned.

Here, the basic processes described above with other more complex processes implemented according to the basic process described above, may be used to form vias before fabricating devices (e.g., transistors, diodes, lasers, photodetectors, etc.) It should be noted that there is an additional advantage over the prior art in that it is not necessary. Further, according to this process, there is no need for voids to be generated on the periphery of the chip where the existing wiring bonding pads are generated. Instead, such instant processes can be further localized and performed at a sufficiently low temperature such that the circuit can be formed on or embedded in the semiconductor prior to the formation of the via and the via can be placed in an area other than the periphery of the chip . Thereby, the process can be used without having to include the process in the design process of chips manufactured by other manufacturers, and a connection path can be formed between the devices on different chips as described in more detail below, Can be formed much shorter than when using a pad. Also, as described in detail below, the process can easily form a path through the wafer, so the process is very useful for forming chip-stack or mix-and-match chip units.

With regard to the process of filling the electrically insulating material into the trench, the problem of pinholes, bubbles, or other defects in the electrically insulating material can occur, especially when the trench is narrow and relatively deep (e.g., 100 microns or more in depth) . If such defects remain, undesirable conductive paths may be created between the doped semiconductor material of the device through which the trenches penetrate the device and conductors are formed therein.

Fortunately, in the event of such potential problems or concerns, such problems or concerns can be practically solved by applying other variants shown in Figs. 17-23.

Fig. 17 is a simplified cut-away view showing part 100 of Fig. 5 as a result of processing according to another variant as follows.

The via trench 1700 is formed as shown in FIG. 7, but unlike FIG. 7, the entire island 306 of the semiconductor material 122 in the annular portion 704 of the insulating material 500 is not removed. The via trenches 1700 are smaller than in the case of FIG. 7, leaving a perimeter annulus volume 1702 of the semiconductor material 122. The main volume 1702 of the semiconductor material 122 is electrically isolated from the semiconductor material 122 of the device 104 because it is bounded by the insulating material 500 and the substrate 112. [ Any defects in the insulating material 500 within the trenches 302 can also be prevented by the bulk volume 1702 of the semiconductor material 122 from forming a metal within the via 1700, It will be isolated from the source. Otherwise, the above method is the same as that described in Fig. 7, the via trench 1700 may be etched through, for example, additional etching or other suitable processing, for example, through laser drilling to a depth 1704 in the substrate 112 So as not to completely penetrate the substrate). The side walls 1706 of the via trenches 1700 as well as the bottoms 1708 of the via trenches 1700 will all be electrically non-conductive, as described above, while the via trenches 1700 are formed, Will be an insulated semiconductor material 1702 surrounded by the annular insulating material 704. [

Figure 18 shows a cross-sectional view of an embodiment of the present invention after forming a via trench 1700 in a loop of a semiconductor material 1702 whose boundary is defined by an electrical insulating material 704 as shown in the side view of Figure 17, Sectional view taken along the line AA in FIG.

FIG. 19 is a simplified cutaway view showing part 100 of FIG. 5 as a result of further performing the metallization process for another modification of FIG. 17 in the manner described with reference to FIG.

FIG. 20 is a simplified cutaway view showing part 100 of FIG. 5 as a result of further performing the metallization process for another modification of FIG. 17 in the manner described with reference to FIG.

FIG. 21 is a simplified cutaway view showing part 100 of FIG. 5 as a result of further performing the metallization process for another modification of FIG. 17 in the manner described with reference to FIG.

FIG. 22 is a simplified cut-away view showing part 100 of FIG. 5 as a result of thinning the substrate so that the lower metallization 1502 is exposed in the manner described with reference to FIG. 15 for another modification of FIG.

23 shows a portion 100 of FIG. 5 as a result of thinning the substrate so that the lower metallization 1502 is removed and the bonding material 1102 is exposed in a manner described with reference to FIG. Fig.

Based on the above, it is possible to form additional variants with double insulated conductors (i.e. coaxial conductors). According to this variant, the dual conductor enables a greater contact density, thereby reducing crosstalk, which is advantageous. Also, as will be seen below, according to the dual conductor variant, the outer conductor can be electrically separated from the inner conductor and driven to a different voltage, and one conductor acts as an electromagnetic interference To protect it from signal noise, or signals may propagate differently through the structure so that low noise data transmission can occur. Further, similarly to the single conductor method, a precision etching treatment defined by a single lithography method is performed to form an annular trench. As will be seen below, the removal of the center material is controlled by the boundary metal and does not suffer from the steps defined in the photorefractive process or the process changes inherent in the etch process. Therefore, this method is more reproducible and has high process robustness.

Two coaxial modifications will be described below with reference to Figs. 24 to 29B. This modification is suitable when the outermost conductor can be in direct contact with the semiconductor material without adverse effect. Next, various other examples of coaxial deformation will be described with reference to FIGS. 30A and 30B. Other dual conductor variants of Figs. 30A and 30B are similar and improved to the other variants shown in Figs. 17-23, and are equally suitable for substantially solving the same problem or concern.

For the first time, the basic dual conductor formation process follows the manner described with reference to Figs. Since this modification is implemented on the basis of the foregoing description, only additional or different aspects related to this modification will be described in order to simplify the explanation, the rest being apparent from the foregoing description. Then, the processing according to another variant of the above-mentioned dual conductor is as follows. First, as shown in Fig. 24, at least the side wall 304 of Fig. 3 is metallized (2402) as described above. The lowermost end 2400 of the trench 302 may be metallized or not metallized, but this will not affect the final result, as will be apparent from the following discussion. Fig. 24 is a simplified cutaway view showing part 100 of Fig. 3, immediately after metallization according to this variant.

After the metallization process, at least the trenches 302 are filled with the electrically insulating material 500. The results of this step are shown in Fig.

Referring again to FIG. 26, the via trench 2600 is formed by removing the entire island 2406 of the semiconductor material 122 bounded by the inner periphery of the annulus 2602 of the metallization 2402.

Alternatively, as shown in Fig. 27, a method similar to that shown in Fig. 17 may be applied at this point. That is, instead of removing the entire island 306 of the semiconductor material 122 inside the annulus 704 of the insulating material 500, only the inner portion is removed so that the annular ring volume 2704 of the semiconductor material 122 remains (2702).

Otherwise, then the scheme will be substantially the same as described above. The via trenches 2600 and 2702 may be etched to a predetermined depth (preferably through the substrate completely), for example, through additional etching or other suitable processing, for example, by laser drilling or removal .

The via trenches 2600 and 2702 are then filled with the conductor 2802 and the substrate is thinned as described above. In the case of the first dual conductor variant (Fig. 28A), the bottom metallization is removed as shown in Fig. 28B and the thinning process is performed until the inner conductor 2802 is exposed on the substrate 112. In the case of the second dual conductor modification (Fig. 29A), the thinning process is performed until the lowermost portion of the metallization is exposed along the inner conductor as shown in Fig. 29B. 28B, one of the conductors is made of the outer ring of the metallization 2804, and the other is made of the inner ring and the inner conductor 2802 of the metallization 2804. The reason for this is that in the modification of Fig. 29B, one of the conductors is made of the conductor 2402 and the other is made of the inner conductor 2802, while the two are short-circuited.

Thus, in the dual conductor variant, as shown in FIG. 28B, it is further preferred that the depth of the annulus 704 and the depth of the via trenches 2700 are both deeper than the point at which the substrate is finally thinned. That is, if the total thickness of the wafer is 500 microns and the wafer substrate is thinned by 200 microns, the depth of the via trenches 2700 will be at least 300 microns and the sum of the possible metallization thicknesses, Would have to be deeper than the via trenches 2700. [0060] The reason for this need is that electrical insulation is required between the two conductors. Also for that reason, in some implementations, failure to apply the lowermost portion of the trench 302 is negligible because it is removed in the thinning process.

It should be noted that, on the basis of the foregoing, it is possible to form additional other coaxial variations similar to those of Figs. 28b or 29b by simply making the sidewalls of the trenches non-conductive prior to metallization. This variant can be implemented, for example, by dielectric sputtering, plasma deposition, or by applying a thin dielectric film to the sidewall, either by forming the initial ring trench in advance (i.e., prior to electronic device fabrication) and using thermal or steam oxidation techniques . This technique involves a step of exposing the sidewalls to a reactive gas to form a thin silicon dioxide film on the sidewall surface in the case of silicon wafers, where the sidewalls are oxidized (conceptually equivalent to rusting the iron). A general overview is that oxidation of silicon can be performed in a steam environment according to the Deal-Grove model. Oxidation can occur in this manner in a highly controlled and reproducible manner. Similar processes can be used to form an oxygen nitride film or a silicon nitride film. According to this variant, there is an advantage in that the oxide film is not deposited but grows thermally, so that it is not uniformly formed and does not cause problems inherent in applying a liquid viscous paste or other type of dielectric. In addition, a very uniform and highly controllable dielectric film is formed over a 12-inch silicon wafer with a thickness of more than a millimeter and a very precise tolerance. Further, according to this step, the effect of smoothing the sidewall is obtained, which further contributes to the uniform metallization.

Of course, this additional variation may be inadequate due to the permittivity of silicon dioxide, silicon oxynitride, or silicon nitride in some applications, and may not be possible in other applications due to other factors not relevant to understanding the gist of the present invention . In addition, the above method is the same as that described in all of the above-described modifications with reference to Figs. 24 to 29B.

For complete understanding, examples of adding feature processing of the above-described selective, additional thermally-formed dielectric or insulator 3002 to the method of Figs. 28 and 29 will be described with reference to Figs. 30A and 30B, respectively . In some variants of Figure 30B, in a variant in which only a part of the inner islands is removed so that the annular portion of the semiconductor material remains around the via trench, the process may be applied to the device previously formed in or on the chip, It is possible to carry out the above-described characteristic processing before the device is formed, or after the appropriate measures have been taken to prevent the process from being damaged in a device previously formed on the chip, It is possible to use the thermally formed dielectric scheme described above to form a dielectric film on the remaining ring.

Alternatively, the partial removal process may be an inverse partial removal. That is, by removing the inner island from the via trench inwardly, it is possible to leave a smaller island inside the via trench. According to this variant, the small island may act as a post on which the contacts are constructed and connected to the metallization or conductor. Similarly, the partial removal process can be used as a water conductor in a male or female conductor, or, if it becomes conductive, to partially remove it from the depth side so as to leave a well or depression that can serve as an electrical contact .

As a result, while taking the same approach as in Fig. 28B but performing the thinning only until the extent shown in Fig. 28A (i.e., until the metallization material at the bottom of the trench is completely removed), three conductors That is, a three-axis) variant can be constructed. These three conductor modifications allow the outer metallization to act as a barrier between the inner metallization and / or the semiconductor and the semiconductor material that supports the conductor and the nearby device, and between the outer metallization and the inner conductor There is an advantageous effect since the metallization can serve as a barrier or a third conductor between the two. Thus, the three-conductor variant itself has several different effects. Of course, all of the options described to be used with any one of them (i.e., thermally formed or applied), in view of the single conductor, the two-conductor and the relationship between the three- , Void space injection, post and penetration contacts (described below), etc.) can generally be mutually applied to each other.

As outlined above, it is unnecessary to fill any remaining empty space after removal of the central island material with anything. In addition, some implementations described in the present invention have certain effects on not doing so.

32 illustrates a method of bonding the chip 102 to the electronic chip 3200 such that the contact pad 3202 on the electronic chip 3200 to be electrically connected to the upper contact 904 of the laser 104 is below the void space 3210 Is a simplified cut-away view illustrating a portion 100 of a chip implementation disposed on an electronic chip 3200. FIG. The embodiment of FIG. 32 is similar to the embodiment of FIGS. 9-16 except that the empty space 3210 remaining after metallization is not filled at all. A solder bump or other softenable and deformable electrically conductive material 3204 is placed over the contact pad 3202 and this portion of the two chips 102 and 3200 can be physically < RTI ID = 0.0 > As shown in FIG.

33 shows a state in which the chip 102 is joined to the electronic chip 3300 such that the contact pad 3302 on the electronic chip 3300 to be electrically connected to the upper contact 904 of the laser 104 is below the empty space 3310 0.0 > 100 < / RTI > of another chip embodiment disposed on top of the electronic chip 3300. FIG. The embodiment of FIG. 33 is similar to the case of FIG. 23 except that empty space 3310 left after metallization is not filled at all as in FIG. A solder bump 2404 is placed over the contact pad 3302 and is used to physically and electrically bond this portion of the two chips 3302 and 3300. [

By not filling the empty spaces 3210 and 3310 in the embodiment of FIG. 32 or 33, the capillary action can be used to pull the solder 3204 into the voids 3210 and 3310 and the deformable material 3204) can be deformed to enter the empty space, thereby a) ensuring excellent electrical connectivity, and b) helping to align the chips.

Figs. 34 and 35 show cross-sectional views of Figs. 32 and 33, respectively, after the chips are coupled to each other. As shown, the solder 3202 is placed in contact with the contacts 3206 and 3306 of the chip, with the contacts 3206 and 3306 of the chip being relatively centered on the contacts 3202 and 3302 of each electronic chip 3200 and 3300, 3210 and 3310 of the first and second openings 3210 and 3310, respectively.

As shown in FIG. 36 for the embodiment of FIG. 34, an insulator or a conformal coating 2800 may optionally be performed (although substantially the same applies to the implementation of FIG. 35 (not shown)).

As mentioned briefly above, regardless of the variant used, the above-described annular trench can take any closed form (as well as the perimeter of the semiconductor material if the variant is used). However, as an extended concept of the above, it is not necessary for the via trench to take the same form as the annular trench, although it takes the same form in most implementations to facilitate implementation as well as capacitance or resistance, It should be noted that the width of the trench does not need to be uniform. Figures 37A-37F illustrate several representative examples of the cross-section of an annular trench to illustrate this point. 37A, the annular trench 3702 is shown as a triangle. As a result, the width 3704 of the trench 3702 is greater at each point 3706 than the sides 3708 of the triangle. 37B, the annular trench 3710 is shown as a rectangle. As a result, the width 3704 of the trench 3710 is greater at each edge 3712 than at the respective sides 3714 of the rectangle, and the longer sides 3716 are farther away than the shorter sides 3718. 37C, the annular trench 3720 is shown to be delimited by two different ellipses. As a result, the overall width of the annular trench 3720 varies with position. 37D, the annular trench 3722 is shown as a square. As a result, the width of the trench 3722 is larger at each corner than at each side, but the sides are equally spaced from each other. 37E, the annular trenches 3724 are shown as being rectangular in the outer periphery 3726, but circular in the inner periphery 3728. [ 37F, the annular trenches 3730 are shown as being rectangular in the outer periphery 3732, but are square in the inner periphery 3734. 37G, the annular trench 3736 has a concavo-convex shape (or a kidney shape) in which the outer periphery 3738 and the inner periphery 3740 are reduced / enlarged at a constant ratio with respect to each other, and the width of the trench is constant Do. 37H, the annular trench 3742 has an outer periphery 3744 similar in shape to that of FIG. 37G and an inner periphery 3746 that is hexagonal.

The concept extended from the above can be similarly applied to a modification having a ring made of a semiconductor material. That is, the shape of each of the peripheral surfaces can be the same as the others, and one or more major surfaces can be made different from one or more other major surfaces according to requirements or needs in a particular application.

In addition to the effect originally obtained from using the above-described method to finally form the connection between the two chips, the above-described approach has a great effect on the area of the chip, die or wafer stacking. From a functional standpoint when a chip, die or wafer is pre-fabricated, for example, any devices that function in terms of transistors, capacitors, diodes, switches, resistors, capacitors, etc., Especially when fully formed.

By forming the vias using the annular via process, a method is achieved which allows the wafers to be laminated in such a way as to obtain electrical conductivity and after the wafer is melted, little or no subsequent treatment is required. This is very effective in terms of cost and yield, and is particularly effective at the wafer level, especially when two wafers are combined or a wafer is arranged with several individual chips. When joining the wafers, one of the main realizations is that the combined two-wafer pieces (after joining the two wafers) have a much higher value than the single-wafer pieces (one wafer just before joining) . Similarly, when three wafer pieces are stacked together, the value becomes much higher. Any post-treatment that is done after the integration of the stacked series of dies adds an extraordinarily high risk because the damage results in the destruction of very large added fragments.

Therefore, according to the above-described processes, a much better method is obtained because the via processing and the thinning are performed before lamination. As a result, it is possible to form completely laminated ready pieces and to allow one piece to be placed to join (i.e., bond) onto the other, without additional wafer processing, and after formation of the on- Is completed. As the chip is laminated in the manner described above, the number of steps of attaching the other layer (i.e., another die) is increased as the value of the combination rises (i.e., thinning has not been necessary and thinning has been performed prior to bonding) Is generally only one. This minimizes the risk of yield loss for expensive parts due to the inherent post-processing inherent in conventional stacking schemes in which chips are stacked and subsequently form electrical contacts.

Thus, compared to the prior art, forming vias prior to lamination makes it possible to:

1) there is no or less post-treatment on the laminated pieces (thus, labor is less and yield is increased);

2) Unlike conventional stacking methods where the alignment tolerance is very large (ie, all the pieces must be aligned in common for the pieces on the floor, each chip needs to be aligned only on the immediately underlying chip ).

38 is a diagram showing a general outline of a process of preparing a wafer to be laminated in a simple form. Figure 38A is a simplified representation of a portion of an initially fully formed wafer and, in particular, an apparatus 3802 and its lower substrate 3804. The general process is as follows. First, a material 3806 is deposited on the device side of the wafer (Fig. 38B). The material 3806 and underlying portions thereof for contact are etched to form a trench 3830 (Fig. 38C). The wall 3810 of the trench 3808 is isolated 3812 to prevent the possibility of the doped semiconductor material shorting to the contact to be formed (Fig. 38D).

Instead of this treatment, the material 3806 can be formed automatically during the deposition of the insulating layer 3812. [ For example, TEOS is placed on the wafers by removing the first stack of material 3806, etching the trenches 3808, and then laminating TEOS (oxidizing material). Because of the manner in which this material is deposited, a 2.5 micron material is placed on top of the wafer and 1.25 microns is placed on the wall in the trench. Thereby, another way of obtaining a thick upper layer at the same time as covering the wall of the trench is obtained. That is, in this manner, the process of placing the material 3806 as a separate step may be omitted or used with the remaining steps in accordance with the topology of the wafer.

A metal 3814 is then injected into the trench to provide a seed layer for plating the conductor (Figure 38e). The remaining via volume is then filled with the metal 3816 to be the conductor (Fig. 38F). The extra metal (and optionally the insulating layer 3812 and a portion of the metal 3806) is then removed, for example, by chemical or mechanical treatment or any combination thereof (FIG. 38g). The wafers are then etched to form openings 3820 and 3822, thereby allowing access to the naturally existing contact portions 3824 and 3826 (Fig. 38H). The metals 3828 and 3830 are then applied to interconnect the existing contact portions 3824 and 3826 with the contacts 3832 and 3834 formed by the new process (Fig. 38i). The rear portion 3826 of the wafer is then thinned to expose the other end of the processed contacts 3832 and 3834 and optionally the insulating portion 3812 at the bottom of the trench 3808 is removed ). The rear portion 3826 of the wafer is then etched to form elevated posts 3838 and 3840 and the insulating portion 3812 is removed from the bottom of the trench 3808 (Fig. 38K). Instead of this treatment, in some embodiments, the insulating portion 3812 may be partially removed or, if it is not required to be electrically conductive (for example, when used to simply align or form a non-conductive post-shaped connection) It may not be completely removed. Finally, if the exposed fill material to be the post is of a type that can oxidize or cause a reverse reaction to the later formation of the connection, then the optional barrier layer 3842 may be deposited on the raised posts 3838, 3840 To prevent oxidation or other reverse reaction other than the above.

According to yet another variant, after applying a soft or malleable material to the top of the metals 3828, 3830 to protect the metals, the steps of Figs. 38j, 38k, and 38l, ). According to this modification, it is possible to reduce the number of steps that must be performed after thinning the wafer.

At this point, a general through-chip connection is formed, which facilitates stacking on a chip, die or wafer substrate and allows one or more wafer units to be formed.

Figs. 39-41 are views generally showing certain portions of chips stacked to form such a unit after being fabricated to form through-chip connections using other variations of the above-described processes. Particularly, FIG. 39 shows corresponding portions 3900 of a series of stacked chips interconnected with each other using a modification of the basic scheme. 40 is a view of corresponding portions 4000 of a series of stacked dual conductor deformation chips. 41 is a view of corresponding portions 4100 of a series of stacked tri-conductor deformable chips. By using one of the processes described in the present invention, it is possible to form stacks and units from wafer parts that do not need to be configured in a coplanar or fully overlapping fashion, yet extend vertically From the above description.

Within each of the three stacks of Figures 39-41, the optional contact pads 3902, 4002, 4102 and 4104 are in the state of being added as standoffs, thus providing adequate clearance and good electrical contact between the wafers .

Depending on the particular application in which the above-described approach is used, the contact can be formed in a variety of ways. For example, the vias described above are formed by micro-bumps thereon by a conventional C-4 solder type process such that two points to be electrically connected are brought into contact, the solder is turned into a liquid phase, Physically and electrically coupled. According to another variant, a pair of contacts, one of which is rigid and the other is relatively flexible, can be used and the two can be combined using the process described in the present invention. According to another variant, both of the contact pairs can be formed with a flexible material thereon, and the two can be combined using an appropriate process as described in the present invention or other techniques. Alternatively, conventional post and socate type schemes may be used. According to this approach, the two contacts are either slightly larger relative to the socket than the socket, or the socket is slightly smaller than the size of the pod, resulting in an interference fit between the two, Is taken as a complementary form.

In either case, it may be preferable to use a thick wafer (Fig. 42A) to secure strength during handling. If the wafer is particularly thick and the diameter of the desired via is less than about 1/20 to 1/30 of the thickness of the desired wafer, then some variants may be adapted to a thicker wafer using a different process. The process of forming such " rear-to-front " vias is shown in a simplified form in Figures 42B-42E. First, the rear side of the wafer supporting the device is etched to form a via (Fig. 42B). The via is then electrically conductive through one of the processes (such as a single conductor, coaxial, triaxial, etc.) or other predetermined process, such as inserting a previously formed post, as described herein 42c). In this way, the result is that the rear side has either a soft material or a rigid post material. Then, across the conductor, from the top (at the front or device side) down to the point at which the bottom of the backside conductor ends, are etched to form corresponding vias (Fig. 42D). Optionally, the front side devices may then be protected and, if so desired, contact or rerouting (not shown) may be performed on the devices using, for example, , The via is made conductive in substantially the same manner as that used for the rear side (Fig. 42E). According to some variants, the material at the bottom of the rear side conductor can serve as the etch stop film and / or as a seed layer for plating the conductor from the front side. Thereby reducing the number of processing steps compared to the method used to form the conductors on the back side. Further, according to another variant, in the case where it is desired that there is no physical connection between the conductor from the rear via and the conductor from the front via, it is preferable that, in the state where the connection is made through the capacitive coupling, An appropriate amount of wafers may remain.

This method can be applied together with the existing two via forming processes in which a single via is formed and the insulator and the metal are stacked in one hole, or the above-described process of the present invention is applied together with the annular via method, Thereby forming an impedance via.

Also, on one side there is a void that is not fully filled, so that the unfilled portion of the via serves as a " slot " for receiving a " post " (i.e., a pressure or interference fit connection) When it is possible to achieve physical connectivity, a rear-to-front scheme can be used. This type of pressure or interference fit is shown in Figure 42f.

According to another variant, a rear-to-front via formation method as described above can be used to form a connection partly passing the chip in such a way that the capacitive coupling can be used for data transfer between the chips. Capacitive coupling operates when the contacts are close and the density of the connections is limited by the crosstalk, so variations of the schemes described in the present invention are ideal for forming chips using a communication type. These schemes can minimize the distance between the contacts using coaxial or triaxial posts so that the shielding means is provided, so that crosstalk due to close connections can be minimized easily. Capacitive contacts also have the advantage that there is no need for substantial electrical contact between the parts. 43A-43D, the via is close enough to the contact on the top of the chip to be physically removed from the contact, but when it is filled, the capacitive coupling of the signal applied between the filler material and the contact (See FIG. 43B) so that the vias are sufficiently close to allow for the formation of the vias. This via is then filled with a metal stud and a single conductor, coaxial or triaxial conductor to obtain good capacitive coupling (FIG. 43C). In this way, it is possible for the wafer to maintain the overall thickness of the connections so that they have adequate distance and sufficient strength for wafer handling. This approach has the additional advantage that a laminate can be produced by laminating the back side of one wafer to the front side of another wafer. In this way, multiple stacks of chips (i.e., stacking of three or more chips) can occur as shown in FIG. 43D. The way the chips are not facing forward and back but facing forward and front is that the third chip is placed behind one of the other two chips and communicates through the entire wafer to avoid the possibility of crosstalk This is in sharp contrast to the above-mentioned method in that it is not easy to cause chip stacking easily since it is necessary to have a low contact density. Of course, according to the method described in the present invention, coaxial or triaxial vias can be used to improve the signal blocking property in order to prevent crosstalk.

Also, for example, in the case where two vias are not connected to each other and a true rear-to-front connection is not made (i.e., the material remains between the vias and the rear side posts formed from the front side) Capacitive coupling can be used with a pressure-fit connection. In this case, the front side via will be formed independently as a rear side via according to one of the variations described in the present invention.

Also, capacitive coupling may occur between one or more contacts on the chip surface (whether formed via a via or other manner). This approach can be used, for example, because there is a chip or metallization between two complementary contacts, or because it remains isolated by another structure, or because one or both of the two are insulators, such as TEOS, It is preferable that the height of the chip is such that the height of the chip is not so easy to physically contact due to the topology even though two complementary contacts are close to each other due to the lamination method can do.

  From the foregoing description, it is to be understood that the various functions of the method of the present invention will be more clearly understood. It is also possible to form another variant which represents a wide variety of possibilities which can be achieved using the inventive schemes. One such variation is shown in Figures 44A-44I. This method may be used in a " pre-connect " variant where a pre-formed lower wafer 4402 (hereinafter "Quot; wafer ") because it attaches the wafer to be processed to the wafer. In this variant, any of the basic connection forming processes may be used. This deformation process is performed as follows.

First, the initial wafer is thinned to the extent necessary to allow the vias to fully penetrate the substrate (Fig. 44A). This step is optional and need not be performed if the particular etch process to be used can penetrate the entire chip without difficulty. Then, the initial wafer is aligned (Fig. 44B), using a bonding material or wafer fusing, or attached to the base wafer using covalent bonding if the wafers are very flat (Fig. 44C). Next, an annular via is formed in the initial wafer over the pads of the base wafer, so that the annular via extends down to the base wafer to surround the desired pad on the base wafer (Fig. 44D). The thus formed annular via is then filled with an insulator such that the subsequent conductor deposition is insulated (Fig. 44E). Subsequently, all or part of the center post is etched down to the desired pad on the base wafer to form a void on the desired pad of the base wafer (Fig. 44F). Finally, the void space is metallized (Fig. 44G), and optionally the void space is filled completely with conductor (Fig. 44H) using one of the schemes described in the present invention, If the center is not fully filled, it can be filled with an insulator (Fig. 44i). As a result, the metal connection causes an electrical connection to the base wafer, effectively extending the base wafer pad through the initial wafer, so that the two chips are physically coupled. This approach has the advantage that the center post of the semiconductor material can protect the pad of the base wafer so that the insulator does not interfere with the base wafer pad. This is significantly different from what would be obtained if the same approach was used to perform the same work using existing methods, as the base wafer could be contaminated by the applied insulator leaving the base wafer exposed.

However, in some cases, the pressure fitting connection may not be appropriate due to the lack of control capability. In such a case, a method referred to as " post and penetration " may be used as another alternative method according to the present invention. Ideally, post and penetration will be available and mainly used with the tack and fuse process, as there is another advantage when used with the advantages of post and penetration and the "tack and fuse" process, respectively .

This approach uses a combination of two contacts: a rigid "post" contact and a pad contact that is relatively flexible (as compared to the post material). In some cases, one or both of the two contacts have a lower rigid support structure or standoff. Briefly summarized, one of the two contacts is a contact made of nickel (Ni), copper (Co), or palladium (Pd) or other suitable rigid alloy as described herein. This contact acts as a "post". The other of the two contacts may be configured such that when the two contacts are gathered by pressure (by force externally applied, or by force, for example, caused by bending the wafer), the post penetrates the flexible material (The " post and penetration " portion), when heated to a temperature above a predetermined temperature (tack during the tack and fuse process) and cooling down to a temperature at which either of the two contacts will not become liquid, So that they can be joined together.

As used herein, the term liquid phase means that the stated metal or alloy is in a fully (or substantially completely) liquid state. When the metal is in a non-liquidus or semi-liquidus state, as used in the present invention, the metal is sufficiently soft to be able to adhere as described above, Or in a liquid enough to move or flow as if it were in a liquid state. Most variations of the processes of the present invention are applied with metals or alloys in the non-liquid and non-solid state. That is, a variation according to the process of the present invention is applied between a solid (complete solid) temperature and a liquid (perfect liquid) temperature on a phase diagram for a metal or alloy, . As shown in FIGS. 33 to 36, this difference will be better understood with reference to coupling a chip to another device, for example. In these figures, if the material 2404 is a solder (metal or alloy) in a liquid state, then the chip will float on the molten solder and the capillary action pulls the solder toward the vias 3210 and 3310 Accordingly, the vias 3210 and 3310 will be centered on the solder ball themselves. In the non-liquid or semi-liquid state, such as that used in most variants of the tack and fuse process described in the present invention, during periods of both tack and fuse, the metal or alloy is very ductile (i.e., Liquid state), there is not enough liquid to float the chip or allow the vias 3210 and 3310 to be centered by themselves. Thus, it is necessary to apply some force (whether external force or force from the weight of the chip without external force) to allow the metal or alloy to enter the vias 3210, 3310.

Thereafter, the second heating (the melting step of the tacking and melting process), which raises the temperature to a temperature higher than the " tack " temperature, causes the solder The materials are mutually diffused each other.

The tack and fusion bonding process is divided into two main parts: an "attachment" or "tack" step and a "fusion" step. The tack step allows a very uniform electrical connection between the tack pairs. Combining the formation of post and penetration bonds with the tack bonds allows any surface oxide on any of the contacts to be easily penetrated. This non-oxide inhibited contact allows a simple fusing process without the need to apply strong pressure. In the absence of a combination of post and penetration and tack steps, in order to allow the contact to penetrate the oxide formed on the surface of the rigid and malleable material either during the hot part of the tacking process or in the initial stage of the melting process, Lt; RTI ID = 0.0 > substantially < / RTI > By passing such an oxide " crust " through the initialization of the tack phase, the frit stage occurs at substantially lower pressures, and in some cases the frit stage occurs without adding more pressure than the chip itself.

At this point, we will define other terms. As used herein, the terms " daughter " and " mother " are terms that are conveniently used to denote whether a particular contact on a wafer is rigid or soft, and the term " mother " And the " daughter " is associated with a soft contact. It should be noted that although the present invention has been illustrated in a fairly consistent one-sided fashion, the terms " mother " and " daughter " The contacts on each wafer may be either rigid or flexible, provided that the corresponding contacts on the other wafer to be coupled are of the opposite type. Thus, one or the other type of contact may be exclusively present on a given wafer surface, and in some variations, both types may be mixed on one wafer side. However, depending on the application example, problems may arise if a type is mixed on one surface. In such an application using the same, different types may be limited to a discrete region without mutual mixing in one region, Mixing the types on a single surface complicates the process unless it involves only one contact type so that the area containing the other type can be easily protected when certain processing steps are performed.

During the attachment or tacking of such a process, " daughter " chips are placed on a " mother " wafer. The mother wafer is maintained at a single temperature. That is, the mother wafer is maintained as an isothermal substrate during the deposition process. If the isothermal temperature of the mother wafer is increased to room temperature or higher, the speed of the adhesion step of the above process can be increased, but the isothermal temperature of the mother wafer can be lowered to about room temperature. However, not only the tack or fusion temperature but also the isothermal temperature are maintained below the melting point of the soft material on the daughter chip. Thus, when two chips are brought in contact to create post and penetration connections, the small daughter chips are each heated to a high temperature such that the interface for that very chip will reach or exceed the appropriate " tack " temperature A tacking process can be performed. Generally, for the main materials mentioned in the present invention, the tack temperature is between approximately 190 ° C and approximately 320 ° C, and a typical typical tack temperature is approximately 270 ° C. In this way, the contacts of other chips on the mother wafer can change the performance of that contact, and some of the contacts are subjected to the elevated temperature for a much longer period of time than the other contacts, Is not heated beyond the point at which the contact of the other chips will experience a non-uniform performance.

The tacking or adhering step is carried out, for example, by maintaining the mother wafer at an isothermal temperature lower than or equal to the lower end temperature, bringing the daughter chip to the mother chip at a lower temperature than the lower temperature, bringing the two chips into contact, Lt; / RTI > to a suitable tack temperature. Thus, once a daughter chip is attached to a mother wafer, the machine arranging and heating the mother chip (heating the daughter chip) will only require sufficient pressure to allow some contact between the components (e.g., A pressure of 2 g or less, preferably a pressure of 1 g per pair of contacts), the pressure is released from the daughter chip.

After release, the cap / tack layer on the daughter chip (or, if the soft material also performs the function of the cap / tack layer, the soft layer) is at a reduced temperature It becomes less flexible. For example, for the baseline materials described herein, the mother chip / wafer substrate can be maintained at a temperature of about 230 ° C to 250 ° C, and the daughter chip can reach the mother chip at a nominal temperature of about 270 ° C , And after the temperature rises rapidly and the contact is made, the temperature rises to approximately 310 ° C to 330 ° C. The order of contact for rapid temperature rise (i.e., whether it occurs before or after contact with the mother wafer) is variable. Clearly, the present inventors have found that, by first contacting the chips and then raising the temperature, oxide formation on the surface of the malleable material is minimized, thus allowing more reproducible contact. Preferably, the use of a soft material can reduce the amount of pressure in the unit contact pair. The inventors have determined that the range of pressure applied to the unit contact pairs is approximately 0.001 g to 10 g, although the lower range is possible, and the lowest pressure is the effect of gravity on the mass (i.e., weight) of the chip itself .

In addition, as noted above, in the case of a tack process, a daughter wafer temperature as low as room temperature can be used if sufficient pressure is applied to break any surface oxide. In this way, the daughter chips can be mounted on the entire mother wafer before the tack state begins. Even with this method, due to the speed at which the process takes place, the mother wafer does not have time to be heated to a significant degree. Thus, the attachment of the second daughter chip to the mother wafer does not soften the cap / adhesive layer of the first chip, even when the size of the first chip in the horizontal and vertical directions is within 100 microns, It is not possible to perform the sorting.

Preferably, both tack and fuse processes are typical non-liquid phase processes. This means that the process is performed to make the soft material significantly soft, but does not change to a fully liquid state during the tack or fuse process. The reason is that if the malleable material is in a liquid state, there is a great risk that a resulting liquid will flow and cause a short in an adjacent contact portion. By keeping the materials in a non-liquid state, a greater contact density can be achieved. However, in some variations, a semi-liquid state can be tolerated (i.e., a portion of the malleable material, which is not significantly less than the entirety, may be temporarily in a liquid state). However, in these modified examples, a liquid-state soft substance is confined in a limited region in order to avoid a possibility of short-circuit at an adjacent contact portion, for example, when a pad to which a soft substance is applied is a non- Generally have common features that use some other type of constraint mechanism to prevent liquid soft materials from causing side effects by allowing them to be surrounded or covered by their surroundings.

In some variations, with respect to the "tack" state of the tack and fuse process, a soft material (e.g., Sn) that is melted at a lower temperature to assist in accelerating the tack time to improve yield, (Such as Au / Sn alloy) may be desirable to cover (cap treatment). In addition, in some variations, the temperature of the bond may be increased so that deterioration of the bond does not occur when the chip is mounted at that temperature for extended periods of time under uncontrolled environmental conditions (i. E., The time required for the chip to mount on the entire wafer) It may be desirable to maintain the mother wafer at an isothermal temperature of the highest possible temperature below. Although the temperature may be higher to speed up the process speed, we typically use a temperature of 230 < 0 > C. The effect of the lower temperature is a change in the temperature and pressure profile of the penetration state of the attachment. Moreover, in order to speed up the processing speed, it is desirable to have a series of processes (i. E., Position and heat) take place as quickly as possible. Another aspect to be noted is that, in some variations, the longer the time spent in the tack, the less and less the critical influence of the state of the melt on yield and the like. For example, at one extreme on FC150 (silicon-to-silicon), we have a tack that lasts for about one minute, and no fused state is needed. This is summarized in FIG.

In another extreme, in the case of a solid, alignment is typically made for about one second, and the tack state is maintained for two to four seconds before the fuse state. Thus, in these variations, the environment for the transition from the tack state to the fused state may be important for obtaining good contact.

Between these two extremes, there is a continuum of process options where adjustment is made between 1) throughput of the fusing process, 2) complexity, and 3) criticality. In the case of a very fast tack process of 2 to 4 seconds, the chips may be held light and thus require a reduced environment during the melt state or may require a substantially greater amount of applied pressure during the melt state. At the other end of the spectrum, a one minute tack process is performed at a higher pressure and temperature, and the tack itself performs a relatively good function of the preliminary "fuse work" of the chips. In this case, the subsequent "fuse" process may simply be a contact anneal in combination with a method of ensuring consistency across the wafer, and in certain circumstances (or when the flatness of the chip placement during the ' , Specific pressure). This continuum is illustrated in Fig.

A significant advantage associated with the tack state is that the inspection of the chip can be performed after the tack process is complete but before the fusing process is started, since the electrical connection is not final and can be easily restored. This means that through the inspection and identification of the bad die before and after the first state of hybridization, the individual chips that were being performed prior to hybridization to another chip were adversely affected by the hybridization process, It is possible to make a judgment as to whether or not there is an effect in the combination of Furthermore, when the cutter daughter chips are mounted on the uncut mother wafer, the inspection can be performed before the mother wafer is cut or cut.

Another significant advantage associated with the use of the tack state is that the chips are very tightly coupled so that if a subsequent check determines that one of the combined chips is not being performed, . The work of separating the two chips can be done using heat or pressure, or both heat and pressure. In the case where individually cut-off daughter chips are mounted on a cut or uncut mother wafer, if one daughter chip has a problem, another "good-known" daughter chip may be attached to the mother wafer. It can be noted that when a particular mother wafer chip is bad, it is no longer attached to the daughter chips and it is easy to discern the operation of cutting the wafer immediately afterwards in two cases, which significantly increases the overall yield. In addition, if the mother chip is not functioning, the already removed daughter chip can be retained for later attachment to the mother chip, thereby increasing the yield and potentially reducing the cost. For example, assuming that the soft contacts of the daughter wafers are made of gold-tin or gold-silver-tin alloy and the flexible cap is made of tin, the tin can be deposited at low temperatures, It does not expand like. As a result of the test, if the daughter chips are defective, the individual chips on the mother wafer are heated, dropped off, and another daughter chip is attached. If all the daughter chips are attached and the test results show good bonding, the entire mother wafer is fused together.

Thus, the tack and fuse method allows only the use of one integrated well-known die. In addition, this method significantly reduces the risk associated with stacking multiple dies, since it does not require slicing the entire stack due to a single bad chip. When chips and stacked units are expensive, this is an inherent and naturally significant advantage.

Moreover, tack and fuse conditions provide another advantage in that the process can be performed at low pressures. The forces used in tack and fuse conditions are typically less than 2 g per unit contact pair of contacts on a pitch of 50 microns or less. In the fused state, the inventors have demonstrated that a force of 0.8 g to 0.001 g per unit contact pair is used. For 400 contact chips, we used 300 grams, and for 10,000 contact chips we also used 300 grams in the range of 0.75 to 0.03 grams per unit contact pair. For a larger number of contacts, for example 900,000, we used 3 kilograms at a condition of 0.003 g per unit contact pair. Ideally, to increase speed, use as little force as possible, and under appropriate circumstances, do not use any force beyond the force applied to the chip by gravity (ie, the weight of the chip).

Conventional processes for attaching the die together require an adhesion strength of from several grams to tens of grams per unit contact pair. This places tremendous stress on each of the semiconductor chips, often damaging or cracking the semiconductor chip. Thus, the method described above can dramatically reduce or avoid the application of stress found when using conventional methods.

In addition, more conventional methods are not suitable for the small dimensions that can be employed by the present inventors. Typical soldering processes are liquid-phase processes, which are not suitable for such small sizes and pitches and also do not apply a few grams of pressure per unit contact pair. In other words, 50 kilograms are required to attach a chip with 10,000 contacts to a size of 1 cm x 1 cm, typically at 5 grams per unit contact pair. In contrast, the pressure in the fusion state of the process is typically less than or equal to the pressure used in the deposition process. For example, using the fusing process described here, a 10,000-contact chip, which required 300 grams of pressure in the tack, required only 9 grams of melt in the process.

In addition, multiple reflow / multi-high stacks can be made practical if only a little pressure is used or no pressure is used at all. In order to produce stacked multi-chips high, the amount of pressure exerted on the chips is such that, while the fusing of chips on it is performed, in particular when some chips on the mother wafer accommodate a larger- Should be low to prevent chipping, prevent yield loss, and prevent the possibility of separation of the lower chips in the stack. If actual pressure needs to be applied on the mother wafer and daughter chips while the fusing process is being performed and if some of the mother chips have a much larger stack than others, A tool set is required. In contrast, using the method of the present invention, which requires a slight external force or no external force at all, can be avoided, making it possible to make multiple high chips more practical, can do.

Another advantage of the variants of the methods described here is that the strength after completion of the fusing process is high. The strength of the contacts after the fusing process is several hundred kilograms per square centimeter, typically 1000 kg / cm2. Of course, as a result, once the fusing process is completed, the reprocessing potential is significantly reduced.

Representative, but not limiting examples of malleable materials are gold-tin (Au / Sn) alloys, silver-tin (Ag / Sn) alloys and other materials also identified herein. It should be noted here that the term "post" is simply used to denote stiffness. And is not intended to be used to limit or constrain the size, shape or geometry in any way. Thus, as described below, and as described in the "Certain Modifications" paragraph, the term "post" means that it has a cross sectional profile that is large or sufficient to achieve the intended purpose described herein The meaning can be wider than that. In addition, the term "post" may be created as part of the processes described herein, for example by thinning the backside of the wafer without making the metal sheath or metal contact thinner, Attached or inserted.

When a stack is included, a constant electrical connection through the wafer may have a rigid contact at one end and a soft contact at the other end. In such a case, for simplicity, if the wafer is once referred to as a "mother" or "daughter ", these terms refer to the subsequent stack layer, And a rigid contact for forming an infiltration connection. For the sake of clarity, the subsequent "daughter" wafer, which is connected to the other end, will be referred to as "daughter wafer 2 ".

One example of such a method is illustrated in Figs. 47 and 48. Fig. In Figures 47A and 48A, complementary contacts 4702, 4704, 4802, 4804 are shown disposed on each of the two chips 4706, 4708, 4806, 4808. For simplicity, electrical connections 4710 and 4810 as well as other components are shown to be located just beyond the perimeter of contacts 4702, 4704, 4802, and 4804.

As shown in FIGS. 47A and 48A, one of the contacts 4704 and 4804 is a rigid contact and the other contact 4702 and 4802 is a soft contact. 47B and 48B show respective contacts 4702, 4704, 4802, and 4804 at locations where mutual contacts were made. Rigid contacts 4704 and 4804 penetrate the soft contacts 4702 and 4802 by applying pressure before or in the tack state. Figs. 47C and 48C show contacts after the fuse state, where the two materials are now mutually fused to form a strong bond between the two.

In addition, the "width" of a soft contact can be "minimal" since it has the same or a smaller width than the contact to be connected (prior to bonding) Quot; contact ". In the above examples, FIG. 47 shows an example including "minimal" contacts, and FIG. 48 shows an example including extended contacts.

In general, it is desirable to make the size of the soft contact slightly larger than the rigid contact, i. E. To use an extended contact. By doing so, the soft contact surrounds the rigid contact, and accurate alignment between the two chips is achieved during integration. This is because in such a case, the rigid contact needs to penetrate somewhere in the region of the soft contact. As a result, a larger alignment offset can be adjusted. This is best understood by considering an example of a soft contact having a circular cross-section of 12 microns in diameter and a rigid contact having a diameter between 10 microns and 6 microns. If the diameter of the rigid contact is 10 microns, an offset of 3 microns will occur at the edge of the rigid material, extending beyond the range of the soft contact. If the rigid contact has a diameter of 6 microns, an offset of 3 microns still remains embedded within the 12 micron diameter of the soft contact material. Typically, the rigid contact will span less than 40 microns at the widest point, and may span less than 25 microns, less than 15 microns, or even less than 10 microns at the widest point. Moreover, with the use of the method of the present invention, the soft contact can be at least as wide as the rigid contact, and preferably can be more than 20% wider. Furthermore, the post height may be greater or less than its width, but typically is greater than its height.

In view of the above basic description, the method of the present invention can be applied to a variety of applications such as, for example, by employing a rigid material suitably as part of a metallized or conductive material so that it can be used as a rigid contact, By applying a second soft material to another portion of the metallized or conductive material so that it can be used as a contact, the scope of application to the above-described modifications can be extended.

Figure 49 shows a portion of a stack of semiconductor chips with through-chip connections created in accordance with any of the preceding implementations in a manner similar to that of Figure 41. For the sake of simplicity and clarity, the through-chip connections are not shown connected to the elements on individual chips to pass through the device, since the presence or absence of such connections is essential to understanding the post and penetration approach It is not.

Any contacts 4902 and 4904 may be added above and below the metallization 2412 and the conductor 2802 to allow each chip to be easily and / Respectively. As described above, a metallization or a metal contact may be used directly. If any contacts 4902,4904 are added in accordance with a particular implementation, then these contacts 4902,4904 may be conventional contact pads of simple construction, one of the types of prior art, or a post formed as described above, Or may be formed in the form of a through contact with a post.

Thus, it can be seen that the stacking operation can be performed more easily by using the post and penetration approach of FIG. Some of the stacks of the simplified form of the chip shown in FIG. 49 stacked using these posts and penetrating approaches are shown in FIG.

It will also be appreciated that variations of some of the implementations described above are possible to facilitate the use of such posts and penetrating contact approaches. For example, an embodiment similar to that shown in FIG. 15 (i.e., the embodiment where the metallization of the trench bottom is not completely removed), except that the bonded substrate 1102 and the finished substrate 1302 are not present , So that the metallization 1502 can be used as one of the rigid or malleable contacts and the second material inserted into the gap can be used to provide the opposite contact (i. E., If the metallization has & And the contact is indicative of the malleability characteristic if the metallization is "rigid"). In this embodiment, as shown in Figure 51, the voids inside the metallization can be filled with, for example, a preformed post 5102 inserted at an appropriate point during processing. Optionally, when the soft material is coated on the end that will contact the other "rigid" material to form the bond, the metallization 1502 and the second material may be made of the same material.

52 is a simplified view after the chip of Fig. 51 is coupled to another electronic chip 5200. Fig. Here, the electronic chip 5200 is shown as having a drive and control circuit diagram 5202 for controlling the laser 5104 shown in the chip of Fig. 51 for illustration. The electronic chip also includes a post 5204 having a stiffness relative to the metal plating material 1504 used in the chip of Fig. Thus, by allowing two chips to be united under suitable conditions, a post and penetration connection portion 5206 is formed so that the driving and control circuitry 5202 and the laser 5104 on the electronic chip 5200 are electrically connected.

Figures 53-71 show a simplified variation of the basic contact formation and coupling approach. For simplicity and clarity, this approach involves a pair of normal (not shown) processes that have been pre-processed (i.e., processing to include devices and associated contacts and traces) but not yet cut into cubes with individual chips Lt; / RTI > As shown, the chips shown in the item "a)" in each of the figures may be used as a daughter chip and then as a daughter chip to be combined with the mother chip shown in the " Lt; RTI ID = 0.0 > IC < / RTI > It should be noted that while this process is shown as occurring in parallel, it should be understood that this is merely to aid understanding. In practice, any one of the processes may be performed prior to the other process, and these processes may be performed to some extent or simultaneously.

First, a daughter wafer shown in FIG. 53A and a mother wafer shown in FIG. 53B will be described. Each of these wafers is sufficiently formed with a chip, and a plurality of elements (not shown) are further formed on each of the wafers. In view of the current state of the art, contacts 5302 and 5304 on the daughter wafer, as shown, may be between 25 microns and 50 microns, although the same approach may be used for contacts with significantly smaller pitches, on the order of 2 microns to 7 microns, Microns. ≪ / RTI > For ease of illustration and understanding, contacts 5306 and 5308 on the mother wafer are shown having a pitch greater than the contacts 5302 and 5304 of the daughter wafer. These contacts 5302, 5304, 5306, 5308 are conventional aluminum IC pads accessible through chip cover glasses 5310, 5312.

Next, dielectric layers 5402 and 5404 are deposited thick on the chip (Figs. 54A and 54B). Thereafter, through the photolithographic patterning process, the region above the contact is opened upward allowing access through this open region (Figs. 55A and 55B).

Etching is then made through the dielectric to allow access to the IC contact pads (Figs. 56A and 56B). Thereafter, the photolith is peeled off (Figs. 57A and 57B).

Alternatively, the thick dielectric layers 5402 and 5404 as described above may be thick photoresist layers (Figs. 54A and 54B). In this case, the thick layers 5402 and 5404 are removed by stripping the photoresist (Figs. 57A and 57B).

Next, a seed layer is deposited on the wafer to facilitate the subsequent plating process (FIGS. 58A and 58B).

Thereafter, a dielectric layer is coated (Figs. 59A and 59B), and a photolithographic patterning process is used to define and control the location where plating occurs (Figs. 60A and 60B).

The wafer is then plated until a predetermined amount of metal is present (Figs. 61A and 61B).

The dielectric is then removed, leaving a "standoff" or protruding contact (Figs. 62A and 62B).

Generally, the mother wafer and the daughter wafer may be provided with an insulating device. The purpose of a rigid structure on a daughter wafer is to provide an isolator so that the entire contact can accommodate the non-planarity of the two chips so that the contact can be formed quickly, while in some cases the contact may not be needed. The purpose of the rigid structure on the mother wafer is to serve as a pierceable post into the soft material on the daughter wafer and as an isolator. Also, since the insulator can be used to allow a height difference between the top-side IC cover glass and the IC pads, some of the contacts may be disposed on the upper side of the glass and the remaining contacts may be disposed on the upper side of the pad.

Returning to the process flow again, a further etching process is performed to remove the undesired seed layer (Figs. 63A and 63B). As shown in FIG. 63A, rerouting of the original contact is completed by leaving the seed layer material on the daughter wafer between one of the contacts and the new isolator / contact. Optionally, additional or alternative reroute layers may be disposed before or after the process is completed. It may also be desirable to plate the reroute layer of a given area thicker than other areas before performing an etching process to remove the seed layer.

Next, a barrier layer is coated on the contacts on the daughter wafer (Fig. 64A). In this case, the barrier layer is made of nickel, and prevents diffusion of the metal into the IC pads 5302, 5304, 5306, and 5308 or prevents the diffusion of metal into individual chips To prevent damage. Optionally, when the approach is used in a tack and fuse joint process, particularly involving post and penetrating contacts, cap layers 6402 and 6404 are formed on top of the barrier layer to prevent unwanted diffusion during the joining process And in this case the cap layer is made of gold. The cap layer is also coated on the mother wafer (Fig. 64). At this point, the rigid contact on the mother wafer is completed.

Again, a dielectric 6502 is coated on the daughter wafer (Fig. 65A). Also, through the photolithographic patterning process, regions 6602 and 6604 above isolator contacts 6606 and 6608 open upwards (Fig. 66A).

Thereafter, the soft contacts 6702 and 6704 are built on an isolator (Fig. 67A) and the dielectric is removed, leaving a fully formed soft contact (Fig. 68B).

The daughter wafer is then flip-processed and aligned with the mother wafer, and through the photolithographic patterning process, the region above the contact can be opened upwards to allow access therethrough.

The two chips are then pressed to form a single chip so that a rigid contact is formed through the soft contact (Figure 70).

Finally, the two chips are permanently attached to each other via the dissolution phase (Figure 71). One thing to note is that as a result of this process, the two chips are spaced at a distance of less than 10 microns, usually less than 5 microns, measured between the top of the rigid posts and the top of the contacts to which the posts on the other wafer are connected It is a point. If the wafer is perfectly flat depending on its use, then this distance will be the distance between the two wafers. However, if the wafer is not perfectly flat, the distance may be longer or shorter due to the geometric shape of the wafer.

72-87 show a simplified process of a variant for creating a contact on a daughter wafer (Fig. 72a) and a mother wafer (Fig. 72b) and then joining two chips together. As with the previous example, two wafers will be described. 72A and 72B, the cover glass opening above the contact pads for IC has a size of between about 8 microns and 14 microns. Of course, the size of such openings may be as low as 4 microns, and in some cases as low as 1 micron or less. Using one or more of the processes described herein, it is advantageous that the treatment of such relatively small sized openings can be done quickly at the same rate as the treatment of relatively large sized openings.

In addition, as shown, the spacing of the pads on the daughter wafer (Fig. 72A) is typically formed at a pitch of 25 microns to 50 microns. Likewise, in the case of the approach described herein, it can be used with a contact having a pitch of nominally 7 microns, and also with a contact having a pitch of 2 microns or less.

This modified example proceeds as follows. First, the dielectric is coated thickly on the wafer (Fig. 73). Thereafter, a photolithographic patterning process is performed to allow the region above the contacts to be opened upwards to allow access therethrough (FIG. 74). Next, the dielectric is etched to remove contact above (FIG. 75A), the photoresist is stripped from the mother wafer (FIG. 76B) and a new reroute path is formed (FIG. 77).

 The exposed areas above the contact and reroute paths on the daughter wafer are metal plated with the barrier layer (Fig. 78A), and the seed layer is coated onto the mother layer (Fig. 78B). Optionally, a barrier layer is coated on the mother wafer to protect the associated IC pads (not shown).

Thereafter, the photoresist is peeled off from the daughter wafer (Fig. 79A). A new photolithographic patterning process is performed to define the area in which the contact is to be built (Fig. 80).

A suitable material is deposited to create a soft contact on the daughter wafer. In this case, the suitable material is a gold-tin (Au / Sn) alloy in which a separating layer of tin (Sn) is topped and then topped with a layer of gold (Au). Subsequently, by plating the exposed seed layer with copper, a rigid contact is formed on the mother wafer (Fig. 81B).

Thereafter, the photoresist is peeled off from the daughter wafer and the mother wafer.

Then, the undesired remaining exposed seed layer is removed from the mother wafer (FIG. 83).

Finally, a cap (optionally after the barrier layer is first formed) is coated on the mother wafer contact to prevent oxidation (oxide cap) (FIG. 84B).

According to the variants described above, the wafers are then aligned (Fig. 85) to one and then tapped (Fig. 86) and also at some point thereafter (Fig. 87).

It will be appreciated that, as discussed above in a somewhat superficially contemplated manner of several variations, there may be additional variations that include more detailed details of the various steps of the process described above. It should be understood, however, that these details are equally applicable to the variations and other modifications described above.

Figures 88-91 and 95-102 show briefly the approach of two additional variants for forming a rigid post on the rear side of the daughter wafer in parallel. Here, it is appropriate to use the term "daughter " as a reference, because the aluminum IC pad will form a soft contact and the back contact will be" mother-type " It is connected to the post.

Moreover, while some variations are shown in a side-by-side fashion, the process steps described herein need not necessarily be done in parallel, and that these processes may be performed on different wafers at different times, Other variations are possible.

This example begins with the wafers 8800 and 8802 shown in Figures 88A and 88B, respectively, and shows a first example of a contact reroute, i. E. A portion of the via not aligned with the pads of the wafer surface, Figs. 88A to 99A) and a second example (Fig. 88B to Fig. 99B) in which vias are aligned with the pads due to no rerouting process of the contacts. In addition, by making the widths of the two vias produced different from each other, it can be shown that vias of different widths can be used for a single wafer or chip, while the width of the vias may differ from the width of the pad on the chip (I.e., the via may be formed to have the same width as the pad, or may be formed wider or narrower than the width of the pad). It should be noted that the components shown in the drawings are not necessarily drawn to scale and should not be formed in the exact portion.

First, the dielectric layers 8902 and 8904 are thickly coated on the wafers 8800 and 8802. In this case, a silicon wafer having aluminum IC pad contacts 8804 and 8806 is used as a wafer (Figs. 89A and 89B). This thick dielectric layer serves to protect the chip, while it acts as a blocking region in subsequent processing steps when the top surface is thinned after the electroplating process. One thing to note is that in subsequent steps, the via is not filled through the electroplating, or b) during the via metal filling process, not through the thinning process (i.e., the etching process or the photolithography liftoff process) If the vias are filled in a manner that allows removal of the excess deposition material, the above steps may be made arbitrarily. Suitable materials for deposition of thick dielectrics include, but are not limited to, TEOS, oxides, nitrides, spin-on glasses, polyimides, BCBs, other polymers or epoxies, thick photoresist layers, etc. (If a photosensitive polyimide or a thick photoresist is used, in some variations, no separate photoresist deposition step is required in a subsequent step).

Next, the photoresist layer is coated and patterned to prevent unwanted portions of the wafer from being etched (FIG. 90). This step is a step of defining the position of a via to be generated later.

The wafer is then etched through the dielectric (FIG. 91), and the semiconductor and substrate are also etched to create vias 9102 in the wafer at the locations where rerouted contacts will be formed in the case of rerouting 91a), typically via 9104 is formed on the wafer through a dielectric and aluminum IC pad contact 8806 (Fig. 91B). It should be noted here that the desired depth is such as to allow exposure of the "post" formed through the thinning process of the backside of the wafer, as evidenced by the following figures. Typically, this depth is about 75 microns. Although it may not be essential to form vias with this thickness, assuming that several thousand or even millions of contacts are formed per square centimeter, by forming them at such depth, So that the entire daughter wafer can be processed in a wafer-scale manner with good yield during subsequent processing steps. Alternatively, the vias may be formed in all directions through the wafer. In the case of such a wafer penetration variant, a thinning and etch processing step as described below which is made to the backside of the wafer to expose the metal inside the vias may not be necessary. Also, although the vias in this example are shown as single conductors, the same approach can be applied to coaxial or triple coaxial conductors in a manner that directly incorporates these production steps into the process.

At this point, there is a need to emphasize certain attributes and advantages obtained through the use of the illustrated process in certain implementations. The attributes and advantages caused by this approach include the fact that the etching and creation of the vias can occur prior to the combination (between the chip and the chip, between the chip and the wafer, or between the wafer and the wafer). In other words, the chip, the die, or the wafer is easily performed before connecting it to the other element. Moreover, with this approach, vias can be etched from the element (i.e., active) side of a previously formed, usable electronic chip. This approach can be used virtually anywhere on the chip where no direct circuitry is formed in the etch path that is not sacrificial. Thus, the vias formed using this approach may not be aligned or aligned with the pads as needed. Also, by forming the vias on the pads and / or by forming the vias in a size considerably smaller than the pads in some cases, the "real estate" on the circuit-stealing IC, particularly in the area of the chip with little or no circuitry ) "Can be minimized.

With regard to the formation of such vias, in some cases it may be desirable to impart a degree of slope to the vias so that the subsequent deposition material can be properly coated on the sidewalls. In this case, the slope can be set to a typical nominal slope of about 88 degrees from the direction perpendicular to the vertical axis of the via (i.e., the width of the via decreases slightly as the depth increases). A cross-sectional view of one example of such a tapered via is shown in FIG.

Typically, vias having a depth of at least 75 microns and a width of at least 5 microns are used. In the case of the vias shown in Figure 92, the diameter is 20 microns and the depth is about 150 microns. 93 is a photograph showing an example of a via (having already been charged) with a depth of 100 microns and a diameter of 20 microns. A width as small as 0.1 micron is also possible, in which case the depth can be made shallower (for example, to a depth of only about 5 microns). However, when a width smaller than 0.1 micron is used, the integrity of the joint to be finally formed can be deteriorated. Likewise, if a shallower depth than 5 microns is used, it may be necessary to thin the wafer down to the extent that the schematic (if any) of the wafer base may be damaged. Currently, in order to achieve sufficient production yield using ideal commercial equipment, depths in the range of 75 microns to 150 microns and widths in the range of 5 microns to 20 microns are commonly used. Of course, for certain applications, depths and widths outside this range are also possible. For example, the vias may be formed to a depth of 300 microns, and in some cases may be formed to completely penetrate the wafer. Of course, currently available equipment does not have enough robustness to allow acceptable yields at such large depths of conditions, including the planned number and density for large commercial production purposes. However, advances in such equipment may reduce or eliminate such limitations over time, resulting in slight changes in depth, number and density as specified in the approach without modification of the approach as described above. .

Optionally, the bottom of the via may be formed with a point. This type of formation is the method used to achieve strong stiffness posts, good penetration of rigid materials into the soft material, and strong final contact (contact to maximize surface contact between rigid and soft materials). In order to accomplish this, the rigid posts are in the form of a pyramid (or pyramid on the upper side of the cylinder), i.e. the base of the post has the same width as the contact below it (a structure maximizing the bond strength of the post and the contact) The upper side of the contact is tapered to a size considerably smaller than the contact so that alignment relative size factors can be achieved. An advantage of this variant is that it allows the sharp-pointed posts to be formed, so that when used for posts and through-connections, a penetration similar to that of a pyramid-shaped profile formed later in the rigid post can be achieved. 94 is a photograph showing a cross section of a chip in which a pin-shaped vias are formed inside.

The photoresist is then stripped (Fig. 95) and coated on the exposed via surface (not shown) with a dielectric or insulating layer to prevent electrical shorting to either the metal or semiconductor circuitry inside the via. The thickness of this layer is typically between about 2000 angstroms and 1 micron. However, for certain applications, the layer may be thicker to balance the thermal expansion coefficient or reduce the capacitance of the via. Examples of insulating materials that can be used include TEOS (oxides), other oxides, nitrides, polymers, CVD diamond, and the like.

A metal barrier layer is then deposited on the dielectric (Figure 96). The barrier layer serves to prevent metal from migrating to the insulator and semiconductor. For illustrative purposes, the barrier shown is titanium-tungsten (TiW), although all of the barrier materials described herein are suitable at this stage.

Then, in certain variants, when the metal is plated, a layer of plated "seed" is coated (FIG. 97). This seed layer is used as a base for electroplating vias. A copper seed layer is preferred because such a copper seed layer exhibits excellent electrical and thermal conductor properties and is being used predominantly in today's industrial applications and is very easy to work in standard semiconductor and packaging lines. However, either of the other materials as described herein in connection with the seed layer for the stiff material and / or the rigid material may be used. If the via is filled in a manner other than electroplating, such a seed layer may cover only the via itself, not the wider portion of the wafer, or may not be present at all. For example, when vias are filled by CVD or evaporation, no seed layer is required.

The barrier layer and the seed layer are typically deposited by sputtering or physical vapor deposition (PVD), although electroplating may be used, in some embodiments, electroplating provides significant advantages over sputtering or PVD.

The vias are filled with a metal or other conductor to form an electrical conduit through the wafer (Figure 98). Typically, the filling material is copper for the plating approach. However, materials comprising any of the other materials described herein as suitable rigid or flexible materials may be used. It should be noted that a simple electrical connection is needed and that vias do not have to be completely filled with conductors if good thermal or low electrical resistance is not required. In this case, the remaining portion of the via may optionally be filled with another material, such as oxide or epoxy. The entire vias typically have to be filled with some type of material because if the air is trapped in the vias in the vias with the chip packaged and sealed then the expansion and compression of the air, This is because defects can be caused. Fully filled with metal results in the lowest resistance and maximum thermal conduction contact. Also, if larger diameter vias filled with metal are used, this metal can contribute to thermal conduction through the wafer.

98, the vias are filled by plating the seed layer using an electroplating process. Optionally, if the plating process is complete and the void remains in the center of the interior of the plating material, the void may be filled with filler material such as oxide, additional metal, solder, or any other material suitable for the application.

Advantageously, when the vias are filled with the same material as the rigid material for the mother wafer or the same material as the soft material for the daughter wafer, there may be advantages in terms of lamination. Alternatively, the via can be filled with the same material as the flexible material if the mating contact on the chip to which the via is attached has a rigid material thereon.

It should be noted that, as shown in Figure 98 (b), when the via is aligned with the pad, the vias can essentially contact the pad by filling the via with conductors.

When a particular wafer is connected to another wafer, as is expected in most implementations, the composition of the barrier and the via fill material of the daughter wafer will follow the same guidelines as the barrier and the rigid material for the mother wafer, When coupled to the mother wafer, it is important that the daughter wafer act in the same manner as the mother wafer.

Returning to the process flow again, as a result of the plating in the previous step, a large amount of conductors must be deposited on top of the wafer and then removed. This step can be accomplished through lapping, polishing, or chemical-mechanical processes (CMP). This thinning is carried out up to the thick dielectric deposited in the first step. The actual thickness used for the coated dielectric, as in the first step, is chosen to provide error margin to this lapping step. If the conductor filling the vias is not deposited by electroplating, this step may be unnecessary. As shown, the chemical-mechanical process (CMP) is then used to remove the excess plating material and the seed layer underneath to the extent that it slightly invades the surface dielectric layer and the surface dielectric layer (FIG. 99).

The photolithographic etching process is then used again to assist access of the wafer from the top of the wafer by coating the photoresist to the IC pad contacts 8804 and 8806 of the wafer (FIG. 100), and then the exposed dielectric 10002 is etched (Fig. 101). 101b), and if a contact is not required between the same pad and the mother chip for a particular pad, then that particular pad may precede this step (i.e., It may remain covered by the photoresist). In a variant, a photolithographic process can be performed such that a connection to the IC contact is formed during deposition (and functionally forming part of the seed layer) of the seed layer or during plating or filling of the via. In this modified example, a photolithography step may be unnecessary.

Thereafter, the photoresist is peeled off and the wafer is cleaned, leaving a post completely formed inside the daughter wafer (FIG. 102).

At this point it is assumed that a wafer is additionally prepared for coupling with other elements such as other chips, dies, or wafers (i. E., The approach is between the chip and the chip, between the chip and the die, The same applies to all pre-strains between the die and the die, between the die and the chip, between the die and the wafer, and between the wafer and the wafer). These additional processing steps are schematically shown in a parallel manner in Figs. This process starts with a daughter wafer as shown in Fig. Also, for ease of understanding, processes performed on a wafer that is used as a "mother type" contact element are also shown.

This process is carried out as follows. First, the dielectric layer is coated on the mother wafer except on the IC contact pad (Fig. 103B). This dielectric layer is already provided on the daughter wafer (Figs. 102A and 102B).

Next, a barrier layer is deposited on the daughter wafer (Fig. 104A), some of which, in the case of rerouted contacts, ultimately become an electrical connection between the original IC contact and the preformed post. It is advantageous to use a barrier layer because the barrier layer prevents the soft material from subsequently interacting with the IC pad or the rigid or insulating metal.

As shown, a barrier material, such as Ni / Au, Ti / Pd / Au or Ti / Pt / Au, is deposited on the daughter wafer via sputtering. In addition, such a barrier can be used generally as a bump metal (UBM), or used in rerouting which does not require removal of the seed layer. This layer is typically formed using electroplating which is optionally combined with an electroplating process for sputtering and / or evaporation processes or top layer formation.

Also, as shown, a seed layer is deposited on the mother wafer using, for example, electroplating or deposition techniques (FIG. 104B). As shown, the mother wafer is formed by coating TiW + Cu and is used as a UBM and seed layer for electroplating a rigid contact on a mother wafer. When copper is used on the upper side, copper electroplating and subsequent post forming processes of stiffness can be made easier. The UBM on the mother wafer can, in some embodiments, be used for dual purpose of seed layer and reroute for electroplating of the rigid member, or it can act as an RF shield between the wafers (patterning for this, But not at the etching stage).

Optionally and alternatively, the barrier and seed layer can be made of the same component. In this case, a single material can function as both layers.

As shown in Fig. 104, the barrier is formed over the entire wafer. So that a subsequent electroplating step can be performed. After such electroplating is completed, however, the seed layer and barrier must be removed in areas where the contacts are not present so that the various contacts do not remain together in an electrical short-circuit (unless otherwise desirable for other reasons In other words, the barrier and seed layer act as electrical rerouting materials in the points).

Subsequent materials may be formed by a process other than electroplating, such as sputtering or evaporation, after which the mother wafer stage may optionally be patterned using photolithography around the pad, a barrier metal deposition process, a subsequent metal A deposition process, and a lift-off process. The net result is the same for the metal and barrier formed around the pad or where rerouting is required.

Thereafter, a lithographic process is performed on the daughter wafer to expose the barrier material covering the original contact (FIG. 105A). In addition, as shown in the present case, the mother wafer is patterned using an undercut to provide any patterned contact, for example, in the form of a pointed pyramid, cone or mushroom (Fig. 105B). Optionally, the mother wafer can be patterned to form some other contact shapes to increase the effective surface area of the contact or to form a contact having a smaller cross-section at a level that is more meaningful than the corresponding soft contact to which the contact will ultimately be connected . Through such a patterning process, the penetrating force can be improved because the coating pressure is dispersed over a smaller area.

In this step (Figs. 105A and 105B), a region where the subsequent metal is disposed is defined. If the subsequent metal is deposited by means other than electroplating, this step is performed prior to deposition of the barrier and seed layer described above. Here, it is assumed that electroplating is used. It should again be noted that lithographic patterning may be performed to allow subsequent electroplating and / or etching of the seed layer (or subsequent lift-off process if electroplating is not used) to define the reroute layer.

The daughter wafer is then metal plated by depositing a suitable metal over the exposed barrier (Figure 106). According to certain embodiments, one or more of the following layers may be formed on the daughter wafer. This subsequent layer may include a layer of insulator (if necessary) to handle the non-planarity of the wafer, a diffusion or soft layer (region to be deformed or to form a contact), a cap or adhesive layer (If necessary), and / or an oxidation barrier to prevent the adhesion / diffusion layer from being oxidized.

Further, on the mother wafer, the voids generated by the lithography process are filled by plating (electric or electroless plating) the seed layer exposed by the lithography process (FIG. 106). According to certain embodiments, a rigid material used in post formation for use in posts and through connections may be added at this stage.

Figure 107 shows one example of a fully plated pyramidal contact for a mother wafer in considerable detail.

Figure 108 is an enlarged view of a portion of a variation of a mother wafer contact having a profile similar to that shown in Figure 107. According to this optional modification (a variant applicable to profiled and non-profiled contacts), some metal of the semiconductor pad 10802 is etched prior to plating (metal plating) of the metal for the post of rigidity, An undercut profile 10804 is formed at the edge of the pad 10802. [ Once the rigid material 10902 is built (Figure 109), some of the rigid material 10902 is used to fill the undercut 10804. This additional filler acts as an anchor for supporting the rigid contact structure during stressing during further processing or during operation due to thermal cycling. As shown, the rigid material 10902 is nickel (Ni).

At the completion of the metal plating and / or plating, the photoresist is peeled off to expose the contact formed on the daughter wafer and the mother wafer (FIG. 110). However, it should be noted that when the barrier for the mother contact is electroplated, this step may optionally be performed before the metal plating followed by stripping the photoresist.

 Next, a photolithography process is used to remove the undesired barrier and seed material from the daughter wafer and the mother wafer, respectively, while protecting the constructed contact or post (FIG. 111). It should be noted that this step may also be used to define and / or reroute the contact. Moreover, in the case where other metals are not electroplated, the order of these steps may be slightly changed, since a lift-off process for subsequent etching may be used.

However, since the seed and barrier materials of this example are electroplated, etching is used. Thus, undesired seed and barrier materials are etched away (FIG. 112). In another alternative optional embodiment, only the barrier and seed material is etched and removed as needed to prevent undesirable short circuiting caused by a single contact, so that most of the surface of the wafer is exposed to the barrier And the seed material so that it can be used as an EMI shielding film to prevent noise or undesirable signal coupling between the stacked chips, especially when the remaining barrier / shielding film is attached to the ground plane.

Thereafter, the photoresist is peeled off and removed (FIG. 113).

At this point, the daughter wafer includes a functional rigid post suitable for use in forming posts and threaded connections with other wafers.

However, as evidenced by the description of the present disclosure, during processing of the mother wafer, a process of electroplating the material of the softness (relative to the material on the daughter wafer post) to the contact continues (Fig. 114b). It should be noted that although such a step is shown as an electroless plating step, a modification of this approach is that an electroplating step may be used. In this variant, the above-mentioned part of the process takes place as part of the metal plating step, or alternatively between the step of stripping the photoresist used in the metal plating step and the coating of the protective photoresist as described above, Can be accomplished as a plating operation. However, in any case, the deposition of the barrier is important because the barrier prevents intermixing of the ductile and rigid material and constrains the flexible material between the IC pad and the rigid material on the daughter wafer.

At this point, the mother wafer has a functional flexible post used to form post and penetration fit connections with other wafers.

However, in this example, after the post is formed on the wafer, the third chip is supposed to be stacked on the upper side of the daughter wafer. Thus, further processing of the daughter wafer is necessary, as will be described below.

First, the daughter wafer is protected from contamination during subsequent thinning treatments (Figure 115 (a)), with the first side of the daughter wafer (i.e., the device and contact supporting side) coated with a suitable removable protective material. Such a cover may consist of only a simple photoresist or dielectric or may be made of a rigid material such as a glass plate or other semiconductor wafer ("carrier" wafer) attached to a daughter wafer using photoresist, wax, polymer, Member. In some variations, a very thick layer (e.g., a layer having a thickness of at least 50% of the thickness of the daughter wafer after the thinning process) is used. In another variant, a rigid carrier wafer may be used. In any case, additional strength reinforcement of the daughter wafer can be achieved through a very thick layer, so that the wafer can be handled without risk of breakage during thinning.

Next, the back side of the daughter wafer is thinned so that the back side is exposed to an empty fill material (e.g., a preformed post). This thinning typically takes place until the thickness of the daughter wafer is approximately 75 microns, considering that the depth of the vias is approximately 75 microns. If the vias extend deeper, the thinning process may be made shorter. Depending on the particular application, a thinning process is performed (Figure 116a) until the posts extend over the backside of the wafer or, in some applications, the posts are at the same height as the backside. However, if the bottoms of the vias are sharp, and if the pointed portion is preferably pyramidal, conical or mushroom-shaped, at the completion of the process, the thinning process may be performed to a sufficient extent to remove the pointed portion of the bottom It is preferable not to be performed.

In this case, an etch process is performed on the back surface so that the posts extend to the rear surface (Fig. 117A), since other posts and penetrating connections are desired. This etching step is needed for two purposes. First, the etching process removes a portion of the substrate around the via so that the via can extend beyond the surface (thus allowing the bead to act in exactly the same way as a rigid post on the mother wafer). Second, the etching process cleans the surface of the contact, allowing for good adhesion of the metal in subsequent processes.

Of course, for daughter wafers without through-connections, although thinning and etching processes may generally be unnecessary in view of other heights, it is nevertheless desirable to carry out these processes.

In the case of a modification using a very thick layer or carrier on the front side, if the thinning is carried out, the finished thickness is likely to exceed the usual 75 microns. In fact, according to this variant, the thickness is reduced to about 10 microns by thinning. Moreover, if the carrier wafer is not removed after the tack and fuse process, the thickness of the wafer can be thinned to approximately 5 microns.

It should be noted that, in a modified embodiment, the thinning step may be performed after the bonding treatment between the mother wafer and the daughter wafer. In this variant, the process is performed in the order of electroless plating, tack, dissolve, daughter wafer thinning, etching of the rear face of the daughter wafer until the contact extends over the backside, coating of the barrier to the back contact and cap, And if it is unnecessary in this case, the front side protection process and the removal process of the protection portion are omitted.

The barrier and cap or cover layer is then deposited on the post (Figure 118). This barrier layer and the cover are important for the protection of the via material. The barrier layer (and barrier cover) performs exactly the same function as the barrier material and the barrier cover deposited above the rigid posts of the "true" mother wafer. A soft material may be pinned between the barrier material on this new post and a subsequent second daughter wafer (i.e., "daughter wafer 2"). As shown, the barrier and cap are deposited using an electroless plating process. In this example, 1 micron thick Ni and 0.3 micron thick Au are used. The advantage of using electroless plating is that it does not require a photolithography step on the backside of the wafer, making it possible to use the thin wafer while making the process simple. These advantages are more extreme than when the wafer is thinned with more extreme limits and are cost effective in via etch and via fill steps in dielectric etch and via fabrication processes. Also, specific materials that may be used include any of the barrier materials as referred to herein.

Further, such a barrier does not have to be deposited by electroless plating. Instead, in some variations, electroplating may be used if a seed layer is deposited on the back and plated and etched in a manner similar to that described above. In other variations, patterning and evaporation or sputtering or other types of deposition processes may be used to coat these barrier layers. If additional steps need to be carried out on thin wafers, the approach of this variant offers several advantages, for example in the process flow of deposited metal, through a lift-off process or in the process of seeding in an electroplating process flow The etching of the layer may define a reroute layer, a barrier or a ground plane on the backside of the wafer. Thereafter, the protective layer is removed from the front surface of the daughter wafer (Fig. 119).

Alternatively, if the protective layer for attaching the carrier wafer to the daughter wafer or a predetermined material formed as an adhesive can withstand the temperature of the tack and fuse process, this step can be postponed after the fuse process is completed. This allows thinner thinning of the daughter wafer while allowing individual dies to be handled during the tacking process without causing cracks or damaging the chips. In such a scenario, the circuit diagram of the daughter chip is directed upward (i.e., facing the opposite side of the mother chip) so that the soft material is positioned on the mother chip. Of course, it should be noted that the mother / daughter practice is merely discretionary and vice versa, and in the case of certain well attachments or other variations, the soft material may be in the via itself or even later shall.

In another alternative variant, for example, if a third chip is stacked on the top side but the vias are not formed so that the chip can be combined with the upwardly facing schematic rather than downward, or if, for example, Is present on the daughter wafer and the upper carrier wafer may have built-in microlenses or other inert elements, or if it is desired that the daughter and mother wafer are RF devices and the two electronic circuit diagrams are not immediately adjacent to each other, The step may be omitted completely and the protective layer may remain permanently. In addition, it is usually necessary to constitute a mother chip so as to have a soft material on the upper side.

At this point, it is possible to connect individual chips, assuming that the above-mentioned contacts on the mother wafer and the daughter wafer are paired together. This linking process is described below.

First, the daughter wafer is flipped, and the individual contacts connected to the mother wafer and the daughter wafer are aligned with respect to each other (FIG. 120). This alignment step is used to align the mother wafer and the daughter wafer. This alignment should take into account ± tolerance around the size of the pad. This alignment tolerance can be set somewhat larger by the exaggerated size of the soft contact. Generally, alignment is done in such a way that the entire upper side of the rigid contact hits the soft contact at some point. For example, if the soft contact has a width of 15 square microns on one side and the upper side of the rigid contact is 5 square microns on one side, if the center of the rigid contact is perfectly centered, Micron, and the alignment accuracy is ± 5 microns.

Thereafter, the contact is subjected to pressure to form a post and a penetrating connection (FIG. 121).

One of the important advantages of such an approach to lamination is that the rigid material penetrates into the flexible material. Thus, a strong bond between the two wafers can be achieved because the surface area between the two contacts is greater than the size of the individual contacts themselves. Moreover, this joint is stronger because the error required to pull the two parts apart is a thin layer separation of the horizontal plane of the post and a shear error of the vertical plane of the post. Note that the latter is a less likely form of error and the risk of total error is less likely than when it is alone.

In fact, the amount of protrusion is also important. Typically, protrusions of at least 1/2 micron are preferred. In some embodiments, the amount of protrusion may be small, but when the protrusion level is low, the strength is greatly reduced. Indeed, for soft materials with a total height of 8 microns, the rigid material is usually determined to extend into the soft material in the range of 2-3 microns. If the soft material is 10 microns, the rigid material typically extends into the soft material to a length of 5 microns. According to the general "rule of thumb ", it may penetrate at least 10% of the thickness of the malleable contact, but may penetrate through the malleable contact and up to 90%.

Another important advantage is the penetration of the posts to allow a significant level of non-planarity of the daughter chip and mother chip to the pitch of the contacts. For example, in the case of a contact having a width of 12 microns and a pitch of 20 microns, the height of the soft material can be quite high, for example, the height can rise to a level where the height and pitch coincide. Likewise, the deviation of the planarity from the contact to the contact can be as large as the thickness of the soft material. For example, if the height of the post is 5 microns and the height of the soft material is 8 microns, the difference in planarity between the contact and the contact may be as high as 8 microns. In this case, some of the posts will penetrate the malleable material as a whole, while others will penetrate less.

Returning again to the process flow chart, the tack phase of the tack and fuse process may be performed following, or simultaneously with, penetration of the rigid contact into the malleable contact. As shown in FIG. 121, two processes occur simultaneously. Electrical connections between the two wafers are formed during the tack phase of the process. Advantageously, no intermediate epoxy or other material is required to hold the chips together and can act as a barrier between the connections.

Optionally, for example, if a potential reprocessing is not included as part of the process, an underfill may be inserted between the two chips prior to the tack phase to fill the gap between the two chips, The material is not adversely affected by the temperature used in the tacking or fusing process.

At this point, the mother wafer and the daughter wafer can be connected and tested (in some cases, one is replaced if there is a problem).

Once it is determined that a permanent connection between the two chips is required, the dissolved phase of the tack and melt process is performed (FIG. 122) to form a connection pair (e.g., a combined unit) 12202, 12204. During the fusing process, the mother diffusion / cap, the daughter oxide cap, and the daughter malleable material all interdiffuse into one to form the final composition of the entire contact.

Optionally, underfill can be inserted between the chips prior to the fusing process, if not previously done. This assumes that the temperature is irrelevant or that the dissolving process is followed. An advantage of using such underfill is that the underfill can reduce trapped air between the two chips to reduce damage to the chip or connection due to temperature cycling (because the tack and fuse process forms a sealed seal) .

Once the mother wafer enters the tacking process (i.e., in the process between the die and the wafer, alignment and tacking are repeated at each good location throughout the mother wafer with no process at the known bad mother die location) , In the process between the wafer and the wafer, the two wafers are processed as a whole, and if any test is performed, the position of the bad chip is recorded for future removal operations) So that all the daughter chips are permanently attached. This can be done at a significantly higher temperature than the tack phase. Moreover, the same time is taken for each chip, and the process is performed on the wafer one at a time, so that a fairly homogeneous connection is calculated across each chip through the process.

The temperature of the dissolution phase is typically between 320 [deg.] C and 400 [deg.] C, depending on the particular material involved.

Advantageously, by separating the tacking process from the dissolving process, it is possible to prevent slowing down of the equipment for performing the tacking process by heating or cooling each portion. By performing such a process at a wafer level in a controlled manner, all of the contacts can have a very similar final composition.

During the tack phase, dissolution phase or tack and dissolution phases, an inert or reducing environment may be used to reduce or eliminate oxides at the material surface and to lower the required temperature or pressure at each step. Typically, such materials are nitrogen, argon, other inert gases or other environment containing foaming-gas, formic acid or hydrogen or other reducing gases.

As described above, the process is not completed because the third chip is connected to the newly formed unit. By connecting the mother chip and the daughter chip, the unit can be connected to another chip. Thus, as shown in FIG. 123, a second daughter wafer is aligned in contact with the appropriate contacts on the units 12202 and 12204.

Advantageously, due to the previous processing step, the exposed side of the via on the top side of the first daughter chip has the same composition as the original upper side of the rigid contact. Thus, in the case of subsequent "daughter" wafers, the bonding process is performed in the same manner as the two first wafers (i.e., through alignment, penetration, tack (optionally test) and dissolution processes). A soft material is secured between the individual barrier layer and the posts on the via that penetrate into the soft material. An important advantage of this process is therefore that the via and base bonding process are set up to operate in the same process flow as the same material system to facilitate repetitive stacking beyond the conventional stacked chip pair.

As a result, the mother wafer is provided with a set of chips and a number of other sets of chips (daughter wafer 2), so that the approach, in some cases, tack, tack, tack, Using an ordered approach, the process can be done in the same manner as each layer if desired.

Thus, a second tapped phase is performed on the second daughter wafer to bond to the second daughter wafer unit, and once completed, the newly formed larger unit is further optionally tested, and if the second daughter chip is defective, This defective chip is detached and replaced (Fig. 124).

Finally, if a permanent connection between the second daughter wafer and the unit is required, the melting phase of the tack and melt process is again performed, and new, larger joining units 12502 and 12504 are formed.

After this step, the process is repeated so that a plurality of additional chips can be incorporated into, for example, "daughter wafer 2" or other chips present on a wafer (not shown). Since each chip is aligned only to the chip immediately below it, since the electrical connections are formed during each tacking process, accumulation of alignment errors, such as in other stacking techniques in which all chips must be stacked prior to attempting through- An additional advantage is achieved.

Furthermore, up to the required range, a test of each larger combination unit can be performed (and, if necessary, reprocessing can be performed) following each successive layer. This also provides significant advantages and very effective cost savings and yield increasing effects, since if the die is stacked in multiple layers, the conventional technique requires that the entire build unit be completed before the electrical test is performed . Thus, a normal part can only be tested after an expensive unit has been created, and only the choice to dispose of an overall expensive unit is left if failure and reprocessing are not possible. Also, according to conventional techniques, for example, if there is an error on the chip in the first row, the risk of damage to the unit during construction of the part is high, or the risk of disposal of the part is considerably increased.

In contrast, using one of the approaches described herein, the multi-stack configuration can be created without significant risk. Further, depending on the specific case, an approach may be performed as many times as necessary in the order of alignment, tack, dissolution, alignment, tack, and dissolution, as described above. Under the conditions that the tacking process has a sufficiently high strength, for example, 500 contacts or more, the process can be selectively performed in the order of alignment, tacking, alignment, and tacking as many times as necessary, And dissolution is carried out only after good testing if option is used). This second approach may be more effective when different numbers of chips are stacked at different locations.

At this point, it is noted that a subsequent process of connecting the second wafer (and subsequent wafers) to the unit without adversely affecting the previously formed internal unit connection can be performed using the post and penetration connection and the tack and fuse process . In fact, it has been surprisingly discovered that by using tack, melt, tack, and melt approaches (depending on whether additional thinning processes are being performed), the successive dissolution steps actually have the effect of lowering the resistance of previous connections. This is an important issue in view of the general common sense that the subsequent dissolution tends to weaken or degrade the previously formed junction (this is particularly true for the "well" junction as described below Has been revealed).

In Figures 126-139, additional variations starting with the daughter wafer to be rerouted and the corresponding mother wafer of Figure 103 are shown without exaggeration. However, although the daughter wafer of the present example is processed as shown schematically in Figs. 77A to 104, this time, the process of creating a post to promote it when the second daughter wafer is stacked on the upper side as in the previous example .

The present process starts from the wafer of FIG. 104 in such a manner that the area for rerouting on the daughter wafer (FIG. 126) is defined through the photolithography process. The barrier layer is then coated, rerouting the contacts on the daughter wafer, and the seed layer is coated on the mother wafer (Figure 127). Next, the photoresist is stripped off (FIG. 128) and a new photolithographic patterning process is used to protect all areas on the original contact (FIG. 129). 130), wherein the daughter layer comprises a separate layer of Sn and a gold-tin (Au / Sn) alloy doped with a cap made of gold, the mother wafer having a contact . Repeatedly, the photoresist is stripped off (Fig. 131) and the undesired seed layer is removed by etching (Fig. 132). Finally, a cap of Ni / Au is coated on the mother wafer contact via electroless plating (Fig. 133).

The wafers are then aligned with respect to each other (Figure 134). The contacts can then be treated to be one to form posts and through connections, and tack, selective testing, and possible melting processes can be performed to produce a combined unit of a combination (these processes are all described and illustrated So nothing is shown to avoid redundant explanations).

In this example, a second daughter wafer is further added on top of the daughter wafer, and this additional process will be described below. First, the back side of the daughter wafer of the combination unit is thinned to expose the previously formed backside contact (FIG. 135). The substrate is then etched to allow the post to protrude above the substrate surface (Figure 136).

This adds another subsequent joining step involving so-called thinning, while the process may be stopped here if it is sufficient for a particular application. The advantage of doing this is that there is no need to add a lithography patterning or material deposition process that requires labor for additional contact and is a major source of yield loss risk. Optionally, a cap can be added (i. E., An additional process is required) if oxidation can be a problem due to the time delay for connection to other elements, materials, or other factors.

137 is a photograph showing an example of a contact after completing the steps shown in Figs. 135 and 136. Fig. In Fig. 137, a post 13702, a barrier 13704, and a substrate 13706 are clearly shown.

If oxidation is suspected to be a problem, the cap is coated on the non-rising portion of the post (Figure 138), completing the rear contact formation process.

As in the first daughter wafer, the next daughter wafer is aligned over this rear contact (Figure 139) where the posts and through-connections between the two are in alignment with the etch process or the like so that the etch process can follow.

In general, there are numerous materials suitable for use as a barrier. These materials include, but are not limited to, Ni, Cr, Ti / Pt, Ti / Pd / Pt, Ti / Pt / Au, Ti / Pd, Ti / Pd / Au, Ti / Pd / , Ta, TaN, Ti, TaW, and W.

Suitable materials for the seed layer include, but are not limited to, Ni, Cu, Al, Au, W, Pd, and Pt.

Suitable materials for the variations include, but are not limited to, Ta / Cu, TaN / Cu, Ni / Au, Ni / Cu, Ti / Pd / Au, Ti / Pd / Cu, , Through evaporation or spraying), or mixtures thereof.

It should be noted, however, that not all barriers on an individual chip or a pair of chips should be formed of exactly the same material.

In general, when a barrier is used, the material must have the following characteristics:

 i) be compatible with certain pad materials (usually the pad is made of aluminum, copper and gold).

ii) When small (<15 μm) IC pads and large (> 50 μm) IC pads coexist on the wafer, they should be selected so that they can be placed on these pads of the wafer in good yield.

iii) If the lower bump metal is also used as a rigid material or acts as an isolator, it shall be capable of being formed to a few microns (> 3 μm), satisfying the above conditions.

It is also preferred that the barrier material be compatible with the deposition material on the top side of the IC pad and the top cover glass / passivation layer of the chip.

The use of a barrier may also provide one or more of the following advantages.

i) increase the reliability of the coupling contact while allowing a high yield.

ii) When deposited on top of the pad and on the top cover glass / passivation layer of the chip, the barrier layer may then be used as follows. In other words,

1) As a signal reroute material

2) as a material for preventing crosstalk between chips as an electric shield between two chips, and / or

3) as a seed layer for subsequent steps that may be performed by electroplating (e.g., forming a rigid post and coating of a soft material).

iii) the shelf life of the daughter material is increased because the barrier acts as a cap to prevent or retard oxidation.

iv) pre-patterned to be used as reroute or barrier.

The materials of the variants described above may provide advantages in some embodiments because:

i) The barrier performance of Ta and TaN is believed to be superior to that of TiW.

ii) The nickel-based process simplifies the process by allowing the UBM and subsequent rigid materials to become one and become identical.

iii) In a variant in which copper is not left exposed, the shelf life is made longer so that compatibility with a given manufacturing process is improved.

iv) If a subsequent electroplating step is not required (e.g., for deposition of rigid members or insulating members on a daughter wafer), any of these materials may be accurately patterned over the pad and reroute or barrier regions , A step for forming a subsequent seed layer, and an etching step for defining these regions are not necessary.

With respect to the use of the barrier layer, in many variations, it is important to ensure that: 1) it is a suitable metal on the premise of interaction; 2) 3) the other metals used in the laminate (e.g., stiffness and insulation) do not interact to cause metal contamination; and 4) the barrier is a package for the tack part of the process (For example, Pb / Sn at an appropriate temperature or some lead-free solder typically functioning at about 240 DEG C to about 270 DEG C) and a process which may be between about 300 DEG C and about 350 DEG C Of the temperature of the dissolving part and a plurality of high temperature cycles at temperatures above this temperature. The barrier maintains the integrity of the adhering material by preventing the mixing of metals that must be kept separately for better integrity of the joint.

This is illustrated by way of example with reference to FIG. In Figure 140, a daughter wafer contact 14002 and a mother wafer contact 14004 just before the tack phase are shown. As shown, the barrier layer 14006 of the daughter wafer contact is made of Ti / Pd / Au and the barrier layer 14008 of the mother wafer contact is made of Ni. The "stiff" material 14010 on the mother wafer is copper and the soft material 14012 on the daughter wafer is Au / Sn. Also, the caps 14014 and 14016 on each wafer are formed of gold, and since the two metals of the initial contact are comprised of the same material, the tacking process can be facilitated while preventing oxidation of the individual materials on each side It is used for dual purposes. However, in practice, it should be noted that in most variations, the cap 14014, 14016 layer is normally completely surrounded by other materials, although only for the sake of clarity of illustration is shown only on the upper side. In Fig. 141, the same contact is briefly shown after the fusing process is completed. After the final metal composition is obtained, the cap layer consisting of two gold layers is deposited on the Au / Sn layer to prevent Au / Sn from mixing with pads and copper above Ti / Pd / Sn layer to form an Au / Sn alloy 14102. [ Thus, the dissolution process Au / Sn 14102 is "trapped" between these two barrier layers 14006 and 14008 to maintain the Au / Sn composition uniformly and consistently over a number of subsequent high temperature steps do.

In contrast, for example, in the absence of the nickel barrier layer 14008, the Au / Sn 14102 is in direct contact with the very thick copper layer 14010 (in actual embodiments the thickness of the copper layer is Au / Sn Of the thickness of the substrate. As a result, Sn is diffused into the copper at a predetermined temperature, and the properties of the alloy thus obtained start to be largely changed. For example, the melting point of copper is 1084 ° C. As Sn is initially diffused into copper, the upper side of the rigid post is a mixture of Sn-rich mixtures with significantly lower melting points (for example, a mixture of 97% Sn and 3% Cu has a melting point of about 230 ° C . As Sn more diffuses into the copper, it has a lower melting point than Au / Sn, and the copper post becomes a rigid member in the tack and fuse process. Equally important is that the copper 14010 seals Sn from the Au / Sn 14102 to raise the temperature at which it becomes ductile. Thus, the rigid member becoming increasingly ductile is pierced into the increasingly hardened flexible member. This affects the contact strength and uniformity and ultimately affects the density of the contact spacing available. Moreover, these effects accumulate over time. Depending on the length of time the fusing process takes place, the composition and performance of the contacts can vary greatly. If the contact has undergone a plurality of dissolution cycles, this would be the case, for example, if the chips were stacked in multiple layers in the vertical direction. The bottom chip of the laminate exhibits significantly different mismatching behavior compared to later-dissolved chips of the laminate. By using such a barrier metal, Au / Sn is largely limited, so that the same composition and characteristics can be maintained through a plurality of dissolution cycles. Even when a barrier is used in this manner, for example, mutual diffusion may occur between Au / Sn and Ni, but the diffusion rate thereof is much slower than that in the case of using Cu alone. For example, Of chips, for example, 100 chips or less, can be neglected. Thus, in the case of certain embodiments, whatever material is used, the barrier should be a component of the final bonded alloy to prevent or minimize interdiffusion that normally would have adverse effects.

In a typical post and penetration approach, although the two mating contacts are shown as being fairly flat, this is not a desirable configuration or prerequisite for all applications. It is desirable to minimize the bad connection, since the quality of electrical connection (or defect) between the two points has a direct effect on the resistance of the connection and the poor connection reduces the yield. Advantageously, the yield can be increased (without increasing the "footprint" of the contact) by allowing the post and piercing approach to be instantly modified to reduce the risk of high resistance connections being created. Such an approach includes creating a pattern or profile on the through contact or the soft contact to increase the contact surface area while improving the penetration efficiency.

If the size is relatively relative and the soft contact is larger than the rigid contact, if the soft contact is located directly on the IC contact pad, the soft contact can be profiled almost automatically. A natural depression is formed in the vicinity of the center of the contact due to the relative height difference between the cover glass on the IC pad and the IC pad itself by patterning the metal for the soft contact in a region larger than the opening for the IC contact pad on which the contact is formed. 142, this profile type soft contact 14202 is shown. As shown, the flexible contact 14202 is formed wider than the IC contact pad I4204. As a result, the rise of the glass 14206 relative to the contact pad 14204 naturally results in the formation of the depression 14208 in the malleable contact 14202. [ Advantageously, this natural depression 14208 makes the flexible contact 14202 more suitable for accommodating the rigid contact 14210, and even when the rigid contact 14210 is substantially close to the size of the depression, Thanks to its natural shape, it helps to align.

Profiling a rigid contact can reduce the initial contact area, effectively increasing the force applied per unit contact area to improve penetration, while increasing the surface area provided by the wall of the profile in the depth direction, A sufficient area of the mechanical contact can be achieved.

For illustrative purposes, Figures 143a through 143h and 143w illustrate some representative, non-limiting examples of the myriad of possible mother contact profiles. In these figures, contact pads of circular, hexagonal, rectangular cross-section are shown in cross-section taken along line A-A and in top view. 143i to 143p show contact pads of complex shapes. For example, a contact pad of a complex shape is shown. For example, an inverted truncated cone (Figs. 143K and 143L) and a reverse truncated pyramidal base section (Figure 143m and Figure 143n), or a post-in-well configuration (Figures 143o and 143p). Examples of other shapes are shown only in side views in Figs. 143q to 143v. Or other three-dimensional shaped contact pads made of a "tire" laminate in the form of a ring or in the form of a pyramid for use with the aforementioned two to three conductor variants, or any other simple or complex combination shape And similar approaches may be used for stereogenic sections.

In another variation, a "wing" as shown in Figure 143v may be used at the base of the contact. Here, the wing can increase the surface area of the contact by increasing the lateral area in the contact in a simple manner.

It may also be desirable to use asymmetric or elongated contacts (i.e., contacts having different widths in different directions to absorb deformation in a particular direction, as shown in Figure 143x). Optionally or additionally, a portion of this asymmetric or elongated contact may be used together such that the contact may be arranged symmetrically about the point of the stressor, but may be directionally deformed in either direction, as shown in Figure 143 . Thus, a more complex version of the contact with respect to the shape of Figure 143y is shown in Figure 143t.

In addition, the profile of the contact may include an undercut as shown in Figs. 143J, 143L, 143N, 143Q, 143R, 143S, and 143U. This undercut serves to increase the strength of the contact, since it provides an area that allows the flexible material to "grab" Likewise, the posts can be patterned to have a larger opposing surface area or total surface area to ensure a sufficient area of the contact even when an incomplete connection is provided. Also, as shown in Figure 143t, a given contact itself can be composed of a plurality of contacts, in which case the individual portions are in an electrically independent state. Alternatively, some or all of them may be electrically connected to each other. This variant provides a larger surface area and an extra effect for more similar shear strength such that if one or more sub-contacts are misaligned, the total contact area can continue to be formed while maintaining a sufficient contact area .

It should also be noted that the specific shape of the contact pad or the shape or configuration of the profiling used is independent of each other. As an important aspect, some of the profiles have been used to increase the effective contact surface area while providing the junction with a shape suitable for the particular application. If a specific contact or profile is not used, then the total current requirement of the contact is subject to the engineering requirement that it can be handled by the minimum allowable amount of contact, and if a particular profile is used, It is possible to increase the surface area to a level sufficient to achieve the desired objective of the possibility that a bad connection may result. Moreover, while discussed in conjunction with stiffness / mother contact, a soft / daughter contact profiled to the topology can be used. In such a case, the configuration of the contact will include the well-known stiffness configuration on the mother wafer in its most usual form.

144 is a photograph of a profiled soft contact of a variant, which has a shape similar to a pyramidal base with rounded corners and a slightly concave upper side.

145 is a photograph of a profiled rigid contact configured to penetrate the soft contact of FIG. 144;

Hereinafter, the contact described above will be briefly described with reference to Figs. 146A and 146B, in which a part of a pair of chips 14600 and 14602 similar to the chip of Fig. 47 is shown. However, in the following description, unlike the chip of Fig. 47, one chip 14602 has a profiled rigid contact 14604 opposite to the non-profiled rigid contact of Fig. The other chip 14600 has a soft contact 14606 similar to the soft contact of FIG. When the two contacts 14604 and 14606 are joined together, a post and penetration fit is formed, as shown in Figure 146B. However, unlike the contacts of Figure 47, each individual mini-post of the profiled contact 14604 is connected to the flexible contact 14606 through the flexible contact 14606, Quot; footprint "of the unconnected contact. Moreover, some implementations of profiled contacts provide additional advantages in minimizing the risk associated with incomplete connections. This independent aspect is also shown in Figure 146B. The gap 14608 is present near the valley 14610 of the rigid contact 14604), the rigid contact 14604 (the gap 14608 is present near the valley 14610 of the rigid contact 14604), the fact that the connection between the two contacts 14604, The additional contact area provided by the profile side 14610 on the contact side 14610 indicates that the connection is acceptable.

It is assumed that, for purposes of illustration, if the rigid contact 14604 is not profiled, the contact area is assumed to be equal to the minimum contact area that can meet the total current requirement of the contact. In this case, if any part of the contact does not form a good connection, the connection is unacceptable and could lead to premature failure during use or may be totally useless. In contrast, in this example the rigid contact of Figure 146 is profiled. Assuming a profile (easily achievable profile) that increases the contact surface area by at least two factors, as shown in Figs. 146A and 146B, if only half of the total surface area produces an excellent connection, Can meet the minimum total current requirement. Therefore, as shown in an enlarged view in FIG. 146B, although there is an area where no contact is formed, this area is considerably less than 1/4 of the contact area required for an excellent connecting portion, have.

Optionally, the profiled contacts may be created using a plurality of small rigid contacts in conjunction with one or more larger flexible contacts to create a single overall connection. For example, a contact may have electrical connections made up of three sets of contact pairs, where each contact pair is composed of a plurality of rigid contacts and one (or a plurality of) soft contacts.

Other variations associated with the profiling concept include the generation of "wells " that are configured to assist or improve alignment, to restrain malleable material, or assist in the formation of good connections, in accordance with certain embodiments. As shown in the following figures and described with reference to these figures, these well-attached variations provide additional advantages and benefits in certain implementations.

147 to 152 illustrate one variant process for implementing the well attaching concept when a mother wafer contact and a daughter wafer contact are paired (Fig. 147). In this variation, the cover glass opening of the daughter wafer is used as a template and is built into a permanent well using, for example, polyimide, SU8, other epoxy, glass, and / or dielectric (Fig. 148A). A similar approach is also used on the mother wafer, except that the well does not surround the entire area delimited by the cover glass. The soft material and (optional) soft cover material are then inserted into the wells of the daughter wafer, note that this material is not filled over the entire depth of the well (Fig. 149A). Similarly, a rigid material is constructed from the pad surface of the mother wafer (Fig. 149B). The wells on the mother wafer are then removed (Figure 150). The well on the daughter wafer is thus held in place.

As a result, the wells of the daughter wafer confine the bonding material (e.g., cover and malleable material) during the penetration process as well as during the tack phase (FIG. 151) and dissolution phase (FIG. The well can also set a depth limit, because the well can be formed at a height that affects the surface on another wafer or well before any other process is performed.

Advantageously, through this approach, the well allows the cover or cap material or the soft material to consist of a material that is semi-liquefied or at a point where it is flexible enough to be an accurate melting point, or at least normally sufficient to diffuse. This is useful when the contacts are placed close together, and the flexibility generated during melting causes the material to expand laterally in an effort to reduce the surface area. For contacts where the distance between the edges of well-free contacts is less than or equal to about three times the height of the soft material, a pre-integrated plan for such use may be desirable (e.g., the soft material is 8 microns high If the distance between the contact edges is less than or equal to about 25 microns, this approach should be considered).

Also, if it is too close to the melting temperature, some material may wet the wafer surface rather than spread, and may flow along the surface. In the case of an unexplained soft contact, such an action may short-circuit between adjacent contacts. Advantageously, by keeping these materials in wells, the flow of material can be blocked by surface tension and the material can be kept in the wells to prevent shorting out adjacent contacts.

For example, if a post-bonding process capable of melting a bonded contact is performed, the well may also be important in some embodiments. For example, if a contact is fabricated at a suitable temperature for the rigid-soft contact to be manufactured, the bonded chip needs to be soldered to the package, but the temperature required for the soldering step is the melting temperature of the contact Respectively. Thus, because the molten material is encapsulated and reattached by the well during cooling, the contact remains intact during the process.

Also, because the well is patterned using semiconductor lithography techniques rather than conventional mask printing or soldering techniques, the well approach is a well suitable for making a number of closely spaced connections.

In another variation, a "recess" of the well process described above may be used. In these variations, the process is performed so that the wells are not filled with the malleable material. These modifications are included in one of the four classes shown in Figs.

Class I (FIG. 153): In this class of well connections, the daughter wafer contains a malleable material and the mother wafer has a rigid well (which appears to be etched in the semiconductor wafer). The walls of the wells are coated with a diffusion layer metal, for example Au. To combine the two wafers, the malleable material on the daughter wafer is inserted and fixed into the well to deform the malleable material. The addition of temperature and pressure during the tacking step causes the flexible material and the diffusion layer to form tacky connections. During the fusing step, the softness of the daughter wafer and the diffusion layer of the mother wafer are mutually diffused to form a metal bond. Depending on the particular implementation, the malleable material comprises a volume material that is slightly larger or at least larger than the well, so that the fixation between the two wafers during the tack step becomes stronger and no voids are formed after completion of the firing step. This class violates the mother / daughter rules.

Class II (FIG. 154): This class is similar to class I except that the wells or soft posts are formed in a shape to automatically or facilitate alignment between two wafers. This class also violates the mother / daughter rules.

Class III (Figure 155): In this class, the posts are rigid and the wells are coated with a soft material to a certain thickness. This is the same as the basic profiled soft contact approach described above except that the soft material has a more pronounced recessed profile and a simple indentation that occurs naturally from the height difference between cover glass and IC pads. The dimensions of the posts and wells are preferably chosen such that voids do not occur after integration (i.e., after completion of the tack and dissolve process).

Class IV (Figure 156): In this class, the wells are coated with a diffusion layer (as in Class I and II, the posts are made of a rigid material but the outside is coated with a layer of a soft material). This is because, if the material ratio of the rigid material is smaller than the material ratio of the soft material, for example, if the rigid material includes copper as the main material but the soft material contains gold as the main material, Lt; RTI ID = 0.0 &gt; I &lt; / RTI &gt;

Advantageously, in the approach described above, the wells may be fabricated or recessed (e.g., by etching the semiconductor) using, for example, a dielectric. The well may also be a by-product of the via formation process. For example, the well may be part of a via that is not fully filled. 157A-157B are longitudinal cross-sectional photographs of a set of vias of 15 micron diameter extending to a depth of 135 microns and vias of a 25 micron diameter extending to a depth of 155 microns, respectively. 158 is a photograph of a similar via that is not filled with all passages to the bottom. As a result, a natural well will be formed by thinning the back side of the wafer until the bottom of the via is exposed. This well can be used as it is in Class I well. Alternatively, a flare or taper may be etched at each entrance to obtain a Class II well.

Figures 159 through 167 illustrate another variation of a Class II type stiffness well attachment approach. This version of the rigid hole well begins with one of the fully formed wafers and pads 15902 exposed through cover glass 15904 (Fig. 159). First, a barrier layer 16002 is deposited over the IC pad 15902 (FIG. 160). Thereafter, the photoresist patterning exposes an area around the IC pad 15902 including a part of the cover glass 15904 (FIG. 161). The wells are automatically formed by a process of depositing the metal with a recess formed by a cover glass on the IC. This makes the patterning easier than some of the other rigid well hole processes. The strip of photoresist removes excess undesired metal remaining behind the fully formed rigid well (Figure 163).

In another class II variation, the wafer 16402 supporting the wafer corresponding to Figure 163 does not have a rigid "post" in the sense previously described, but in the appropriate portion, the insulator 16404 coated with a flexible material cap 16406 ), This variant violates the daughter / mother rules (Fig. 164). The holes in the stiffness formation permit penetration of the soft portion on the isolator with good fit and suitable surface area (Figure 164). As shown in Figure 165, the flexible cap is melted and attached to the post by heating. As shown in Figure 166, during the tack step, the flexible cap is liquid or semi-liquid and fills the void of Figure 165. This is desirable because gases trapped in the voids, such as by expansion and contraction during thermal cycling, can potentially make the contact unreliable. If the soft cap fills voids during the tacking step or at the beginning of the firing step, the fusing step diffuses the soft cap into the flexible material forming the rigid cap and the final connected fusion connections.

Another well attachment strain may be formed using the profiled contacts of Figures 144, 144, or 146. [ In this variant, the well is formed by a pattern of rigid material to form a wall that can prevent liquid matter from passing through. Thus, if properly designed, this approach would allow the well to contain any liquid material or prevent the flexible material from expanding laterally, allowing higher yields at high contact densities, Allows the use of the process with or without use and allows very dense connections.

Figures 168-170 illustrate another variation of the well attach approach where chips are attached to each other by separate remote contacts. This approach is advantageously applicable at least in the following three cases.

1) it is not desirable to place the cover material on the malleable material since it can adversely affect the manner in which the material is bonded

2) For example, if each wafer has a very smooth surface, adhesion is performed at a very low temperature (or even at normal room temperature) in order to improve the processing speed, then the chips are attached by the force of van der Waals When a covalent bond is formed that allows connection by insulator such as oxide, nitride or other dielectrics by means of suspension atom bonding (this avoids or reduces the waiting time to reach the temperature of the component, Potentially reducing the cost of major equipment)

3) As described above, leakage or creep can occur, which can limit the potential density of the actual contact, so that the primary contact does not completely change in liquid phase and self-centers the chips for a subsequent melting process, (In which case a low cost device can also be used to perform the adhesion, since the remote attachment contact can indirectly provide that level of accuracy, allowing the device to be placed at a high pitch of the primary contact Since it is not necessary to have the necessary alignment precision)

By way of example, remote contacts 16802 and 16804 may be made of a material such as indium, at room temperature, and thus may be attached using only the pressure to squeeze the components together. Alternatively, some other low temperature material may be used that can be adhered even if the particular material is not critical and does not adversely affect the whole (i.e., causing a short circuit), even at a high temperature. For example, a low temperature solder (less than 250 DEG C) may be used. If liquid, the surface tension can be performed by low cost equipment, such as a conventional pick and place machine, by aligning the two chips and the deposition process with low alignment accuracy. In addition, the remote contact can be configured so that a simple covalent bond aligns and connects the chip when it is very flat.

In this process, as shown in Figures 168-170, a separate contact is used to connect the device during the initial attaching phase (take-up phase). Figures 171a and 171b show a top view of an alternative remote contact deformation similar to that of Figures 168-170. This isolated contact can be completely detached from the electrical contact, e.g., formed at or around the periphery of the individual chip (Figure 171a), or disposed with the actual electrical contact (Figures 168 and 171b). Also advantageously, the remote contacts described herein are compatible with all variations of the primary contacts, and may have a greater height and width than the primary electrical contacts, since they do not have to be of a closure pitch. Preferably, the primary contact should be high enough not to contact during the attachment process (Figure 169). Note that this attachment or bonding process does not require high strength. Subsequent melting processes of the primary contacts can provide strength to the bonded chip. Figure 170 shows the result of the permanent contact of the primary contact with the high strength bond as the wafer of Figure 169 after the melting process.

In general, as with the tack step, the dissolving step may occur at a temperature and / or pressure greater than that required for the attachment or adhering step of this deformation.

In other words, compression of the attachment contact, such as a material that may change to a liquid or semi-liquid phase during the tack and dissolve steps, may laterally extend the attachment contact and / or heating of the material may cause the material to change to a liquid phase, Opening up to the car contact can potentially lead to electrical shorts. Thus, one advantageous choice is to apply the principle of forming a "well" based electrical contact described herein to a remote contact. Likewise, they can be liquid or laterally stretched without contaminating or shorting the primary contacts during pressure application or at temperatures during the tack or fuse process.

Advantageously, the remote contact may be configured to allow testing of two chips, regardless of the coupling in the tack and melt stages, or before bonding the actual contacts together before coupling. If one or both chips are non-operational (i.e., non-functional or non-functional) after the chip is designed such that the location of the remote contact is the location of a special pad capable of inter-chip communication to test whether the coupling of a particular individual chip is operational, The chip is detached and a new chip is attached.

Also, with proper design, this prior art imitative hybridization testing approach is very useful because the bonding can occur in wafer-to-wafer, chip-to-wafer or chip-to-chip based designs. Thus, the choice of bond type to be used for a given application (i.e. wafer-to-wafer, chip-to-wafer or chip-to-chip) may be partly a factor in the functionality to be tested. For example, if testing is possible on a wafer-based basis, all chips on two wafers can be hybridized on a wafer-based parallel basis by flipping the non-operational chips once and then for reprocessing. Alternatively, this approach may be used where individual dies originate from one or more castings and there is no preferred way of knowing before a given die is a known good die or hybridization.

In yet another alternative form, the remote material may be a material such as a primary contact (e.g., rigid and flexible) that is higher than the primary contact such that the primary contact does not contact during the initial attachment step. Then, during the fusing process, the remote contacts will be more compressed than the primary contacts. Advantageously, by using the same material for the remote and primary contacts, the process is simplified.

From the above description, derived deformations can be derived that establish and combine concepts from multiaxial through vias, well attachments, profiled contacts, and remote attachment deformations.

Variations of the first group include complex contact forms (i.e., conventional single square or non-single point contact forms). By way of example, in the simplest case, a more complex case, similar to a coaxial or three-axis through-chip connection whose cross section is square (FIG. 172A) or circular (FIG. 172B), is shown in an irregularly open or closed There is a generation of a shielded contact.

In the case of coaxial or triaxial contacts, the inner contact is connected so that the outer closure ring is signaled while connected to the role or ground as a ground. When used with a coaxial via (Figure 173), the contact is securely shielded all the way to the other chip. In addition, or alternatively, the coaxial contacts can be used independently of the vias themselves (Figure 174) such that each contact is itself blocked. This ensures that chip-to-chip contacts are spaced closer together than are available without a coaxial approach. In addition, the outer contact rings of each contact may be connected and / or connected to electrically insulated metal on the wafer and / or may form inter-chip shielding (FIG. 175).

If the outer ring of the contact is used as the ground, only the area where the signal propagates passes through a very small opening in the shielding layer, thereby enabling shielding between chips. The same holds true for three-axis connections where there may be other signal pairs in the outer ground. Thus, such contacts are particularly suitable for chips that carry high speed or RF signals.

The second group of variants may be implemented as two chip (or chip-to-package or board-to-chip) connections to protect a connection pad, e.g., an I / O pad, or an external device And a contact approach for forming an airtight seal between them. In this case, the connection pads and / or optics are either present or introduced at the same time and inserted between two elements (e.g. two chips or one chip and package or board). The ring is formed on two elements outside the area to be protected and is configured to be coupled using a soft / stiff or well attachment process so that when the two elements are hybridized together, a closed metal thread is formed around all of them do. This hermetic package is able to withstand most of the environmental conditions because the non-porosity of the metal can withstand most environmental conditions.

An important advantage of some modifications of this approach is that connections can take a variety of geometrically closed shapes, since they use soft and rigid connections (and, on the other hand, other connection approaches such as liquid metal solder). This is in sharp contrast to the liquid phase material that is reshaped to the lowest effective surface area through surface tension (e. G., The cube becomes spherical and the corners become round, etc.), and the technique is based on the ability of the liquid material to move along a predetermined surface of the chip, While being used to transport, it is not possible to reliably assure proper distribution of the material with respect to the contact, to avoid void formation, to prevent potential shorting of the contact when some material is depleted in a given area, none. On the other hand, as a variant of this approach, the approach is largely irrelevant, regardless of the shape, so the simplicity or complexity of the shape is irrelevant - except that the shape is defined as photolithographic (ally) There are restrictions.

Figures 176 through 179 show two simple examples of the above. 176 depicts an assembly 17602 having an area 17602 with an inserted device (not shown) and a rigid 17604 and soft 17606 contacts surrounding the periphery of the device area 17602, As well as the corresponding chip surface configured to form an airtight seal around the periphery. Figure 177 shows a side cross-sectional view along the line A-A of the same chip of Figure 176 after coupling. Figure 178 shows a more complex arrangement in which the stiffness 17802 and soft 17804 contacts have a more complex shape and actually form three different sealed chambers around the device areas 17806, 17808, and 17810. [ Figure 179 shows a side cross-sectional view along the line A-A of the same chip of Figure 178 after coupling.

At this time, not only the via forming deformations but also the rigid / soft contact deformations can be summarized in the form of a table using the tables in FIG. 180 and FIGS. 181A and 181B.

180 is a table summarizing other approaches for forming other variations utilizing the stiff / soft contact paradigm. This table reads downward into a circle of stock by each text containing box representing the step in the process and by each empty box (or portion thereof) indicating that no action is required.

Similarly, Figures 181a, 181b, and 182 are tables that summarize other approaches for forming via deformations, including those described. These tables are also read downward into the original stock by each text containing box representing the steps in the process and by each empty box (or portion thereof) indicating that no action is required. The lower end of Figure 181a is connected to the upper end of Figure 181b.

These examples describe the approaches with reference to an alternative of metal deposition or plating of a daughter wafer on a daughter wafer (a daughter wafer). For the sake of clarity, Figures 183-192 show in greater detail the process flow of a particular example involving metal deposition on a daughter wafer. Then, Figures 196 to 205 show the process flow of plating the daughter wafer with the same starting wafer.

The process starts with each daughter wafer and mother wafer (mother wafer) of Figure 183. Photolithographic patterning is performed on the daughter wafer using, for example, a 10 micron resist object of Hoechst AZ4903 or Shipley STR1075 (Figure 184). A barrier and rerouting layer of 200 Angstroms Ti, 3000 Angstroms Pd and 400 Angstroms of Au is deposited on the daughter wafer and a barrier layer of 1000 Angstroms TiW and a seed layer of 3000 Angstroms copper is deposited on the mother wafer ). A thick dielectric (7 microns) or photoresist is then applied to the mother wafer to form a 14 micron wide IC pad with an opening of 10 microns (Figure 186). Next, the daughter wafer is metallized with an Au / Sn layer at a height of about 6 to 8 microns on the daughter contact on the IC cover glass (typically larger than the smaller one), and then finished with 400 Angstroms of Au (Fig. 187). The mother wafer is metallized on the IC cover glass at a height of 4.4 to 5 microns (Figure 187). The photoresist is then removed from both wafers (Fig. 188). This photolithographic patterning is then performed on the mother wafer to form openings of 15 to 16 microns wide for barrier deposition (Fig. 189). Alternatively, a self-aligned seed etch is performed as needed to ensure that the undercut does not affect the bump. Thereafter, a barrier made of 2 micron Ni finished with 3000 angstrom Au is deposited (Fig. 190). Thereafter, the photoresist is removed (Fig. 191). Finally, the unnecessary seed layer is removed by etching (FIG. 192). This is done as a self-aligning etch using a spray etcher, so that photolithography is unnecessary because Ni / Au allows etching through Cu / Ti / W. If, for example, a spray etcher is not available and self-aligned etching can not be performed, additional photolithographic patterning steps (Figures 193, 194, 195) may be needed to protect areas that are not to be etched. However, for some etch approaches, because of the potential for significant undercuts, for such lithography, the protective photoresist should be wide enough to prevent undesirable undercuts (Figure 193). For example, an etch with a contact at a 50 micron pitch is performed, and as a precaution, protects the area of the IC pad twice the width, in this case 27 microns for the 14 micron pad. However, if a spray etcher is used to perform self-aligned etching, an undercut of less than about one micron is possible, so that very small areas can be protected by such an approach. Thereafter, the dicing, matching, tacking and melting processes are performed so as to be able to combine both.

Conversely, the following process flow for the plating case is shown in Figs. 196 to 205. Again, the process begins with the wafer of Figure 183. First, the daughter wafer and the mother wafer each have a barrier and rerouting (daughter wafer) of Ti0.1 / W0.9 and a seed (mother wafer) layer of 3000 angstrom Cu (Figure 196). 197, photolithographic patterning is performed on the daughter wafer to limit the barrier region to be applied, and a thick dielectric (7 microns) or photoresist is applied to the mother wafer, as in Figure 186 Thereby forming a 14 micron wide IC pad having an opening of 10 microns. The barrier layer is then added to the daughter wafer (Figure 198) and lifts off unnecessary barrier metal (Figure 199) when the photoresist is removed from the daughter wafer. This photolithography is then performed on a daughter wafer using, for example, a 10 micron resist object of Hoechst AZ4903 or Shipley STR1075 (FIG. 200). Next, the daughter and mother wafers are metallized (Figure 201) by plating to a height of 6 to 8 microns (as in Figure 187) on a daughter wafer at a height of 4.4 to 5 microns on a mother wafer on an IC cover glass . Also, for example, a cap of 400 Angstroms Au is applied according to plating complexity. Thereafter, the photoresist is removed (FIG. 202). This is followed by preparation for barrier addition on the mother wafer using photolithographic patterning (Figure 203). The barrier is then deposited on the mother wafer (Figure 204). Again, the photoresist is removed from the mother wafer (Fig. 205). Thereafter, the excess seed is removed by etching using the self-aligned etching as shown in FIG. If a spray etcher is not available, such as the deposition example, additional photolithographic masking, etching and removal steps are required to make the protection area large enough to allow etching undercuts.

At this time, dicing, matching, tack and dissolving processes can be performed as required to combine the two.

Based on the above, it is useful to note the advantages and disadvantages of each approach to assist in the selection of the process approach to be used for a particular application.

The deposition approach for a daughter wafer has the advantage that there is no seed layer and no electroplating, which is a mask process that automatically has the complex precision of Au / Sn. However, this approach has the following disadvantages. That is, it is difficult to control run-through thickness, and if it deviates from the deposition direction, a metal "wing" may occur and an Au regeneration program may be required.

The plating approach for a daughter wafer has the following advantages. That is, it can be supported by a major equipment supplier because it is inexpensive, requires no regeneration, and can be used with conventional and widely available plating equipment. However, the required complex precision is +1.5% / - 2.5%, which has the disadvantage of requiring additional mask steps.

There are three important process variations using a mother wafer.

1) electroless plating (shown in FIG. 206A (chip), FIG. 206B (plating using 6-8 micron Ni) and FIG. 206C (cap using 3000 angstrom Au)

2) a thin resist electroplating process using copper (Fig. 207A (first masking), Fig. 207B (4.5 micron Cu), Fig. 207c (2 micron Ni wrapped in a cap of 3000 angstrom Au) 207e (Excess seed etching removed)

3) thick resist electroplating process using copper (first masking), FIG. 208B (copper plating), FIG. 208C (second masking, barrier and cap), FIG. Seed etch removal)

Each of the secondary advantages and disadvantages are as follows. Advantages of electroless approaches include no barrier deposition, no seed layer deposition, no seed etching, and no masking process. However, the electroless plating of nickel may not be suitable for high-volume wafer yield because of difficulty in controlling thickness or nodule formation that may affect yield. The advantages of a thin dielectric process are: In other words, the process can be more controlled using thinner Ni, copper gives less stress to the IC cover glass, copper is more mainstream and copper electroplating is more controllable. However, the Ni / Au penetration into the mushroom-shaped sidewalls is inconsistent and potentially exposes some copper, the mushroom shape is not suitable for the tacking process and requires additional processing steps (ie, seed deposition, Etc).

The advantages of a thick dielectric deposition process include better contact or "bump" geometry, full coverage of copper by barrier / cap, better control of uniformity and shape, lower Ni nodule formation, . However, this approach may require this approach sprayed etcher, as it would potentially require additional masking steps if self-consistent seed etching is invalid.

With regard to the discussion of deposition and plating variants, some mother and daughter contacts will be described in detail to better understand the process.

Figure 209 shows an example and typical dimensions of a mother wafer contact having a 14 micron wide contact pad disposed at a 50 micron pitch prior to barrier deposition.

210 shows the contact of Figure 209 after barrier and cap deposition.

Figure 211 shows the general dimensions of a mother wafer contact with an 8 micron wide contact pad arranged at a 25 micron pitch.

212 shows an example and typical dimensions of a daughter wafer contact having a 14 micron wide contact pad disposed at a 50 micron pitch formed by deposition.

Figure 213 shows an example and typical dimensions of a daughter wafer contact having an 8 micron wide contact pad disposed at a 25 micron pitch formed by deposition.

214 shows an example and general dimensions of a plated mother wafer contact having a 14 micron wide contact pad disposed at a 50 micron pitch before self-aligned seed etching is performed.

215 shows the contact of Figure 214 after self-aligned seed etching has been performed.

The range of Au / Sn presented in relation to Figures 212 to 215 is representative of a more general range. In practice, about Au _{0 .7} Sn _{O .3} to _.9 Au ₀ Sn _{0. 1} range or a suitable temperature adjustment (ie, temperature increase with increasing Au content and temperature decrease with decreasing Sn content), a wider range may be used.

Having described various penetrating chip connection variations and applications with respect to the electrical aspects of the various chip-to-chip connections, it does not specifically include any additional alternative variations or chip-to-chip signaling utilizing embodiments including unfilled internal trenches or voids Explain the non-transformation.

In particular, if the deepest void is unfilled, an alternative advantageous lamination deformation can be created. By keeping the voids closed but open to each other in the peripheral components, the voids can be used, for example, to help cool the stack of chips.

In this variant, a series of wafers with vias are stacked so that material around the vias protects the via sidewalls in the resulting semiconductor wafer and creates a continuous and adjacent air and liquid fill tube when the wafer is attached. The laminated portion is arranged so that the tube extends through some or all of the laminate. A portion of the tube through the chip stack is covered by a configuration having a condensation region, for example the laminated portion is connected to a tube embedded in the heat sink. When filled with the appropriate fluid (and if necessary, the wick), each of the tubes acts as a heat pipe to more efficiently drop heat from the IC stack.

Alternatively, the electrically insulated metal may be connected to a heat pipe (fins or plates) between stacked chips on an unused chip or extend outwardly therefrom to increase heat transfer capability. In addition, such a pin or plate is formed by a barrier or seed layer, for example, to perform multiple roles by acting as a pin that simultaneously provides a shield or ground plane and multiple roles.

This is accomplished, for example, using internal vias as part of the heat pipe configuration, as shown in Figure 216. Figure 216 shows a simplified form of a portion 21600 of a stack of chips made up of any number of the same or different individual laminate chips 21602-1 to 21602-n + 1. In this example, each inner metallization 2402 is connected to the top or bottom (using processes such as post and penetration connections or any other approach such as wafer melting or equivalent bonding) to seal the inner voids together, 0.0 &gt; 21604 &lt; / RTI &gt; Suitable fluids 21606 (and wick 21608, if necessary) are contained within the tube at the proper pressure to provide heat to the individual chips 21602-1 through 21602-n + 1 &lt; / RTI &gt;

Depending on the particular implementation, one end of the tube may be a surface of doped semiconductor material or substrate 21612 (i.e., the tube does not go to all passages) or other chip within the chip that does not include a portion of the tube, &Lt; / RTI &gt; Also, the plurality of tubes may be formed with different operating fluids or different pressures for each working fluid (same or different) to have different evaporation and condensation temperatures. In this way, a wider range of heat pipe operation can be obtained. In addition, these heat pipes can be grouped or dispersed relative to the chip relative to thermal "hot spots" on the chip.

In some variations, if present, the wick 21608 may be formed of, for example, a porous or capillary structure, a sintered powder, a slotted tube, a mesh, a carbon nanotube structure, graphite, &Lt; / RTI &gt; Also, the operating fluid may be any heat pipe fluid, provided it does not corrode, degrade, or adversely affect the contacting surface (i.e., doped semiconductor, substrate, insulator, conductor metal, etc.). Typical working fluids may include water, alcohol, acetone or, in some cases, mercury. In addition, in any variation, materials that are solid at Atm (101.3 kPa) and 68 [deg.] F (20 [deg.] C) can be used when evaporated or sublimed in an appropriate manner to provide for the transfer of the necessary heat of evaporation to the heat pipe. Finally, if it is suitable for the dimensions of the insert to the inner vias, a preformed (i.e., a pre-fabricated heat pipe) can be used.

Advantageously, the approach can increase the effectiveness even if the cooling method is additionally employed, since the heat pipe can be located close to where the heat is generated and these heat pipes can be scattered through the chip. The approach described above can also be used to create a heat pipe within a chip where electrical connections are needed.

It is preferable to electrically insulate the chips from each other to prevent electric crosstalk. Further, when devices are stacked to obtain the advantage of one of the via processes (or variations thereof) described herein, there may be applications where it is desirable to couple the two chips to a third chip that communicates with them, . &Lt; / RTI &gt; As is apparent from the above description, the process of forming a wafer-to-wafer connection can be performed at any location or location where the paired chip contacts for the remainder of the wafer (i.e., on one or more chips) And the number of contacts. This means that in some cases a single daughter chip connects two or more mother wafer chips or "daughter wafer 2" chips connects two daughter chips or mother and daughter chips. Thus, the connection is a simple application of an additional process of a "daughter wafer" or "daughter wafer 2 &quot;, and a set of connections having the same process but not connected to the mode of the daughter chip has a counterpart on the same chip. However, in any of these variations, the two base chips (i.e., the chips to be connected by a single chip) may have different heights. Therefore, it is necessary to handle such height difference. Advantageously, another variant of the via process can achieve this. Figures 217a through 217b illustrate two examples of the method. Fig. 217a shows a separation form of this modification, and Fig. 217b shows a connection form. In both cases, the same shield gain can be obtained. In combination with the previous approach, in step 1, one or more chips with vias are attached to the base chip. In this case, a via (or another contact post connected to the upper chip) is fabricated to extend an arbitrary distance over the attached chip. This can be accomplished, for example, by plating a metal or removing substrate material to expose more metal, depending on whether a via process transformation is used. In this approach, vias are typically fabricated before the chips are joined together. In the case of the chip of Figure 217b, in step 2, the wafer may be coated with a layer of a non-conductive dielectric such as polyamide, BCB, another polymer, an oxygen or nitrogen dielectric or other non-conductive material that may be deposited on the surface of the wafer have. In the case shown in Figure 217a, the thickness of the layer is determined by the need to separate two vertically stacked chips from each other. This thickness is usually greater than the width of the signal line (e.g., &gt; 5 microns), but because the signal strength decreases with distance and the capacitive coupling decreases proportionally with distance and EMI interference decreases in proportion to the square of the distance (E.g., greater than 25 microns) for better separation. As shown in Figure 217b, the two attached chips may have different heights. The reason for the height difference is not related to the process but is otherwise etched or thinned to produce a height difference of more than 100 microns depending on the storage during the process due to lapping or polishing on a substrate originally having a different thickness . In some cases, the coating material may be added to the same height as the top of the thickest chip attached to the base chip. If a rerouting layer is not required (described below in conjunction with step 4), this step 2 is optional in any variation of Figure 217b. In step 3, the wafers are lapped or polished to expose vias or other large plated or metallized connections of various chips. In step 4 (optional), to facilitate connection, the surface of the polished / wafed wafer may be patterned and (if necessary) an electrically rerouting layer deposited on the surface. This allows the two chips that do not have matching pads to be connected together by routing signals that need to be connected together. Also, in the context of Fig. 217b, the rerouting can cause two chips in the bottom layer to be spaced farther apart than corresponding connections on the top chip disposed in step five. In step 5, in Figures 217a and 217b, another chip is attached to the structure by one of the bonding method variations using, for example, a soft or rigid bonding process. The process of steps 2 to 5 is repeated to add a subsequent layer (assuming that the chip attached in step 5 has or does not have a post extending an appropriate distance from the surface to the top). Advantageously, the chip of step 5 does not have a via unless it is connected to an additional layer on top of the structure.

Figures 218a and 218b illustrate alternative variations to accomplish the tasks of Figures 217a and 217b. In this alternative variant, the holes are etched with a planarizing material such as polyimide, rather than thinning the chip as in step 3 of the process of Figures 217a and 217b. Then, if necessary, the rerouting layer of step 4 is used to change the route of the electrical signal and connect to the lower chips. Next, hybridization as shown in step 5 of FIG. 218A or FIG. 218B may occur. This procedure is more complicated than the method of Figs. 217a and 217b since electrical contact is required after bonding. However, as shown in step 6 of FIG. 218b, this process is more advantageous for simultaneous connection with multiple other layers of a later chip than in FIG. 217b. Since the wear process in step 3 of Figure 217b can wear all the posts at the same height, it is more difficult to do the same in the method of Figure 217b, so that the upper level daughter chip is placed at the lowest level It is difficult to adhere to the daughter chip.

As is known herein, any number of elements can be stacked highly. However, in some special cases, tack, fuse, tack, fuse approach, or tack, tack, tack, and overall fuse approach In addition to determining whether or not it is applicable, the effects of the stacking and the geometry need to be considered. For example, in a wafer-scale laminating process as described herein, via through-via connections, whether the original daughter wafer should be thinned in advance before being diced to engage the mother wafer, or whether the daughter wafer should be thinned Chip or full wafer basis) and then thinned. The difference is as follows. The tack, fuse, thin, tack, fuse, and thin approach are less number of steps and, more importantly, can reduce yield when thinned before dicing and bonding. The advantage is that you do not have to deal with very thin wafers. However, this has the disadvantage that it requires less labor on the joints, i. E. Thinning over the more expensive joints compared to the daughter wafer (s), which can reduce the yield.

Another disadvantage arises when several daughter stacks with different chip counts are located on the mother chip. Since the separate thinning step needs to take place in each layer of chips on the mother wafer, the arrangement and order of the thinning is important. As a result, without proper planning, some stacks can not have additional chips because they are located below the height of the adjacent stack. This makes it difficult or impossible to thin the chip.

On the other hand, there is an advantage that thinning before bonding can always be performed, but there is a disadvantage that there is a large risk for having a thin wafer as described above.

An application example of a number of different alternative, selective, complementary variations described above will be described with reference to Figs. 219 to 221. Fig. Figures 219-221 illustrate some additional advantages that may be achieved in a particular application, i. E., A microprocessor application.

Figure 219 schematically illustrates a typical microprocessor chip 21900 of the prior art. (ALU), a register (REG), a buffer and other logic devices (BUFFER & LOGIC), an input-output (I / O) A first level cache memo L1, a second level cache memory L2, a memory control unit MEM CTL, a memory read-write control unit R / W CTL, a RAM, a ROM, Decoding circuit (RAM / ROM DECODE). As shown, these components occupy considerable area, and the distance between any given component and the other components is quite long.

220 schematically illustrates how an alternative microprocessor is formed from the same components using the methods described above. On the other hand, such a microprocessor has a smaller footprint, mixes high and low speed technologies, and substantially reduces the distance between components. Especially. 220A illustrates an example microprocessor chip 22000 having reduced footprint through use of through-chip connections as described herein with the components of FIG. 219 and stacking of components. Through the lamination, the components are formed into chip devices 22002, 22004, 22006 (side view), which are also shown as an exploded view 22008, 22010, 22012, respectively, and the footprint covered by their subcomponents Reduce overall. In addition, as shown in the respective side views 22008, 22010 and 22012, the distance between all subcomponents of each chip device 22002, 22004, 22006 is substantially reduced due to the through-chip connections. Moreover, the chip-to-chip connections in the chip devices 22002, 22004, and 22006 need not be substantially circumferential, but in fact are located at almost any location on the sub- Can be.

FIG. 221 directly compares the footprint of chip 21900 of FIG. 219 with the footprint of chip 22000 of FIG. Both are small in size and few in number, but obviously the latter footprint is substantially less than the former.

If the chips are designed with the possibility of stacking in mind, other advantages can be achieved. For example, in the example of FIG. 220, each subcomponent chip can be designed independently and only needs to share a common interface with other chips, so that different mix endmatches of processing devices 22006 and 22012 Mix and match configurations can be designed. Thus, a number of different arithmetic logic units (ALUs) having different speeds can be designed, thus making it easier to form a collection of cavities of processing chip devices. Likewise, second-level cache memories L2 of different sizes may be designed for use in processing chip device 22006 for discrimination or performance enhancement, the point of which is price in groups. This concept is a specialized case as described below as a sensible and active packaging.

As can be seen from the preceding discussion, the results of the processes and aspects described herein are the ability to form different types of packaging more efficiently than previously used.

At present, complex integrated circuit chips are fabricated and packaged as shown in FIG. Through front-end processing, low-speed functions, high-speed functions, input / output and high-speed (ie, core analog and digital) functions can all be formed on a single chip. Next, back-end processing adds metallization within the layer to form connections between the various on-chip devices. Finally, once the chip is complete, the chip is bonded to a separate package, such as a pin grid array, a ball grid array, or a conventional IC package. This method has many drawbacks, including the requirement that all devices must be implemented with the highest speed / highest cost technique necessary for any on-chip device because all devices are located on the same chip. As a result, high cost "real estate" is wasted on low cost and / or low cost devices that can be easily implemented with low or low cost technologies.

However, by using the aspects described herein, various forms of packaging can be utilized, some of which in turn help in the risk of cost optimization, processing time, and yield. For example, through the use of the aspects described herein, configurations as shown in Figures 222b through 222f can be made.

Figure 222b illustrates an exemplary deployment example made using aspects described herein. This is called a routingless architecture because it isolates the routing process from the chip formation process and allows them to run concurrently. In this arrangement example, a first chip (Chip 1) is formed using front end processing with low speed function, input / output and core analog and digital functions. A second chip (Chip 2) is formed using back end processing to form metallization layers connecting devices on the first chip (Chip 1). The first chip and the second chip are then joined together, for example, using a wafer-to-wafer or covalent bond method, wafer fusion, or the like, for example, using one of the methods described herein. This combined device can then be treated as a conventional chip and connected to a conventional package in a conventional manner, or it can be processed for bonding with another wafer, chip, or device as described herein.

Another alternative method is shown in Figure 222c. This method is called the "chip package" method because the chip connections are part of the package. This method may be implemented on a wafer part in which back-end processing may serve as a package for the first chip, or in the method of FIG. 222B, except that the back-end processing for forming the routing is performed on one wafer. Which package is formed on another package such that the two are processed and combined together as described herein to form a second chip in the process. Thereafter, the first chip and the second chip of the method can be processed and combined together as described herein. Optionally and alternatively, the machining necessary for the combination of the first chip and the second chip may be performed in whole or in part as part of the machining required to join some of the routing portions to the package portion. Advantageously, with this method and an appropriate design plan, the second chip design is comprehensive to a number of different first chip designs, resulting in potential cost and other savings.

Another alternate method is shown in Figure 222d. This method is called the "active package" method because it adds low speed functionality to the package second chip that faces the portion of the primary chip. Thereafter, the first chip and the second chip may be coupled together and connected together through suitable means for a particular application. This can reduce the use of expensive real estate by low / low cost devices. Here, if the slow function is more comprehensive, more advantages and savings can be achieved.

Another alternative method is shown in Figure 222E. This method is referred to as "active package with I / O ", similar to the method of Figure 222D except that the input / output is moved from the first chip technology to the second chip. Thus, in this way, the first chip only includes core analog and core digital functions. Here, the chips may be combined or otherwise connected together for operability. Again, because input / output is typically slow and large in size, substantial savings can be achieved in this manner. Likewise, by careful design, the second chip of the method is comprehensive to many first chip designs, thus also providing the advantages of the prior art method of Figure 222A.

Another most sophisticated alternative of the methods is shown in Figure 222F. This method is referred to as " system on chip "or" system stack ". In this way, there is only core digital functionality on the first chip of the appropriate speed / cost technology. The second chip is likewise formed and has core analog functionality with the appropriate speed / cost technology. In addition, the third chip is formed and includes only input / output functions executed by its own appropriate technology. Finally, a fourth chip, essentially corresponding to the second chip of Figure 222D, is formed. Advantageously, through this method, important mixing and matching can occur, in many cases, because the first chip, the second chip, the third chip and the fourth chip designs are designed to have only chips intended to be attached . Moreover, apparently, this method can be such that each chip is, for example, a chip in a group of chips that all share a common interface for its function.

Thus, both of the methods of Figures 222B-222F enable the formation of sensible and active packages, so that designers dismantle their designs so that most, if not all, of the circuits use the technology best suited to their function. In some cases this means the creation of a completely new design, and in other cases it means the use of a combination of existing chips. Both of these cases use one or more aspects of the variants described herein. In this regard, the functions appearing in these examples are not intended to mean that certain aspects should be disassembled in the manner shown, but merely to illustrate the concept. Also, for example, a chip with some analog functions and some digital functions and another chip facing a single chip for each functional group can be formed, and the point is that parts of the overall design are suitable for them It is in the ability to adapt to the technologies. It is also possible to achieve results that were previously impossible or cost prohibitive due to functional consequences similar to those made conventionally (e. G., Fig. 222A) or due to inherent constraints in the prior art method of Fig. 222A through the methods of the present invention can do.

As a result, low performance circuits can be designed on a single chip, and high performance chips can be designed for higher performance technologies. Moreover, this type of method is more cost effective, since a significant amount of high-speed technology real estate can be saved by moving a low speed circuit off-chip without the need for powerful signal driving circuits. Some examples of the myriad possibilities associated with the high level description of the processes described herein are shown in Figure 223.

Thus, some of the aspects discussed above are discussed in further detail. Presently, in order to manufacture electronic chips, wafers must undergo two sets of processes, such as front-end processing and back-end processing. In the front-end processing, actual devices including transistors and resistors are fabricated. In the case of a silicon chip, this can be achieved, for example, by the growth of silicon dioxide, patterning to obtain the desired electrical properties and implantation and diffusion of dopants, growth or deposition of gate insulators, &Lt; / RTI &gt;

In back-end processing, the various devices fabricated during the front-end process are connected to form desired electrical circuits. This relates, for example, to the deposition of a trace metal, which forms the connection as well as the insulating material and its etching into the desired pattern. The metal layers are typically comprised of aluminum or copper. The insulating material is typically silicon dioxide, silicate glass, or other low insulating constant material. The metal layers are connected by etching the vias in the insulating material and depositing tungsten therein.

Currently, in the case of 12 "wafers, each of the front and back-end processing using 90 nm processes takes about 20 days to complete and they occur continuously. As a result, Days.

Advantageously, using the processes described herein, the above methods can be applied to the most widely known submicron design rules based on chip manufacturing techniques, since both front and back-end processing occur simultaneously in different unrelated factories (For example, 0.5 占 퐉, 0.18 占 퐉, 0.13 占 퐉, 90 nm, 65 nm, 45 nm, and the like) can be reduced by almost half. This enables front-end processing on one wafer (front-end or FE-wafer) and parallel execution of back-end processing on another wafer (back-end or BE-wafer) . In this way, it can be implemented in a factory where routing is low for a portion with transistors or other devices, each taking approximately 20 days. The connection points are then obtained by thinning the wafer and forming connection points on the back side of the FE-wafer using a variant of the via processes described herein. In a similar manner, the processes described herein are used to form a set of complementary attachment points on the BE-wafer corresponding to the attachment points of the FE-wafer. Then, for example, if malleable and rigid corresponding connections are formed (typically the FE-wafer is a daughter wafer of the above processes with malleable contacts) tack and fuse approach, described herein (E. G., Using a remote attachment approach, a shared or other wafer surface bonding method (by itself, a through-via method, and / or the use of a simple filled via that serves to hold the two wafers together to maintain alignment, Or with alternatives), the two wafers are bonded together.

Advantageously, through this method, the metal layers required by the topology and stress constraints imposed by the increasingly sensitive transistors need not be limited in thickness or density. Also, by separating the process into two chips, the lines can be larger and more layers can be formed, increasing chip intercommunication capabilities and lowering parasitic resistance for faster chip-to-chip communications.

Advantageously, since the method of the present invention is independent of the particular fabrication or connection technology used to fabricate a particular FE-wafer or BE-wafer, or the design rules applicable to such fabrication, Techniques can be used to run together at the nano-level. In other words, the methods described herein are applicable to any chip design rule where devices or their connections are made of a material (Si wafer, GaAs wafer, SiGe wafer, Ge wafer, InP wafer, InAs wafer, InSb wafer, GaN wafer, GaP wafer Sub-micron or sub-nanometer sub-micron or non-sub-micron sub-nano sub-nano sub-nano sub-nano sub- whether or not any methods resulting from a high-resolution mask or a non-mask are used to form the nanometer characteristics or to define the spacing between the geometries of the devices, their connections, or the connections themselves, It does not matter. Thus, it should be understood that the chip fabrication techniques described above may be used to fabricate semiconductor devices, such as SiGe, silicon-on-insulator (SOI), junctions from carbon nanotubes, biochips, To other methods that are designed to provide high performance and / or to reduce the required power.

Figures 224 to 231 schematically illustrate this method. As shown in Figure 224a, the FE-wafer 22402 on which the front-end processing has been performed to form transistors and other finished devices may include front-end devices protected with a photoresistor or other removable protective material 22502 Thereby providing a support (Fig. 225 (a)). The FE-wafer is then thinned (i.e., removing some or all of the underlying substrate) to a thickness of a few microns or more as needed due to the desired or desired height for the mixed FE / BE chip. The vias can then be removed from the back of the FE-wafer to the appropriate device connection location points, for example, using a backside process as described herein or simply a via process as described herein, (Fig. 227A). Alternatively, one or more through-vias 22702 having a slightly widened shape on the device face, for example, having a malleable contact on the backside may be used, for example, a well or a reverse well approach ) Or a surface of a pressure fit connection. These vias serve to secure the FE and BE-wafer chips together horizontally with respect to each other, when a shared or wafer side joining method is used. In addition, a receptacle for connections between chips having the form of vias to be part of the heat pipe arrangement or the non-electrical communication arrangement (both of which are described in detail below) may be added. Then, the vias become conductive (Figure 228), and the FE-wafer is ready to be bonded to the BE-wafer.

At the same time, a metallization layer 22404 is formed on the BE-wafer (Figure 224b). In this structure, no protection / support is required because the semiconductor material serves as a protection / support. However, if it is substantially excessively thinned, the application of a removable support layer may be necessary. 226b), if necessary or a complete penetration into or through a particular inner metal layer is required (Figures 227b, 228b), vias are formed (also shown in Figure 226b) 227b, and metallized (Figure 228b). In addition, depending on the specific performance, contact with the inner layer can be made by physical connection or non-physical (i.e., capacitive) coupling. Otherwise, for example, when a post and penetration / tack and fuse approach is used, a complementary connection, such as a complementary connection to a strut or well, reverse well or other connection, Are formed. Likewise, complementary fixed vias (22704 in Figure 227b) may be added to the BE-wafer, or vias may be added that are part of the heat pipe arrangement or the non-electrical communication arrangement. Furthermore, when a heat pipe arrangement is used, it is desirable to use BE-wafer metallization (Figure 228b) to seal one end of the heat pipe. This is especially the case where rigid tack and fuse methods are used due to the strength and tightness of the seals that can be formed.

The FE-wafer and the BE-wafer are then aligned with respect to each other (Figure 229), once they are brought together (Figure 230) (Figure 231), they form a complete wafer unit of each electronic chip do.

Figures 233 through 235 show other variants of the method described above. As with the approaches of Figures 224 to 231, these alternative variations include an FE-wafer (also referred to as a FE-wafer) comprising a semiconductor device 23202 (i.e., transistor, laser, photo detector, capacitor, diode, etc.) doped on a substrate 23204 232A) and a BE-wafer (FIG. 232B) with metallized device interconnections. However, unlike the method of Figures 224-231, the BE-wafer is flipped, aligned, and bonded to the top of the FE-wafer, which occurs before the substrate is thinned (Figure 232A). Alternatively, the same method as in FIG. 232A can be performed as shown in FIG. 232B, so that the BE-wafer can be thinned before bonding.

Another alternative method is shown in Figure 234. In this case, the BE-wafer is thinned to expose the innermost layer of the original chip from Figure 232B, which is bonded to the top of the FE-wafer.

Figure 235 shows another improvement or alternative variant. As a result of the methods of Figures 231, 232b, 233b, or 234, after bonding, the other side of the metal of the BE-wafer is exposed. Thus, another chip may be bonded to the metal to create another form of chip stacking method.

Another advantage of these methods is that, if needed, other rerouting of the connections can be made on FE-wafer or BE-wafer (or possibly both wafers). Thus, FE-wafers and BE-wafers can be formed more inclusive, while providing the appropriate connection locations for a particular application. Moreover, mixed FE / BE-wafers or FE / BE / FE-wafers or chip stacks can be treated like other wafers formed using all of the conventional processes, ) &Lt; / RTI &gt;

Moreover, through the use of chip-to-chip optical connections, chip devices can be designed that use higher speed communication between chips rather than having wired connections due to problems associated with crosstalk that causes interference . For example, by placing a semiconductor laser on one chip in a stack and placing corresponding photodetectors corresponding thereto on other chips in the stack, optical connections other than wired connections can be formed between the two. When this semiconductor laser and the photodetector are located sufficiently close to each other, the possibility of optical crosstalk is minimized. This aspect is illustrated schematically in Figure 236, which shows a portion of chip device 23600 including two chips 23602, 23604. One of the chips 23602 has a laser 23606 on top thereof and the other chip 23604 has a photodetector 23608 on top of it so that the optical signals emitted from the laser 23606 Detector 23608. &lt; / RTI &gt; Moreover, the techniques described herein facilitate optical communication between chips, even if one or more chips are placed between the two chips. For example, even if two other chips 23702 and 23704 are placed between the two chips 23602 and 23604 as shown in FIG. 237, light from the chip 23602 with a laser is reflected by the photodetector A modification of the heat pipe arrangement may be formed to allow the chip 23604 to reach. To this end, a through-chip approach is used, but the internal space is not filled with any electrical conductors nor is it left open for use in heat pipes. That is, the inner space is filled with an optical transmission medium 23706, such as an optical epoxy or other light-transporting material, to form an optical waveguide. With the use of optical waveguides, the metal and / or insulator confines the light, allowing the via to behave like an optical fiber. Moreover, by adjusting the via size and the composition of the external metal or insulator, the waveguide can have essentially the same characteristics as single mode or multiple mode optical fibers. Also, in a variant with a "central island" of silicon, if the central island is not thermally oxidized and removed, this oxidation will cause the central island to become silicon dioxide, . Thereafter, the laser light can be carried through the chip (s) placed between the optical transmission medium 23706 by locating the laser at one end of the waveguide and placing the photodetector at the other end of the waveguide.

Specific substitution of the contact material and the example (Alternatives)

As described below, the fairly complex contact surface due to the tack and the self-characteristics of the fusing process is repeated in a simple form as shown in Figure 238. [ Accordingly, it is important to note the alternative materials available for the components of the daughter wafer 23802 and the mother wafer 23804 contact.

Generally, for any purpose, the daughter wafer contact 23802 of Figure 238 will include the functional layer shown in Figure 239. Likewise, the mother wafer contact 23804 of Figure 238 will also include the functional layer shown in Figure 240. It is noteworthy that the contacts 23802 and 23804 each have a function layer composed of one or more material layers, or one material layer can sufficiently serve as a multiple function layer. This can best be explained by a specific example of the daughter wafer contact shown in Figure 241 and a specific example of the mother wafer contact shown in Figure 242. [ As can be seen from the figure, any particular layer can be made of a component material, an alloy thereof, or a superlattice.

Referring again to Figure 239, in the case of an electroless variant, the daughter contact 23802 includes the following components.

Barrier layer: Ti / W + Pd

Standoff layer: None

Diffusion / malleable layer: gold / tin (80/20) (1 to 12 microns)

Cap / adhesive layer: gold (> 500 Angstroms; typically 1,500 to 10,000 Angstroms)

Oxidation barrier: The cap / adhesive layer also acts as an oxidation barrier. The soft layer may be composed of a combination of an insulating layer, a diffusion layer, a cap layer and a barrier layer. In the present invention, the soft layer is a combination of a diffusion layer and a cap layer.

Likewise, with respect to the mother contact (see FIG. 240), the mother contact 23304 includes the following components:

Barrier layer: No Cu / Al pad

Rigid layer: Copper (> 2 microns)

Diffusion barrier layer: nickel (5000 Angstroms; typically 0.5 to 3 microns)

Cap / diffusion layer: gold (> 500 angstroms; typically 1,500 to 10,000 angstroms)

In the context of the foregoing, non-limiting examples of alternative materials that may be used in certain contact layers will now be described.

Ti / Pd / Au, Ti / Pd / Au, Ti / Pd / Au, Ti / Pd / Pd / Pt / Au, TiW, Ta, TaN, Ti, TaW, and W, but may be omitted if the pad is made of the same material as the insulator. Examples of the insulating layer / stiffness layer (mother) include Ni (especially when the barrier is nickel), Cu (especially when the pad is copper), Al, Au, W, Pt, Pd, . When sputtering is performed instead of plating, any metal having a melting point higher than the melting point of the soft layer (generally, higher than 50 ° C) may be used. These metals can also constitute barrier materials.

Ductile (Diffusion) Substance: A metal having a low melting point is a metal having a melting point lower than that of 1,000 占 폚 such as tin, indium, lead, bismuth, aluminum, zinc, magnesium, etc. or a combination of two or more of these metals or silver, copper, It is an alloy in combination with a metal having a high melting point such as water. Examples of the combination include Au / Sn, Cu / Sn, Cu / Zn, and Bi / Ag. What is important in this selection is that the process is very slow, the cost is increased, and there is a problem of creep or running that limits the density by causing contact shorting, It is not suitable for melting. The combination of soft layer / rigid layer ultimately gives strength to the contact. In general, it is preferable to select an alloy containing a compound containing at least one selected from Au, Ag, Bi, Cd, Cu, Fe, In, Pb, Sn, Sb and Zn. In the presence of an insulating layer, the most important requirement is to have a melting point equal to or lower than the melting point of the rigid post. Generally, the inventors used a melting point of 100 ° C to 500 ° C, but the soft layer should be at least 50 ° C below the melting point of the rigid layer. The ductile material is composed of a variety of materials and has the advantage that it can provide the appropriate height necessary to relieve the non-planarity of the contact. In fact, a malleable material can be formed on the upper part of the insulator post of the rigid material. For example, in some cases, the soft material is composed of Au / Sn and is up to 5 microns. In other cases, it may consist of a stack of rigid materials (such as nickel 4 microns) covered with a thinner layer of soft material (e.g., 1 to 1.5 microns).

Flexible cover material (cap / adhesive layer): They have a wet at temperature such as low temperature metals (or alloys) such as tin, indium, lead or zinc. It is important that such cover materials are generally much thinner in thickness than the layer of soft material. For example, it will usually be about 10 to 20 times thinner. For example, the soft (including the isolator) material is up to 5 microns and the soft cover material is 0.5 microns, typically in the range of 0.1 to 1 micron (or about 50 to 5 times thinner than the soft layer thickness). As such a cover material, tin (Sn) is preferable. This cover material has a low melting point and turns into a liquid in the tacking process. However, because the thickness of the layer is very small, there is no shorting between adjacent contacts, even if it is not fully liquefied. At the same time, since the tack step becomes a liquid phase process, the cover material can be attached more quickly to the rigid cap. Generally, the cover material should be selected so that after fusion, the resulting combination is compatible with the flexible material to be suitable for strong bonding. Taking an annotation as an example, this approach can be applied to Au / Sn contacts that mostly include tin caps.

When used in a "tack" process, the adhesive layer is an easily oxidizable material such as tin or zinc, and can be covered with a very thin oxide barrier. have. Alternatively, the oxide may be removed using a reactive gas or liquid in the tapped process, or the oxide should be decomposed using sufficiently high pressure, which may occur when indium is used as the cap. The cover material may be epoxy. For most materials, a thickness 10 times thinner than the cap is used. The soft cover material may be a hot material that becomes a low temperature alloy (or adhesive) when the soft cover material begins to mix with the rigid cover material or the soft cover material. For example, if the two covers are two parts of a mixable epoxy, or if the oxidation barrier is gold and the soft layer is gold / In the process, when the tin is intermixed into the oxide layer, the material has a lower melting point. In general, this layer may be a metal / material that is not easily oxidizable (Au, Pt, etc.).

FIGS. 243A to 243C are photographs of cross-sections of actual contacts (mother and daughter) formed using this variation in the tack and fuse process, showing examples of other layers and how they interact with each other.

Figure 243a shows a pair of contacts joined with a mother wafer and a daughter wafer after the tack step in the tack and fuse process is completed. As can be seen, the bond between the two is excellent, but not as persistent, as evidenced by the large area of non-bonding material.

Figure 243b shows a similar pair of contacts after completion of the fuse step. Here, as in the case of using the barrier, it can be seen that the coupling is continuous. In Figures 237a and 237b, it should be noted that the soft material is significantly trapped between the barriers.

Figure 243c is a photograph of a similarly coupled contact pair after the fuse step. In the photo above, the components are not clearly visible, but the IC pads of the mother and daughter wafers can discriminate the relative relationship of size between the two.

Connection-related tooling ( Tooling )

It should be noted that the various approaches related to the interconnections of chips, die and wafer substrates with chips, and details that can make use of many permutations, variations and combinations thereof, have been described and may be advantageously employed to contribute to the bonding process You can branch and explain various types of tooling. Of these tooling methods, it is not important to achieve substitution, modification, and combinations thereof, but rather, they are developed to facilitate the process and to other chip-related processes such as "pick and place, And is particularly preferable for simultaneous execution on multiple chips, and at the same time when chip heights are different from each other.

For purposes of illustration, reference will be made to tooling variants related to their use in tack and fusing processes, but since variations are part or minor variations of the method, understanding of the method need not account for simpler use.

As described above, the attaching process is performed in two steps. The first step is a "tack" step in which chips are lightly adhered to each other, and the second step is a "fusion" The tack phase heats the contacts and causes the contacts to be adjacent to each other under low pressure, allowing the materials on the two corresponding contacts to interdiffuse.

 During this process, by applying a low pressure so that the chip does not move during the process if gravity alone does not provide the necessary pressure enough, it is possible to prevent the adhesion of the contact and prevent mechanical contact of the attachment surface, which makes it impossible to resist wafer handliling Reducing the likelihood of shock or non-uniformity. In addition, the pressure can be adjusted to a certain degree when the soft material partially or entirely becomes liquid due to the partial heating (or is not simply liquefied and is more flexible than the theoretical one so as to interfere with pressure and surface tension or other forces, In the case where ductility occurs), it is possible to prevent excessive and independent lateral movement of the portion. Therefore, manufacturing tolerances and deviations can be identified by applying a lower pressure to ensure a wider temperature and a tolerable range of processing conditions in the fusing process.

However, one of the problems of applying pressure to the chip is that, in the case of a multi-chip with a substrate element (e.g. a wafer) attached, each chip may not be on a plane and may even vary significantly in height to be. Accordingly, when simply placing a flat surface or a flat plate on the chip, the applied voltage will be applied non-uniformly.

As will be described below, a method designed to derive the foregoing is to utilize a placement of a source of force and a chip that allows for the same pressure to be applied to all chips, either by following a different height or by identifying it.

One of the ways to achieve the use of this arrangement is to use a series of pins or posts matching each chip based on a one-to-one arrangement. Two variations of the method will now be described, with the understanding that different tooling methods can be combined with the characteristics of each of the tooling methods described below or with the characteristics of other tooling methods.

Figures 244 to 247 show an embodiment of tooling for performing a pin or post series method.

As shown in FIGS. 244 and 245, the method uses a pin or post set 24402 within frame 24404. Each pin or post may move along at least a longitudinal axis (in some embodiments, a plane or slope may allow for a sleight angle of the pivot if it is a potential feature). The posts or pins can be retracted and separated. The posts or pins have a surface disposed to contact one chip.

According to one embodiment, the surface of a given pin or post may be flat, a die in opposition to a pressurizing chip, or any other form suitable for a particular application. In addition, the fins or posts on the surface or adjacent thereto may be circular in shape by itself or in non-circular (e.g., oval, square, hexagonal, octagonal, etc.) closed form. In addition, the perimeter and planar area of the surface may be larger or smaller than the boundaries and area of a particular chip that is adjacent (e.g., extends to the periphery of the chip or may include some or all of the interior). It is important to arrange the surface so that it can apply force to the chip, without damaging the chip (especially cracking or chipping).

In use, the posts in the frame are lowered (in some cases, the frame itself) until the posts meet the chip properly in voluntary conditions (Figure 245). In this case, the pin is fixed in the proper position. As a result, an appropriate amount of force can be applied to the frame (in the embodiments, the pin or the post). As the tool moves downward, it exerts a force perpendicular to the chip so that force can be evenly transmitted to each chip through the pin or post.

Thereafter, in accordance with the present invention, or otherwise, the bonding process can be proceeded as described above.

246 and 247 are similar to the method of Figs. 244 and 245 except that instead of using one pin or post for one chip, a smaller pin or group of posts is used to join each chip. Or post-sequence method. As a result, according to the method, each pin or post in a group can be used to identify the non-planarity or height difference of one chip. In addition, in one embodiment, when at least some of the pins are positioned outside the perimeter of the chip, the pin is extended below the upper surface of the chip, causing the pin to perform lateral movement. On the other hand, the method is the same as a pin / post per chip fixing a surface 24606 of a spontaneous group of pins / posts in contact with each chip so as to be able to apply force through a frame, group or pin. Also, the pins / posts in the group may have circular or non-circular intersections around each surface. In addition, as will be seen below, by selecting the appropriate shape of the pin, the pin / post within a group can be formed or removed to achieve the desired advantages. It should be noted that each pin / post or group (in the case of multiple pins / posts per chip) needs to be large enough so that the pressure transmitted through them does not break the chip and break the corners or corners of the chip during processing .

In both cases, with the frame holding the posts or pins, once fixed, the posts or pins can be moved meaningfully only in the vertical direction, so that the structure can be moved only vertically according to the structure of the chips attached to the wafer Can be applied.

Preferably, as described, the force required for the "tack" step is less than 1 g per contact when using the tack and fuse method, and less than 0.001 g per contact typically in the fusing process. As a result, the pin or post can be fixed without difficulty by means of clamping or locking, which is a matter of design choice and is not critical to understanding tooling and its use.

Advantageously, in one embodiment, any one of the tooling can be further improved by allowing vacuum to be applied to the chip. In the case of pin-to-chip tooling per chip, this can be achieved by providing passages 24412 and 24414 through posts and openings on the post surface 24406. Alternatively, using the pin / post group method, the pin / post itself can provide a passage through the vacuum. Alternatively, a suitable shape and spacing of the pins / posts may be determined to form (within the chip boundary) the passageway between adjacent fins so that a vacuum can pass through the passages therebetween, or may be removed (near the chip periphery) .

According to one tooling embodiment using this variant, the tooling itself can be used in a pick-and-place process, or during a process such as tack or melt, Vacuum can be applied to the chip to further hinder movement.

Alternatively, materials may be applied to the surfaces 24406 and 24606 of the pins or posts to initially bond the pins or posts to the chip, and such materials may be selected to "detach" . For example, a material that is liquefied, melted, melted, or vaporized at about the tack or melting temperature may be used on the surface, but if the chip is left undisturbed and the chip or chips remain free of residue, May be removed through a harmless process, or ignored without adverse effects.

The post / pin solution imparts only vertical motion, and embodiments of the method do not actually hold the chip in place, in some cases, force is uniformly applied to each chip, and the chip is subjected to a process such as tacking or melting It can not be guaranteed that it is not inclined. Thus, in some cases, movement of the chip or non-uniform melting between chips or chips having different heights may occur.

In this case, as shown in Figs. 248 and 249, the stiffness, which adjusts or adjusts the height of various parts to prevent localization pressure that causes scratching, chipping or chip damage while maintaining pressure on the chip A tooling method using a sponge compliant compliant or deformable material 24802 formed between the plate 24804 and the daughter chip 24906 can be used. This method utilizes sponges or deformations of a thickness (generally from 0.01 &quot; to 0.125 &quot;) suitable for a particular application. Non-limiting examples of such materials include high temperature polymers such as Kalrez ^® 7075, Kapton ^® or Teflon ^® (all manufactured by DuPont), high temperature silicone rubber, thermal pad (manufacturer: Bergquist Company of Chanhassen, Ceramic fiber reinforced alumina composites such as Zircar RS-100 (manufacturer: Zircar Refractory Composites, Inc., NY, NY 10921), catalog numbers 390-2xM, 390-4xM and 390-8xM (x: width from McMaster-Carr Supply Company (Manufactured by McMaster-Carr, part no. 87575K89), glass fiber paper (manufacturer: McMaster-Carr, part number: 9323K21 ), Or other materials.

 In addition, depending on the material used between the plate and the chip, it may be a material that is reused for two or more times of pressure application and bonding, or used only in a single use.

 As in the pin / post variant shown in Figure 249, the plate moves down to the chip under pressure, so that the deformable material follows the chip and encircles the periphery of the chip so that it is constrained to lateral movement. Thereafter, the bonding process is performed using pin / post system tooling.

Alternatively, this arrangement can advantageously be used according to pin / post system tooling, if the particular application is less desirable to apply force to the pin / post through the frame. In this arrangement, the pin-type tooling is applied as described above. However, once the pins / posts are all of the same height and are in contact with the chip, the pin / post ends exhibit the same height difference as the chip. However, by using plates and material arrangements at the ends of the pins / posts in the opposite direction of the chip, a height difference can be used and suitable forces can be applied easily and uniformly. In addition, through this method, it seems that sufficient material can be physically removed from the chip, which does not require thermal resistance, as a material that must be in direct contact with the chip.

Other ways to keep the chip bonded to the device associated therewith are similar to the plate modification of Figures 248 and 249 shown in Figures 250 through 254, and the relatively thin but rigid material 25002 is preferably in liquid or gel form And a body 25000 formed by coating with a curable material 25004 that can be cured.

The body 25000 is disposed on the chip 24906 array so as to be adhered to the curable material 25004 while maintaining the horizontal state (Fig. 251). (Or, as long as the curable material remains thick, the rigid portion of the fused body is a flexible compliant material, and when cured, the entire body (i.e., the body and the curable material) Maintain sufficient thickness to act together.

Once cured, the chip can be moved to the attached element, so that, if necessary, the body can measure mass in a separate, movable weight during the attachment process (Figure 252). In addition, since the curable material is adhered to and cured on each chip, the attached chips can not move with respect to each other in any direction (side, vertical, or tilt (pitch and yaw angle) If the entire body remains the same height in the attachment process, the chip will maintain a similar orientation.

Optionally, an underfill 25302 material can be introduced between the body and the element to which the chip is attached (Figure 253). Underfill 25302 can be used to fill the gap between the chip and the device to which the chip is attached. In addition, since the area between the chip and the body is sealed, the underfill 25302 can be introduced in a controllable manner (i.e., without flowing into undesirable locations)

Once combined, the weights can be removed (if used), underfill applied (if used), and any suitable process that does not damage the chip (e.g. chemical processes such as lapping or polishing of the wafer) , Or a chemical mechanical process (CMP)) can be used to remove the entire (or wide) body (Figure 254). By removing the body, the entire chip assembly can be used to attach a new layer of the chip as is the current bottom element.

Similarly, the "body" method may be used in conjunction with pin / post system tooling which identifies the pin / post height difference and forces the frame through a method other than direct application. In this case, the pin / post is brought into contact with the chip so that the body opposite to the chip is brought into contact with the distal end of the pin / post and hardened. Thereafter, a force is applied as described above in the preferred process. Once the chip is attached, the pin / post-frame-whole body combination can be easily removed from the chip, as is the normal pin / post method. Thereafter, the entire body can be separated using pin / post-frame tooling through a convenient process of softening or removing the hardenable material, or simply cutting or shearing the pin at points outside the hardenable material.

 Another advantage of this combination method is that if the assembly-line method of combining multiple chips into one or more respective sub-elements, as described above in connection with a particular variant, uses a portion of the pick-and-place method, Repeatability is possible.

Finally, in connection with all of the above tooling, as well as variations, permutations, or combinations thereof, it may be desirable to use a gas, formic acid or flux of forming gas, such as forming gas, And the like.

In either case, it should be noted that the pin / post method preferably utilizes a flexible or spongy material (i.e., by applying an excessively high side pressure to the chip itself, it can be tilted, moved during the fusing process, And may require very (commercially feasible) stringent immunity with respect to process conditions.

 In summary, while the invention has been described in the context of certain types of chips, including optical chips (i.e., one or more lasers, one or more light detectors, or a combination thereof), the methods described herein may be used in conjunction with optical components, Can be used equally well to form "through-chip" electron junctions in a type of doped semiconductor chip that includes transistors or electronic circuit components that replace it.

Likewise, certain materials have been found suitable for use as "post and penetration" contact materials, but an important characteristic is that the diffusion between the two occurs, , These materials do not mean only the above-mentioned usable materials.

The particular material pair is determined to some extent by factors such as availability, cost, compatibility with other components used or manufacturing related processes not described herein, so that more than a few potentially infinite material pairs Itemization is not helpful. Likewise, in addition to optical epoxies, there are many optically transparent materials. However, the selection criteria for the particular substance to be used for a particular use are influenced or influenced by this issue and other factors that are not appropriate. Thus, it should be understood that optical transmissive media (or media) that are inserted into the voids required for a particular application to transmit the laser light are considered to be preferably usable materials, even if not all of these possible alternatives are specifically listed.

It is, therefore, to be understood that the disclosure (including the figures) has been presented for illustrative purposes only in many embodiments. For the convenience of the reader, the present description is directed to illustrative examples of all possible embodiments and teaching the principles of the invention. The specification does not list, but is not limited to, all possible variations. It is not intended to be exhaustive of the scope of the other embodiments in that other embodiments do not present certain parts of the invention and that other embodiments which are not mentioned are also available as part of the present invention. Those skilled in the art of the present invention will appreciate that many embodiments that are not mentioned are incorporated into the same principles as the present invention and that other embodiments are equivalent thereto.

Claims (59)

In a method for physically electrically connecting two chips, Aligning an electrically conductive first contact of a first chip with a corresponding electrically conductive second contact on a second chip, wherein the first contact comprises a first material and the second contact is more than the first material The second material being malleable; Contacting an aligned first contact of the first chip to a second contact on the second chip; Applying a first pressure to the first and second chips sufficient to penetrate the second material and thereby form an electrically conductive first connection between the first chip and the second chip, Raising the temperature of the first and second contacts to an elevated temperature below the liquefaction temperature of the material; And Cooling the first and second contacts to an ambient temperature after formation of the electrically conductive first connection, Wherein the two chips are electrically connected to each other. 2. The method of claim 1, further comprising profiling the contact pad surface of the first contact prior to the aligning step. 3. The method of claim 2, wherein the profiling comprises forming one or more valleys on the outer surface of the contact pad surface of the first contact. Way. 3. The method of claim 2, wherein the profiling comprises forming at least one concentric closed-ring valley on the outer surface of the contact pad surface of the first contact A method for physically electrically connecting two chips. 3. The method of claim 2, wherein the profiling includes removing at least two distinct elevated bumps by removing a portion of the contact pad surface of the first contact. How to make electrical connection. 2. The method of claim 1, further comprising etching the contact pad surface of the first contact prior to the aligning step. The method of claim 1, further comprising the step of selecting one of the metals or alloys as the first material, wherein the metal or alloy has a melting temperature that is at least 50 캜 higher than the melting temperature of the second material. A method of physically and electrically connecting two chips. 8. The method of claim 7, wherein selecting one of the metal or alloy as the first material comprises: A third material comprising at least one of Al, Au, Co, Cr, Cu, Ni, Pd, Pt, Ta, or W; A fourth material comprising an alloy of Al, Au, Co, Cr, Cu, Ni, Pd, Pt, Ta, or W; And TaN, TaW, a combination of Ti and Pd, a combination of Ti and Pd and Pt, a combination of Ti and Pd and Pt and Au, a combination of Ti and Pf and Au, a combination of Ti and Pt, a combination of Ti and Pt And Au, or a fifth material comprising at least one of TiW The method comprising: selecting one of the plurality of chips to be physically connected. The method of claim 1, further comprising the step of selecting one of a metal or an alloy as said second material, wherein said metal or alloy has a melting temperature that is at least 50 캜 lower than the melting temperature of said first material. A method of physically and electrically connecting two chips. The method of claim 9, wherein selecting one of the metal or alloy as the second material comprises: A sixth material comprising at least one of Sn, In, Pb, Bi, Al, Zn, or Mg; A seventh material comprising at least one of Sn, In, Pb, Bi, Al, Zn or Mg; And An eighth material comprising a metal or alloy having a melting point less than &lt; RTI ID = 0.0 &gt; 1000 C & The method comprising: selecting one of the plurality of chips to be physically connected. The method according to claim 1, wherein after said cooling step, Raising the temperature of the first and second contacts to a separation temperature below the liquefaction temperature of the second material; And Separating the first chip from the second chip to separate the first contact from the second contact Further comprising the step of electrically connecting the two chips. 12. The method of claim 11, Further comprising attaching the first contact to an additional contact of the third chip. &Lt; Desc / Clms Page number 21 &gt; 12. The method of claim 11, And attaching the second contact to an additional contact of the third chip. &Lt; Desc / Clms Page number 20 &gt; The method according to claim 1, Contacting an additional contact of the first or second chip with a third contact on the third chip; The first contact and the third contact being stiffer than the first contact and the third contact so as to penetrate the further contact of the further contact and the third contact, thereby disconnecting the electrically conductive first connection between the first chip and the second chip The first contact and the third contact, while applying sufficient pressure to form an electrically conductive second connection between the third chip and one of the first or second chips, Raising the temperature of the further contact and the third contact to a temperature; And Cooling the contacts of the first chip, the second chip, and the third chip to an ambient temperature after formation of the electrically conductive second connection portion between the third chip and one of the first or second chips Further comprising the step of electrically connecting the two chips. 2. The method of claim 1, wherein raising the temperature occurs simultaneously with at least one of the aligning step and the contacting step. In the chip, A first chip comprising a first electrical contact comprising at least two layers, Wherein one of said at least two layers comprises one of a first metal or a first alloy and another of said at least two layers comprises a second metal or a second alloy different from said first alloy, Wherein the first electrical contact has a proximal end and a distal end for the first chip and the distal end has a protruding shape in a plane parallel to the first chip, Wherein the first electrical contact and the second electrical contact facilitate penetration of the second chip into the second electrical contact and when the first and second electrical contacts are connected at a temperature below the melting point of the second electrical contact, At least a portion of the second electrical contact is more flexible than a portion of the first electrical contact, and the at least a portion of the second electrical contact is configured to facilitate mechanical and electrical connection between the second electrical contact for And is configured to deform when the first and second electrical contacts are connected at a temperature below the melting point. 17. The method of claim 16, wherein the first electrical contact comprises a plurality of discrete elements disposed on a base portion, each of the plurality of discrete elements having a cross-sectional area measured parallel to the chip, Wherein each cross-sectional area is smaller than a cross-sectional area of the base portion. 18. The chip of claim 17, wherein the plurality of discrete elements comprises at least two individual posts. 19. The device of claim 17, wherein the plurality of discrete elements comprises at least two elements stacked together, wherein one of the at least two stacked elements has a shape Chip having the same but different length perimeter. 21. The chip of claim 19 wherein a first element of the at least two stacked elements is disposed on a surface of a second element of the at least two stacked elements. 21. The method of claim 20, wherein the first of the at least two stacked elements and the second of the at least two stacked elements have the same distance between corresponding points on the periphery of the first and second stacked elements Of the chip. 17. The chip of claim 16, wherein the distal portion comprises a pattern configured to enable penetration of the first electrical contact to the second electrical contact, the pattern comprising at least two bumps. 17. The chip of claim 16, wherein the distal portion comprises a pattern configured to enable penetration of the first electrical contact to the second electrical contact, the pattern comprising at least one pyramid. 17. The chip of claim 16, wherein the distal portion comprises a pattern configured to enable penetration of the first electrical contact to the second electrical contact, the pattern comprising a truncated pyramid. 17. The chip of claim 16, wherein the distal portion includes a pattern configured to enable penetration of the first electrical contact to the second electrical contact, the pattern comprising a shape having a point at the distal portion. 17. The method of claim 16, wherein the distal portion comprises a pattern configured to enable penetration of the first electrical contact to the second electrical contact, the pattern comprising a first geometric shape on the second geometric shape chip. 27. The chip of claim 26, wherein the first geometric shape is different from the second geometric shape. 27. The chip of claim 26, wherein the first geometry and the second geometry are the same. 27. The chip of claim 26 wherein the first geometric shape has a first width at its widest point and the second geometric shape has a widest point that is narrower than the first width. 27. The method of claim 26, wherein the second geometric shape extends beyond a peripheral boundary of an integrated circuit (IC) pad located beneath the second geometric shape, Chip that is. In a semiconductor chip, Integrated circuit (IC) pads; And And a device electrically coupled to the IC pad, The IC pad is also electrically connected to a first electrical contact, A first surface configured to enable penetration of the first electrical contact to the second electrical contact at a temperature below the melting point of the second electrical contact on another semiconductor chip, Wherein the first surface is more ductile than the electrical contact and the first surface is angled outwardly from a tip of the first electrical contact toward the IC pad; And Wherein the second surface is closer to the IC pad than the first surface and the second surface is closer to the tip of the second electrical contact than the second surface Wherein the first surface is inclined inward toward the center of the first electrical contact from the end And a semiconductor chip. 32. The semiconductor chip of claim 31, wherein the cross-sectional profile of the first electrical contact comprises one of a pyramid or truncated pyramid. 32. The semiconductor chip of claim 31, wherein the first electrical contact comprises a first geometric shape having the first surface over a second geometric shape having the second surface. 34. The method of claim 33, The first geometric shape having a tip portion and a first extending portion with respect to the tip portion; The second geometric shape having a second extending portion for the tip portion; Wherein the first and second extending portions are adjacent to each other. 32. The semiconductor chip of claim 31, wherein the cross-sectional profile of the first electrical contact comprises an inverted trapezoid. 36. The semiconductor chip of claim 35, further comprising a triangular phase on the inverted trapezoid. 37. The semiconductor chip of claim 36, wherein the second surface defines an undercut in a portion of the first electrical contact closest to the semiconductor chip. 32. The semiconductor chip of claim 31, wherein said second surface defines an undercut proximate said base of said first electrical contact. 32. The semiconductor chip of claim 31, further comprising a wing positioned proximate to a base of the first electrical contact. In an electrical contact of a semiconductor chip, Means for enabling penetration of the electrical contact from a temperature below the melting point of another contact that is more ductile than the electrical contact to the other contact, wherein the electrical contact is inclined outwardly from the tip of the means for enabling penetration to the semiconductor chip Said first surface including a first surface; And Means for securing a strong physical connection between said another electrical contact and said electrical contact when said electrical contact is connected to said other electrical contact, wherein said means for securing said strong physical connection is closer to said semiconductor chip than said first surface Wherein the second surface is inclined inward toward the center of the electrical contact from an end of the second surface closest to the tip of the means for enabling the penetration, Means of securing &Lt; / RTI &gt; 41. The electrical contact of claim 40, wherein the means for securing the strong physical connection comprises an undercut. delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete

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