KR101168786B1 - Chip connector - Google Patents

Abstract

A method of electrically connecting a first contact on a first wafer to a second contact of a second wafer, the first contact comprising a rigid material and the second contact comprising a material that is flexible with respect to the rigid material Allowing the material to penetrate the soft material, wherein the rigid and soft material are electrically conductive; contacting the rigid material with the soft material; Applying a force to one of the first contact and the second contact such that the rigid material penetrates the soft material; Heating the rigid and ductile material to make the ductile material soft; And constraining the soft material into a predetermined area.

Contacts, flexible materials, rigid materials, wafers

Description

Chip Connector {CHIP CONNECTOR}

TECHNICAL FIELD The present invention relates to semiconductors, and in particular, to electrical connections for devices.

It is difficult to make an electrical contact (by forming an electrical conductor via) that extends all of the course through the electronic chip. a) the vias are very shallow, i.e. at a depth significantly less than 100 microns, b) the vias are large, c) the vias are separated by a large distance, i.e., several times the width of the vias Otherwise, it is almost impossible to have not only large quantities but also precision or controlled repeatability. This difficulty is exacerbated when the via is close enough to generate signal crosstalk, or when the chip passing through the via has charge. The reason is that the conductors in the vias cannot be allowed to operate as short circuits or carry a charge that is different from the charge of the relevant part of the chip. In addition, existing conventional processes are not suitable for use in forming integrated circuit (IC) chips (ie, including active semiconductor devices). These processes can damage the chip, increasing costs and ultimately reducing yield. In addition to the problems described above, capacity and resistance problems arise when the material passing through the via has a charge or when the frequency of the signal to be transmitted through the via is very high, for example, above 0.3 GHz.

Indeed, the use of non-scaleable large packaging, not scaling semiconductors with similar assembly costs, chip cost proportional to area, and high performance processes are very expensive, as well as only part of the chip area. This actually requires a high performance process, the current process is limited in voltage and other technologies, the chip designer is limited to one process and one material for the design, the high power pad driver (via the package) What is needed for the chip-to-chip connection, that even small changes or even minor design errors require the manufacture of one or more complete new masks for the new chip, making a complete new chip requires millions of dollars for the mask cost alone, Difficult or complex to test chips, and complete Numerous problems remain in semiconductor technology, including the difficulty of testing a combination of chips before packaging.

Thus, there is a need for a technique that can address one or more of the above-described problems.

A process for facilitating the formation of chip-to-chip electrical connections with vias through the wafer, pre-formed third chips, and doped semiconductor substrates has been developed. The form described here assists the approach and represents an improvement in the general field of coupling chips together.

One form is a method of electrically connecting a first contact on a first wafer to a second contact of a second wafer, the first contact comprising a rigid material, wherein the second contact is a flexible material relative to the rigid material. Comprising, upon bonding, allowing the rigid material to penetrate the soft material, wherein the rigid and soft material are electrically conductive; contacting the rigid material with the soft material; Applying a force to one of the first and second contacts such that the rigid material penetrates the flexible material; Heating the rigid and ductile material to soften the ductile material; And constraining the soft material into a predetermined area.

Another embodiment includes forming a well on the second wafer in a manner that binds and constrains the malleable material.

Another form further includes adding the soft material onto the IC pad of the second wafer, wherein the IC pad is at least one of a cover glass of a second wafer disposed near the IC pad or a dielectric on the second wafer. Recessed with respect to the soft material partially overlying the IC pad and partially over the cover glass or dielectric or both, and the outer surface of the soft material overlying the IC pad is It is at a different height than the other portions of the soft material overlying the dielectric or both.

Yet another aspect is a connection formed between complementary contacts on two chips, comprising: a first electrical contact on a first chip of the two chips; A second electrical contact on a second chip of the two chips; Bonding metal to physically electrically connect the first and second electrical contacts; And a connection comprising a material bounding the periphery of the bonding metal to prevent the bonding metal from swelling or leaking out in the lateral direction from the contacts.

The advantages and features described herein are some of the many advantages and features available from exemplary embodiments and are described to aid in the understanding of the present invention. It is to be understood that they are not to be regarded as limiting the invention as described by the claims or as equivalents to the claims. For example, some of these advantages are incompatible with each other in that they cannot exist simultaneously in a single embodiment. Likewise, some advantages are applicable to one aspect of the present invention but not to other aspects. Thus, summaries of features and advantages should not be considered in the direction of determining equivalents. Further advantages and features of the present invention will become apparent from the following detailed description, drawings, and claims.

1 is a simplified side view of a portion of a chip that includes a number of active electronic devices.

FIG. 2 is a plan view of the top surface of the specific area of FIG. 1. FIG.

3 is a simplified cross-sectional view of a portion of FIG. 1.

4 is a plan view of the top surface of the particular region of FIG. 1 after forming the trench shown in side view in FIG.

5 is a simplified cross-sectional view of a portion of FIG. 1 as a result of subsequent processing.

6 is a plan view of the top surface of the particular region of FIG. 1 after filling the trench with the electrically insulating material shown in side view in FIG.

7 is a simplified cross-sectional view of a portion of FIG. 1 as a result of continued processing.

8 is a plan view of the top surface of the specific region 124 of FIG. 1 after creating the via trench.

9 is a simplified cross-sectional view of a portion of FIG. 1 as a result of continued processing.

10 is a plan view of the top surface of the particular region of FIG. 1 after metallization of the via trench;

11 is a simplified cross-sectional view of the portion of FIG. 1 as a result of any subsequent processing.

12 is a plan view of the top of a particular region of FIG. 1 after optionally introducing a bonding material into the remaining voids.

13 is a simplified cross-sectional view of the portion of FIG. 1 as a result of any other processing.

14 is a plan view of the top surface of the particular area of FIG. 1 after optionally adding a finishing material with remaining voids. FIG.

15 is a simplified cross-sectional view of a portion of FIG. 1 as a result of continued processing.

16 is a simplified cross-sectional view of a portion of FIG. 1 after thinning the substrate to remove the bottom metal.

17 is a simplified cross-sectional view of the portion of FIG. 5 as a result of processing of another variant.

FIG. 18 is a top view of the section taken below the particular region of FIG. 1 after creation of the via trench; FIG.

19 is a simplified cross-sectional view of the portion of FIG. 5 as a result of further processing in the manner described in connection with FIG.

20 is a simplified cross-sectional view of the portion of FIG. 5 as a result of another optional processing in the manner described in connection with FIG.

21 is a simplified cross-sectional view of the portion of FIG. 5 as a result of another optional processing in the manner described in connection with FIG.

22 is a simplified cross-sectional view of the portion of FIG. 5 as a result of thinning the substrate in a manner described in connection with FIG. 15 in another variation of FIG.

FIG. 23 is a simplified cross-sectional view of the portion of FIG. 5 as a result of thinning the substrate to remove the bottom metal in the manner described in connection with FIG. 16 for further modification of FIG.

24 shows in simplified form the dual conductor deformation after metallization of the sidewalls;

FIG. 25 illustrates in simplified form the dual conductor variant after filling the trench with an electrically insulating material 500. FIG.

FIG. 26 illustrates in simplified form a via trench created by removing all islands of semiconductor material;

FIG. 27 illustrates in simplified form a via trench created by removing only an inner island of semiconductor material;

28 illustrates, in simplified form, an example of a dual conductor variant.

29 shows, in simplified form, another example of a dual conductor variant;

30A and 30B illustrate the use of any additional thermally produced dielectric or insulator, respectively, in the approaches of FIGS. 28 and 29.

31 shows, in simplified form, an example of a three-conductor variant.

32 is a simplified cross-sectional view of a portion of another chip implementation similar to the implementation of FIGS. 9-16 except that voids remaining after metallization are not filled.

FIG. 33 is a simplified cross-sectional view of a portion of another chip implementation similar to FIG. 23 except that voids remaining after metallization are not filled.

34 and 35 are cross-sectional views of each of the chips of FIGS. 32 and 33 after hybridization to each other.

FIG. 36 illustrates the embodiment of FIG. 34 after selective coating of an insulator or conformal coating.

FIG. 37 shows a representative example of a cross section of an annular trench; FIG.

FIG. 38 shows, in simplified form, a general schematic form of a process of preparing a wafer for a stack.

39-41 illustrate portions of example chips that are processed to create through-chip connections using other variations of the processes described herein that are later stacked together to form a chip unit.

42 shows, in simplified form, a process for rear-front deformation.

Figure 43 shows in simplified form the process for capacitive coupling deformation;

FIG. 44 illustrates in simplified form the process for pre-connection modifications.

45 and 46 illustrate, in simplified form, exemplary tack and fuse parameters.

FIG. 47 illustrates a simplified example including a “minimum” contact. FIG.

FIG. 48 illustrates a simplified example involving extended contacts. FIG.

FIG. 49 illustrates a portion of a stack of semiconductor chips with through-chip connections described herein. FIG.

FIG. 50 illustrates a portion of a simplified stack of the chip shown in FIG. 49 stacked using a post and through connection approach.

51 shows in simplified form the voids in the metallization film by means of preformed posts.

FIG. 52 shows, in simplified form, the chip of FIG. 51 after being coupled to an electronic chip;

53-71 illustrate simplified variations of the basic contact formation and engagement approach.

72-87 illustrate another simplified variation of the basic contact formation and engagement approach.

88-91 illustrate, in simplified parallel form, a first portion of two further variant approaches that will later form rigid posts on the backside of the daughter wafer.

92 is a cross-sectional photograph of an exemplary beveled via.

93 is a photograph of an exemplary viae having a depth of 100 microns and a diameter of 20 microns.

94 is a cross-sectional photograph of a chip on which sharp vias are formed.

95-102 show, in simplified parallel form, a second portion of two further alternatives of FIGS. 88-91;

103-125 illustrate, in simplified parallel form, a modified process of preparing a wafer for bonding to other elements.

126-139 illustrate, in simplified form, another modified process for preparing a wafer for bonding to other elements.

140 is a simplified illustration of daughter wafer contacts and mother wafer contacts immediately before a tack state;

141 illustrates in simplified form the contact of FIG. 140 after the fuse process is complete;

142 illustrates a profile of a flexible contact.

143A-143P illustrate representative examples of some of the myriad of possible mother contact profiles.

144 is a photograph showing another example of the profile of a soft contact.

145 is a photograph showing a profile of a rigid contact designed to penetrate the flexible contact of FIG. 144.

146 illustrates in simplified form a profile of another contact example;

147 through 152 illustrate a modified process for implementing the well attachment concept.

153 through 156 show, in simplified form, the types of reverse well modifications.

157A-157B are longitudinal cross-sectional photographs of sets of 25 micron diameter vials extending to 155 microns deep and sets of 15 micron diameter vias extending to 135 microns deep, respectively.

158 is a photograph of a via different from FIGS. 157A and 157B not filling all of the paths to the bottom.

159 through 167 show yet another variation of the class II-type rigid well attachment approach.

168-170 illustrate yet another variation of the well attachment approach where chips are attached to each other by separate remote contacts.

171A and 171B are schematic views of different remote contact variants.

172 illustrates a cross section of an exemplary coaxial contact.

173 through 175 illustrate examples of use of coaxial contacts.

176 through 179 show two examples of sealing using the contacts described herein.

FIG. 180 is a chart summarizing different approaches to forming other strains using the rigid / soft contact paradigm. FIG.

181 and 182 are charts summarizing different approaches to forming via strains.

183-195 detail the process flow for a particular example involving metal deposition on a daughter wafer.

196-205 illustrate in detail the process flow for a particular example involving metal plating on a daughter wafer.

206 illustrates in simplified form the mother wafer electroless plating variant;

207 shows in simplified form a thin dielectric strain of a mother wafer;

208 shows in simplified form the thick dielectric strain of a mother wafer.

FIG. 209 illustrates exemplary general dimensions for a mother wafer contact having 14 micron wide contact pads spaced at a pitch of 50 microns prior to barrier deposition.

FIG. 210 illustrates the contact of FIG. 209 after barrier and cap deposition.

FIG. 211 shows the general dimensions of a mother wafer contact with 8 micro wide contact pads spaced at 25 micron pitch.

FIG. 212 illustrates exemplary typical dimensions of a daughter wafer contact having 14 micron wide contact pads spaced at 50 micron pitch produced by deposition. FIG.

FIG. 213 illustrates exemplary typical dimensions of daughter wafer contacts having 8 micron wide contact pads spaced at 25 micron pitch produced by deposition.

FIG. 214 illustrates exemplary general dimensions of plated strained mother wafer contacts with 14 micron contact pads spaced at 50 micron pitch before self-aligned seed etching is performed.

FIG. 215 illustrates the contact of FIG. 214 after self-aligned seed etching is performed.

216 illustrates using an internal via as part of a heating pipe arrangement.

217 illustrates in simplified parallel form a variant of separation and connection;

FIG. 218 illustrates, in simplified parallel form, yet another variant of separation and connection;

219 shows, in simplified form, a representative example of a conventional microprocessor chip and its respective components;

FIG. 220 illustrates, in simplified form, how other microprocessors may be constructed from the elements of the microprocessor of FIG. 219 to provide less space and substantially reduced distances between elements.

FIG. 221 shows a direct comparison between the space of the chip of FIG. 219 and the space of the chip of FIG. 220;

222 illustrates a functional packaging variant.

FIG. 223 shows a specific example of a variant of the packaging of FIG. 222;

224 through 231 show a brief overview of routingless processing variations.

232 through 235 illustrate, in simplified form, another routingless processing variant.

236 shows in simplified form the use of an optical connection rather than a wire between two chips;

Figure 237 illustrates in simplified form the use of a variant of the heating pipe configuration that allows light to pass from the laser-bearing chip to the photodetector-bearing chip even when two other chips are interposed between the laser-bearing chip and the photodetector-bearing chip. Indicative drawing.

238 illustrates in simplified form the tack and fuse process approach.

239 illustrates in simplified form the functional layer of a daughter contact;

240 illustrates in simplified form the functional layer of a mother contact;

FIG. 241 is a view showing, in a simplified form, a material constitution example of a functional layer of a daughter contact; FIG.

242 shows, in simplified form, an example of the material construction of the functional layer of a mother contact;

243A, 243B and 243C are photographs of combined mother and daughter contacts.

244 and 245 show, in simplified form, single pin pores per chip;

248 and 249 illustrate, in simplified form, different pore approaches.

250-254 illustrate, in simplified form, another pore approach.

Hereinafter, with reference to the accompanying drawings will be described in detail the detailed operation and structure of the present invention. It should be noted that reference numerals and like elements among the drawings are denoted by the same reference numerals and symbols as much as possible even though they are shown in different drawings.

Firstly, the term "wafer" to be used in the present invention hereinafter refers to "chip", "die", and "wafer" unless the specific mention clearly and exclusively refers to only the entire wafer (divided into multiple chips). It should be noted that all terms such as "may be included. For example, an entire wafer may be an 8-inch or 12-inch wafer, chip or die "chip-to-wafer", "wafer-to-wafer", or "wafer scale". (wafer scale) " processing into multiple chips. The term may be technically replaced by a chip or die. In addition, the substantive reference to "wafer or chip" or "wafer or die" to be used hereinafter is intentional even if the above mentioned content is not satisfied. Should be considered as term duplication.

In general, certain embodiments to be described below enable the formation of a connection between two or more wafers, each wafer being a fully-formed electron in a simple controlled fashion. (electronic) device, active optical device, electro-optical device, and by this control scheme, the via is deepened, high repeatability, controlled capacitance and resistance, and the via and wafer Alternatively, electrical isolation between the substrates (through the vias) is possible.

According to the embodiment of the present invention, an electrically conductive via may be formed. Although the chip's depth-to-width ratio is generally used in a ratio of 5: 1 to 10: 1, the vias of the present invention are less than about 15 microns wide and about 50 microns deep, The ratio of the width to the depth of the chip is set at the ratio of 30: 1 and 3: 1. In addition, the present invention has the advantage that the chip portion through which the via penetrates becomes electrically active.

In particular, the present invention provides an electrical access through the doped semiconductor portion of the wafer using a passage. Sidewalls at the location of the passageway insulate the doped semiconductor from the electrical conductor, the electrical conductor propagating through the passageway.

In addition, the present invention provides a narrow passageway (i.e., about 15 microns or less) that allows tight control of the thickness of the insulating material and the electrical conductors in order to maintain constant and acceptable capacitance and resistance. ) In providing.

In addition, the present invention is suitable for forming a contact having a circular diameter of the pad (0.1 micron to 15 microns), the contact has an upper end and a lower end, the upper end has no limit (limit) and the size is simple In the present invention, the general degree of integration may be further improved, and the lower end may be implemented with photolithographic techniques currently available. In other words, the advancement in the photolithography technique of the present invention makes it possible to further reduce the current limit as a smaller definition.

In addition, solder contacts are hundreds of thousands of microns in length, or wirebond contacts are thousands of microns in length and often require a pad driver for impedance-to-chip impedance driving. The present invention utilizes very short contacts (less than 10 microns), which further lowers the parasitic electrical effect between chips.

The contacts in this study are spaced from each other by three or less times the contact size, and have a width of mellalleable material prior to the degree of integration with complementary contacts. The complementary contacts, for example, have an initial contact height of 8 microns, and the spacing between the contacts reaches up to about 25 microns.

The present invention allows for stacking on separation spacings of about 20 microns or less. Although about 1 micron spacing is implemented in the present invention, spacing of less than 10 microns is common. In general, the minimum spacing is determined by the topology of the nearest surface between the two wafers that are connected to each other, the two wafers contact each other at their highest height and the distance between the pads represents the maximum height spacing.

The present invention can form a contact on a pitch of 50 microns or less. In the present invention, a pitch of 7 microns is realized, but a pitch of 25 microns or less is usually used. Limited to the capabilities of currently available photolithography techniques. Here, the pitch can be made smaller.

Some variants have the following characteristics:

That is, the potential for millions of contacts per cm ² ; Electrical, mechanical and thermal attachments occurring simultaneously; Attachments having a low force but high strength (1000 kg / cm ² ) connection; Connections with economines of scale; Accommodated non-planar wafers; Most processing on wafer scale (eg 10 micron GaAs on 8 ", 10", 12 "wafers); chip and chip-to-chip, chip and wafer, chip and wafer Wafer-to-wafer-based processes; electrically grounded processes; made in linearized devices (i.e., device-bearing chips) and used as third-party supplied chips Connecting vias; forming vias before multiple chips are connected to each other; capability to test or reactivate chip combinations as needed before permanently connecting them; mixing and matching different technologies (Ie GaAs-to-InP, InP-to-Si, GaAs-to-Si, SiGe-to-SiGe-to-Si, etc., and insulating wafers made of ceramic, LCP or glass); The ability to form chip-sized packages with the benefits of expensive processors It has a complete set of circuits that enable a low-speed function that eliminates the need for one chip, but behaves like a single chip, with multiple voltages, technologies, And the ability to be designed to have materials; not taking into account the technology required for other aspects of the design; enhanced off-chip communication; facilitating increased modularity of the design at the chip level. Where the chip level allows the core design to be produced in multiple products without spending the remaining redundant non-recurring engineering costs; and enabling speed matching as a technology type The circuit no longer needs to be produced at high cost, and the technology is implemented in terms of speed.

Overall, the present invention aims to improve the ability to form chip-to-chip connections using through-wafer electrical contacts. The through-wafer electrical contact can be used as a doped substrate, but will not short out the substrate, resulting in a charge opposite to the substrate. In addition, this "through-wafer" study is available with wafers composed of semiconductors, insulators such as ceramics, and conductive or nonconductive materials.

In addition, using current devices for etching semiconductor materials (with a 30 to 1 aspect ratio), vias and narrow vias of narrow cross section (i.e. 15 microns wide, in some cases less) A process is done for vias whose depth extends from 50 microns to 500 microns. In addition, the process enables close control of capacitance and resistance. For example, vias formed through the process convey high speed electrical signals (ie, frequencies above 0.3 GHz) or optical signals in some implementations.

In addition, embodiments of the present invention allow the formation of concentric vias, and if they are conductive, each can carry different signals and charges. Furthermore, embodiments of the invention allow for the inclusion of an inner via in a concentric via, in which the inner beer is used as a heat pipe arrangement in a cooling system. To be used as a part. Still other embodiments enable the use of a stacking method, in which a plurality of chips are stacked and electrically connected to each other based on the chip and the chip, the chip and the wafer, or the wafer and the wafer.

Advantageously, virtually all the stacking processes and variants described below require only a new stacked piece to be aligned at the bottom of the piece. This is in stark contrast to the prior art, where all the pieces in the stack must be aligned together, after which the conductive material is inserted into the stack to form a trans-stack connection.

This study ensures that all the pieces in the stack are aligned exactly with every other piece, rather than just underneath the piece in which it is typically placed. In addition, the present study allows for an even implementation using uniaxial, coaxial, and triaxial connections, which could not be achieved at all in the normal alignment method.

The various methods described above are merely presented as examples using all examples of wafers composed of semiconductor materials. Examples of the semiconductor materials are silicon (Si), silicon-germanium (SiGe), gallium-arsenic (GaAs), and the like, which are preformed (ie, include integrated circuits or components thereof, and contact Optical devices such as pads, modulators, laser detectors).

The first embodiment of the present invention involves the two-etch process. Here, there is a need for the wafer to be etched for the purpose of semiconductor material (ie doped semiconductor with or without some or all of the substrates associated therewith) in the two-etch process.

This embodiment process begins with a device-bearing-wafer of semiconductor material. At least one trench portion with the correct width allows the wafer to be etched to the desired depth, in the case of a semiconductor wafer, so that the trench extends into the wafer substrate and forms a perimeter with respect to the semiconductor material portion.

In particular, the protrusions form a closed shape so that the outer wall / inner wall of the trench need not have the same shape. The capacitance and resistance of the ultimate via connection is controllable through selection of the shape of the inner / outer protrusions of the trench and their separation distance. Trench depth is typically over 50 microns (in some cases over 500 microns). However, since the trench does not propagate through the entire substrate of the wafer, the bounded semiconductor piece does not fall out. The trench is filled with an electrically insulating material.

At least the bound portion of the semiconductor piece is etched away leaving a hole of a cross section narrower than bound by an outer trench wall, such that vias formed by etching the semiconductor via are bound by an insulating material or Bound by a perimeter ring protruding from the central semiconductor piece of depth, the remainder being the substrate. The holes are metalized to form electrical connections between the top of the wafer and the bottom of the holes. The back portion of the wafer (ie, the substrate) is thinned to expose the metallized portion at the bottom of the hole so that the hole is a substrate side contact or portion thereof (hereinafter, broadly referred to as "contact"). ).

Typically, although in some embodiments the metallization extends to only a sufficient depth when the substrate is sufficiently thinned, it will at least be metalized to the highest depth of the surface portion defining the hole. In this regard, the contact can be formed if the process for performing the metallization fails to perform metallization up to the full depth where the metallization extends to where the thinning stops. . For example, in this embodiment, if the vias are expanded to a substrate having a total length of about 600 microns, the metallization will reach a total depth of about 300 microns (ie, 300 microns less than the vias themselves), and the process Is not negatively affected until the depth at which the substrate is thinned (allowing metallization without weakening the wafer or chip to an unacceptable range).

Through the embodiments, variants, permutations and combinations described above, connection points can be brought closer to on-chip devices. By bringing the connection point closer to the on-chip device, the chip-to-chip connection in the vertical direction (i.e. through-chip stacking) is made easier, and the distance between the connection points can be reduced, Reduce the need for the use of wirebonds for chip-to-chip connections.

In addition, the present invention facilitates the formation of sub-component specialty designs, allowing them to be mixed and matched with one another during manufacturing. That is, the third dimension makes the chipset material, geometry, and product easier to use.

In addition, the present invention develops in that it allows mixing of different speeds or material technology types and reduces manufacturing costs as well as mix-matching of major or subcomponent designs. Chip-to-chip connections are formed using optical parts rather than electrical connections between chips.

The contents of the present invention become more useful through the optical use of the chip-chip connection, thereby reducing the stress of the chips connected to each other and reducing the risk of chip damage.

The above features will be described through a number of examples with reference to specific drawings, which are only for the purpose of explanation of the invention and the scope of the invention is not limited thereto and can be applied to other examples. In some cases, the overall exaggeration or distortion may be intentional to aid in the presentation and understanding of the present invention.

In addition, according to the present invention described above, specific devices are arranged on a chip independently of each other. Thus, references to a particular type of device (e.g., a laser of the first example) are arbitrary and have nothing to do with the aspects to be described below, unless the electrical contact is a part of a device that needs to be made. That is, the present invention, which will be described below, applies essentially the same in all devices and circuit elements in which contacts are formed.

1 is a simplified side view illustrating a portion 100 of a chip 102 that includes a number of solid state electronics, such as resistors, capacitors, transistors, diodes, lasers, photodetectors, or some combination thereof. The part 100 shown in FIG. 1 is for illustrative purposes only and has an upper mirror 106, an active region 108 below it, and a bottom mirror 110 disposed on the substrate 112. And a laser 104, which has a height 114 of several microns from the upper outer surface 116 of the non-device portion near the device 104 of the chip 102.

As shown, the laser 104 is a conventional vertical cavity surface emitting laser (VCSEL). For convenience of description, the top mirror 106 is electrically connected to a predetermined element on the side 118 of the substrate opposite the side 120 where the laser 104 is provided to be located near the device 104 within the specific area 124. It should be assumed that it is necessary to penetrate through the doped semiconductor material 122.

Initially, the terms "top" and "bottom" described above are customary in that a laser or photodetector is referred to as the device described above, so that "bottom" means that the laser It refers to the part closest to the substrate regardless of whether it is emitted toward the substrate 112 or from the substrate 112 (or regardless of the direction of receiving light in the case of a photodetector).

FIG. 2 is a top view of the top surface 116 of the particular region 124 of FIG. 1 before the process begins.

Hereinafter, a basic process of forming a through-chip contact will be described with reference to the information introduced in FIGS. 1 and 2.

3 shows a simplified cutaway view of the portion 100 of FIG. 1 as a result of the following processing.

First, the semiconductor material 122 is etched to a depth at which the trench 302 is partially formed in the substrate 112, preferably using an anisotropic etching process (to form a relatively straight trench sidewall 304). And penetrate through to form trench 302. The overall depth of trench 302 may be at least 100 microns and may optionally extend from 500 to 600 microns or more. The trench 320, however, must stop forming before the substrate 112 extends completely through, otherwise in many cases the implementation of the present invention is lost. The trench 302 is a ring shape that takes a closed form while forming a cross section in a plane parallel to the plane of the substrate. By using such an annular trench 302, the island 306 of the semiconductor material 122 remains and is in place by at least the intact portion 308 of the substrate 112. At this time, the "ring" described to indicate the trench 302 is shown in a circular shape, but it should be noted that this is merely to simplify the description. The terms "ring" and "ring" as used herein are not limited to any particular or certain form, and it should be understood that the outer circumference does not have to take the same form as the inner circumference. As long as the trench takes a closed form and forms an "island" therein, the term trench, as used herein, should be considered as a cyclic trench or loop. That is, the terms “ring” and “ring” refer to a closed inner and outer circumferential shape that includes a closed (or regular polygon) or other closed inner and outer circumferential shape, such as a soft shape, a rugged shape, or the like. It is described to include any combination of inner and outer shape. These terms are also described to encompass fixed and varying widths as desired or required in certain cases.

FIG. 4 is a plan view illustrating the top surface 116 of the specific region 124 of FIG. 1 after forming the trench 302 shown in the side view of FIG. 3. In FIG. 4, the annular nature of the trench 302 can be clearly seen. The trench 302 has a closed inner circumference 312, outer circumference 314 and width 310 and surrounds the island 306 to form an island 306 therein from the semiconductor material 122.

FIG. 5 is a simplified cut-away view showing part 100 of FIG. 1 as a result of subsequent processing as follows.

At least the trench 302 is coated with a dielectric or other electrically insulating material 500, and optionally, the insulating material 500 may be applied to cover a portion of the outer surface 116 to a predetermined thickness. . Optionally, if heat transfer is a concern, a good thermally insulator may be used as the electrically insulating material 500.

The effect obtained in the above manner can be seen by contrast with respect to the prior art. First, as a general problem, it is very difficult to apply the dielectric material uniformly, especially when the thickness must be uniform. Secondly, this problem is aggravated when the dielectric is to be applied to an uneven surface, and more serious when it is to be applied on vertical walls such as vias as described in the present invention. Thus, these methods have no meaningful ability to control uniformity, in that other schemes form holes and allow the dielectric to be precisely applied to the walls of the formed holes and then conductive. The lack of uniformity in these schemes can have a dramatic effect on capacitance and impedance, especially when the relevant signal frequencies are very high, for example above 0.3 GHz, and thus the performance. In contrast, according to the methods described herein, the size of the trench 302 can be precisely controlled to the precision of the trench 302 itself, so that the capacitance and the resistance can be precisely controlled. Since the inner and outer circumferential walls of the trench 302 contain a portion covered by the insulating material 500 therein, the thickness and uniformity of the covered portion are defined by the inner and outer circumferential walls of the trench 302. Is defined. Therefore, it is only necessary to make sure that the trench 302 is filled, which is a low cost process with very low precision. Unlike the prior art, there is no need for precision during the application of the dielectric.

FIG. 6 is a top view of the particular region 124 of FIG. 1 after filling the trench 302 with an electrically insulating material 500 and (optionally) partially covering a portion of the upper outer surface 116 as shown in the side view of FIG. 5. It is a top view which shows 116.

FIG. 7 is a simplified cutaway view of a portion 100 of FIG. 1 as a result of subsequent processing as follows.

When the electrical insulating material 500 is solidified (by curing or hardening treatment or other processing), the particular desired implementation of the island 306 of semiconductor material in the annular portion 704 of the insulating material 500 is realized. To a depth 502 sufficient (e.g., to a depth similar to trench 302) as necessary to achieve (i.e., the trench further extends to some distance into the substrate, but preferably the substrate 112 is And not to fully penetrate) to form via trench 702. Indeed, the depth 502 of the via trench 702 further extends to a depth sufficient to reach substantially the same distance as the trench 302 into the substrate 112 during the processing as described below in this case, if necessary. As long as it is longer or shorter than the depth of the trench 302. In addition, the innermost wall of the annulus 704 defining the boundary of the island 306 determines the shape and contour of the via trench 702 formed by the removal process that will later become a dielectric. Therefore, it is not generally affected by the etching process, and the removal of the island 306 of the semiconductor material does not require strict control in the width and depth directions thereof. Can be removed Of course, other suitable processes, such as laser ablation, laser drilling, or some combination thereof, may be used to augment the removal of the island 306 or otherwise to remove the island 306.

Subsequent to this example process, if via trench 702 is formed, sidewall 706 will be an insulating material 500 and bottom 708 will be defined by substrate 112, so that bottom of trench 702 is defined. The sidewalls 706 of the via trench 702 as well as the portion 708 will all be electrically nonconductive.

FIG. 8 is a plan view showing the top surface 116 of the specific region 124 of FIG. 1 after the via trench 702 is formed in the annular portion 704 of the electrical insulation material 500 shown in the side view of FIG. .

FIG. 9 is a simplified cutaway view of the portion 100 of FIG. 1 as a result of subsequent processing as follows.

The via trench 702 is at least the length of the via trench sidewall surface 706 using, for example, physical or chemical vapor deposition techniques for sputtering, deposition, plating, or other metal application, or any combination thereof, if desired. The metallization of the longitudinal portion (ie along its depth) makes it electrically conductive. That is, in this metallization treatment, a conductive solid, a conductive epoxy or a reflowable material (for example, a suitable temperature conductive liquid material such as solder) can be used. This metallization can be used to form a continuous electroconductive connection at least approximately from the via bottom 708 to the top 116 (in most cases to the device when the device is part of the chip where the via is formed). Generally will be used. As a representative example, FIG. 9 shows an electrical trace 902 formed by this process that extends from the contact 904 on the top mirror 106 of the laser 104 to the bottom 708 of the via trench 702. ). As shown, the entire sides of the sidewalls 706 and bottom 708 of the via trench 702 are completely covered with metal.

As described above, the width and length of the insulating ring portion can be strictly controlled, such as the thickness of the conductor formed by the metal treatment, thereby achieving a constant capacitance for the metallized surface. Insulation material 500 also electrically insulates contact 904 from the semiconductor material 122 through which it passes, thus failing to insulate the semiconductor material, which, if not insulated, may electrically short the contact to another device or conductor. May cause

FIG. 10 is a plan view showing the top surface 116 of the specific region 124 of FIG. 1 after metallization of the via trench 702 and formation of wires 902 to the device contacts 904 shown in the side view of FIG. 9. to be.

11-14 illustrate additional and optional processing that may be useful or desirable for some implementations. The manner shown in FIG. 11 or 12 is independent of the manner shown in FIG. 13 or FIG. As a result, depending on the particular implementation, the schemes shown in FIGS. 11 and 12 or the schemes shown in FIGS. 13 and 14 may each be used separately and the two schemes may be used together in their respective order.

One or both of these optional methods can achieve various effects. First, filling the void with material adds mechanical strength and increases structural strength, thereby reducing potential stress. Secondly, the use of solder, epoxy, or any other bonding material can help in the final connection of the chip to other devices, especially if the connection involves bonding the chip to another chip. Can give Third, by injecting the material into the void, it is possible to reduce the risk of unwanted material entering it. Finally, the possibility of damaging the metallized part in the via trench by the injection material is reduced or eliminated, especially when less than all sidewalls are metallized. In addition, by changing the thickness of the insulating portion and the metal, the coefficient of thermal expansion (CTE) of the wafer can be balanced to match the coefficient of thermal expansion of the wafer. For example, an oxide (with a thermal expansion coefficient of 1 ppm) may be used together with copper (with a thermal expansion coefficient of 17 ppm) to match the thermal expansion coefficient of silicon (with a thermal expansion coefficient of 2.5 ppm).

Of course, both of these matters are optional and may not be adopted while using the present invention. However, these two treatments are illustrated in conjunction with FIGS. 11 to 14 to fully understand.

11 is a simplified cutaway view of a portion 100 of FIG. 1 as a result of the following optional processing.

After the metallization is completed, if the remaining empty space 1100 is not left empty for use as described below, the remaining empty space 1100 is a predetermined material (in this case, for example, the bonding material 1102). In part or in full. Depending on the particular embodiment in which this variant is to be used, the bonding material 1102 may be conductive or non-conductive. That is, for example, it may be an electrically conductive material, such as solder, metal, or alloy, which may be applied through electroless plating or electroplating or deposited by evaporation deposition or sputtering, or an oxide such as glue or epoxy or silicon dioxide. It may also be a non-conductive bonding material such as.

12 illustrates the top surface 116 of the specific region 124 of FIG. 1 after selectively injecting the bonding material 1102 into the remaining void 1100 of the via trench 702 shown in the side view of FIG. 11. Top view.

13 is a simplified cutaway view of a portion 100 of FIG. 1 as a result of the following optional processing.

In place of or in addition to the above-described treatment, if the void space is not completely filled by the metallization treatment, if there is a void space 1100 remaining after the metallization treatment is completed, for example, a part or whole of a simple finish 1302 may be used. It can also be filled. Depending on the particular embodiment in which this variant is to be used, the finish 1302 may include an insulator, such as an insulating material 500 that was originally used to fill the trench 302, a conductive epoxy, a conductive solid, or a reflowable material. Conductors can be used or else a conformal coating can be used. In addition, when using the finishing material 1302, it is not necessary to inject the finishing material into the empty space 1100 alone. As shown in FIG. 13, when the finish 1302 is an electrically insulating material and a bonding material 1102 is used, the finishing material 1302 can be injected on top of such a bonding material 1102 after formation, and of the outer surface of the wafer. It may extend out of the void 1100 to cover and protect a portion 1304 of the wire 902 extending to a portion and / or contact 904, or may be implanted to planarize the wafer even when there is no void have. For example, finish 1302 may be planarized, an oxidized material that may be used to planarize the wafer so that the entire surface may be bonded to other elements such as wafers or individual chips.

14 selectively selects an amount of finishing material 1302 sufficient to cover and protect at least a portion 1304 of wire 902 into the void 1100 remaining on top of the bonding material 1102 as shown in the side view of FIG. After the addition, the top view 116 of the specific region 124 in FIG. 1 is a plan view.

Referring back to the above basic process, FIG. 15 is a simplified cutaway view of the portion 100 of FIG. 1 as a result of the following subsequent process.

When the metallization shown in FIGS. 9 and 10 is completed, the non-device of the substrate 112 (whether using either or both of the two options shown in FIGS. 11-14) is used. Back side 118, at least bottom metallization 1502, using, for example, chemical treatment such as etching, mechanical treatment such as polishing, chemical mechanical treatment (CMP), or some combination thereof. By thinning until) is exposed, device contacts electrically insulated from the doped semiconductor material 122 (in the case of the bottom mirror 110 of the laser 104) without having to perform a special post-treatment ( An electrical contact 1504 is formed in the backside 118 of the substrate 112 that is electrically connected to 904.

Instead of this process, thinning may be performed until the bottom metallization 1502 is removed or the void 1100 itself is exposed (whether or not it is filled). FIG. 16 is a simplified cutaway view of a portion of FIG. 15 after the process of thinning the substrate to remove the bottom metallization; FIG. Preferably, if at least the method of FIGS. 11 and 12 is used, the empty space 1100 will be filled with the adhesive material 1102. Thus, as shown in FIG. 16, thinning the rear portion 118 of the substrate 112 until the bottom metallization 1502 of FIG. 15 is removed may still serve as part of the rear side electrical contact. The bonding material 1102 may be exposed while leaving the “ring” of the metal contact 1602 intact. Therefore, if the bonding material 1102 is electrically conductive (for example, solder), both the ring portion 1602 and the bonding material 1102 function as contacts. On the other hand, if the bonding material 1102 is not electrically conductive, the ring portion 1602 functions as a contact and provides an electrically conductive path from the rear portion 118 to the device contact 904, while providing the bonding material 1102. Can be used to bond the chip to other devices.

Instead of this approach, the configuration of FIG. 15 or FIG. 16 may be adapted to project out of the bottom of the wafer for use as a contact in a post and through manner, either alone or in conjunction with the tack and fuse methods described herein. It can also be thinned.

Here, the basic process described above, along with other more complex processes implemented according to the basic process described above, may form a via prior to fabricating devices (e.g., transistors, diodes, lasers, photo detectors, etc.) on the wafer. It should be noted that there is an additional effect compared to the prior art in that there is no need. In addition, according to this process, only vias need not be generated on the periphery of the chip where the existing wiring pads are generated. Instead, such instantaneous processing may be more localized, such that the circuit may be formed on or embedded in the semiconductor prior to via formation and may be performed at a sufficiently low temperature so that the vias may be placed in areas other than the main portion of the chip. . Thus, the process can be used without the need to include the process in the design of chips manufactured by other manufacturers, and wiring connections between devices on different chips as described in more detail below. It can be formed much shorter than when using the pad. In addition, as will be described in detail below, the process can easily form a path through the wafer, making the process very useful for forming chip stacks or mix and match chip units.

Regarding the process of filling the trench with electrically insulating material, the problem that pinholes, bubbles, or other defects may occur in the electrically insulating material, especially when the trench is narrow and relatively deep (eg more than 100 microns deep) There is. If such defects remain, unwanted conductive paths can occur between the doped semiconductor material of the device where the trench penetrates the device and the conductors are formed therein.

Fortunately, if there is such a potential problem or concern, other variations shown in Figs. 17-23 can be applied to practically solve the problem or concern.

FIG. 17 is a simplified cutaway view of a portion 100 of FIG. 5 as a result of processing in accordance with another variation as follows.

The via trench 1700 is formed as shown in FIG. 7, but unlike FIG. 7, the entire island 306 of the semiconductor material 122 in the annular portion 704 of the insulating material 500 is not removed. The via trench 1700 is smaller than that of FIG. 7, leaving a perimeter annulus volume 1702 of the semiconductor material 122. The major volume 1702 of the semiconductor material 122 is electrically insulated from the semiconductor material 122 of the device 104 because the boundary is determined by the insulating material 500 and the substrate 112. In addition, since the overall semiconductor material 122 is more complete and uniformly formed, any defects in the insulating material 500 in the trench 302 may cause any defects in the metal 1 in the vias 1700 by the housewife volume 1702 of the semiconductor material 122. It will be insulated from fire. Otherwise, the method is the same as described in FIG. Thus, similar to FIG. 7, the via trench 1700 is (preferably to a depth 1704 in the substrate 112 via, for example, additional drilling or other suitable treatment, such as laser drilling). May not be formed completely through the substrate). Once the via trench 1700 is formed, not only the bottom portion 1708 of the via trench 1700 but also the side walls 1706 of the via trench 1700 will be electrically non-conductive as described above, but the side walls 1706 may be It will be an insulated semiconductor material 1702 surrounded by the ring insulating material 704.

FIG. 18 shows the specific region 124 of FIG. 1 after forming the via trench 1700 in the annulus of the semiconductor material 1702 whose boundaries are defined by the electrically insulating material 704 as shown in the side view of FIG. 17. ) Is a plan view showing a cross section taken along line AA below.

FIG. 19 is a simplified cutaway view of a portion 100 of FIG. 5 as a result of further metallization of another variant of FIG. 17 in the manner described with reference to FIG. 9.

20 is a simplified cutaway view of a portion 100 of FIG. 5 as a result of further metallization of another variant of FIG. 17 in the manner described with reference to FIG. 11.

FIG. 21 is a simplified cutaway view of a portion 100 of FIG. 5 as a result of further metallization of another variation of FIG. 17 in the manner described with reference to FIG. 13.

FIG. 22 is a simplified cutaway view of a portion 100 of FIG. 5 as a result of thinning the substrate such that the bottom metallization 1502 is exposed in the manner described with reference to FIG. 15 for another variation of FIG.

FIG. 23 illustrates a portion 100 of FIG. 5 as a result of thinning the substrate such that the lower metallization 1502 is removed and the bonding material 1102 is exposed in the manner described with reference to FIG. 16 for another variation of FIG. It is a simplified cutaway view.

Based on the above, it is possible to form further alternative variants with double insulated conductors (ie, coaxial conductors). According to this variant, the double conductor has an advantageous effect because it enables a larger contact density to reduce crosstalk. Further, as can be seen below, according to the double conductor variant, the outer conductor can be electrically separated from the inner conductor and driven at a different voltage, and one conductor acts as an electromagnetic interference (EMI) blocking film It can protect against signal noise, or the signals can propagate differently through the structure so that low noise data transmission can occur. In addition, as in the single conductor method, a precision etching process defined by one lithography method is performed to form a cyclic trench. As can be seen below, the removal of the central material is controlled by the boundary metal and does not undergo the process changes that originally occur in the steps or etching processes defined in photolithography. Thus, this method is also more reproducible and has high process robustness.

Hereinafter, two coaxial modifications will be described with reference to FIGS. 24 to 29B. This variant is suitable when the outermost conductor can be in direct contact with the semiconductor material without adverse effects. Next, various other coaxial modifications will be described with reference to FIGS. 30A and 30B. The other double conductor variants of FIGS. 30A and 30B are similar and improved as the other variants shown in FIGS. 17-23 and are likewise suitable for substantially solving the same problems or concerns.

For the first time, the basic double conductor formation process is in the manner described with reference to FIGS. Since this variant is implemented based on the foregoing, only additional or other aspects related to this variant will be described for simplicity, and the rest will be appreciated from the previous description. Thereafter, the treatment according to another variant of the double conductor is as follows. First, as shown in FIG. 24, at least sidewall 304 of FIG. 3 is metalized 2402 as described above. The bottom end 2400 of the trench 302 may or may not be metalized, but this will not affect the final result, as will be apparent from the description below. FIG. 24 is a simplified cutaway view of a portion 100 of FIG. 3 immediately following the metallization according to this variation.

After metallization, at least trench 302 is filled with electrically insulating material 500. The result of this step is shown in FIG.

Referring again to FIG. 26, the via trench 2600 is formed by removing the entire island 2406 of the semiconductor material 122 whose boundaries are defined by the inner circumference of the annulus 2602 of the metallization 2402.

Alternatively, as shown in FIG. 27, a method similar to that of FIG. 17 may be applied at this point. That is, instead of removing the entire island 306 of the semiconductor material 122 in the ring portion 704 of the insulating material 500, only the inner portion of the semiconductor material 122 is removed so that the main ring volume 2704 of the semiconductor material 122 remains. (2702)

Otherwise, the scheme will then be substantially the same as described above. The via trenches 2600 and 2702 do not fully penetrate the substrate 112 to a predetermined depth (preferably through additional etching or other suitable treatment, for example, by laser drilling or removal). Can be formed).

Then, the conductors 2802 are filled in the via trenches 2600 and 2702 and the substrate is thinned as described above. In the case of the first double conductor variant (FIG. 28A), a thinning process is performed until the bottom metallization is removed and the inner conductor 2802 is exposed on the substrate 112 as shown in FIG. 28B. In the second double conductor variant (FIG. 29A), as shown in FIG. 29B, the thinning process is performed until the lowest part of the metallization part is exposed along the inner conductor. In the variant of FIG. 28B, one conductor consists of an outer ring of metallization 2804 and the other consists of an inner ring and inner conductor 2802 of metallization 2804. This is because the two are shorted in contact with each other, whereas in the modification of FIG. 29B, one of the conductors is made of the conductor 2402 and the other is made of the inner conductor 2802.

Thus, in the double conductor variant, as shown in FIG. 28B, it is more preferable that both the depth of the ring portion 704 and the depth of the via trench 2700 are both deeper than the point where the substrate is finally thinned. That is, if the total thickness of the wafer is 500 microns and the wafer substrate is as thin as 200 microns, the depth of the via trench 2700 will be at least 300 microns plus the possible metallization thickness, resulting in the ring portion 704. The original depth of would need to be deeper than the beer trench 2700. The reason for this necessity is the need for electrical insulation between the two conductors. Also for that reason, in some embodiments, failure to apply the bottom of trench 302 has little effect since it is removed in the thinning process.

Based on the foregoing, it should be appreciated that additional coaxial variations similar to FIGS. 28B or 29B can be formed by simply making the sidewalls of the trench non-conductive prior to metallization. This variant can be implemented, for example, by dielectric sputtering, plasma deposition, or by forming an initial ring trench in advance (ie prior to electronic device fabrication) and applying a thin dielectric film to the sidewalls using thermal or steam oxidation techniques. . This technique involves exposing the sidewalls to a reactive gas such that in the case of silicon wafers the sidewalls are oxidized (conceptually equivalent to rusting iron) to form a thin silicon dioxide film on the sidewall face. In general terms, the oxidation of silicon can be performed in a steam environment according to the Deal-Grove model. In this way oxidation can occur in a highly controlled and accurately reproducible manner. Similar processes can be used to form a silicon oxynitride film or a silicon nitride film. According to this variant, the result is that since the oxide film grows thermally without being deposited, it is advantageous in that it is formed uniformly and does not cause the problems that originally arise when applying liquid viscous paste or other types of dielectrics. In addition, a very uniform and highly controllable dielectric film is thus formed over a 12 inch silicon wafer to a very precise tolerance to a thickness of more than millimeters. Further, according to this step, the effect of smoothing the sidewall is obtained, which further contributes to the uniform metallization.

Of course, these additional alternatives may be inadequate in some applications due to the dielectric constant of silicon dioxide, silicon oxynitride, or silicon nitride and may not be feasible for other applications due to other factors not relevant to understanding the subject matter of the present invention. Can be. In addition, the method is the same as described in all of the modifications described above with reference to Figs.

For complete understanding, examples of adding the optional, additionally thermally formed dielectric or insulator 3002 to the scheme of FIGS. 28 and 29 will be described with reference to FIGS. 30A and 30B, respectively. . In some variations of FIG. 30B, that is, in a variant in which only a portion of the inner island is removed so that the annulus of the semiconductor material remains around the via trench, the process may be in a device preformed on or on the chip, or in or on the chip. If all of the above devices are not damaged for the process, the above-described feature processing may be carried out after appropriate measures are taken to prevent the process from damaging the devices previously formed on the chip. Assuming that it can be used, the thermally formed dielectric scheme described above can be used to form a dielectric film on the remaining annulus.

Alternatively, the partial removal process may be inverse partial removal. That is, the inner islands can be removed from the beer trench inward, leaving smaller islands inside the beer trench. According to this variant, the small island can act as a post on which a contact is made and connected to the metallization or conductor. Similarly, the partial removal treatment is partial removal in terms of depth to leave wells or depressions that can be used as male conductors of the male and female conductors or, if they become conductive, can serve as electrical contacts. Can be.

As a result, the three conductors (as shown in FIG. 31) are formed by performing the thinning as described in FIG. 28B but only to the extent shown in FIG. 28A (ie, until the metallization material at the bottom of the trench is completely removed). That is, it can be clearly seen that the three-axis) modification can be configured. These three conductor variants allow the outer metallization to act as a barrier between the inner metallization and / or the conductor and the semiconductor material supporting the nearby device and between the outer metallization and the inner conductor. There is an advantageous effect since the metallization can serve as a barrier or third conductor between the two. Thus, the three-conductor variant in itself has several different effects. Of course, in view of the relationship between the single conductor, the two-conductor, and the three-conductor, any of the options described (ie, thermally formed or applied) coated film for use with any of them , Void injection, post and through contacts (described below), etc., are generally mutually applicable to all of them.

As briefly described above, it is not necessary to fill the empty space left after the removal of the central island material with any. In addition, some embodiments described herein have a particular effect on not doing so.

32 illustrates coupling the chip 102 to the electronic chip 3200 such that the contact pad 3202 on the electronic chip 3200 to be electrically connected to the upper contact 904 of the laser 104 is below the empty space 3210. A simplified cutaway view of a portion 100 of a chip implementation disposed on an electronic chip 3200. The implementation of FIG. 32 is similar to the implementation of FIGS. 9-16 except that no void 3210 remaining after metallization is filled at all. Solder bumps or other soft, deformable, electrically conductive materials 3204 are placed on the contact pads 3202 and physically pass this portion of the two chips 102, 3200 through deformation or capillary action upon insertion by pressure. Also used for electrical bonding.

33 illustrates coupling the chip 102 to the electronic chip 3300 such that the contact pad 3302 on the electronic chip 3300 to be electrically connected to the upper contact 904 of the laser 104 is below the void 3310. A simplified cutaway view of a portion 100 of another chip implementation disposed on an electronic chip 3300. The embodiment of FIG. 33 is similar to the case of FIG. 23 except that the empty space 3310 remaining after metallization is not filled at all, as shown in FIG. 32. Solder bumps 2404 are placed over contact pads 3302 and will be used to physically and electrically bond this portion of the two chips 3302 and 3300.

32 or 33, by not filling the voids 3210 and 3310, capillary action can be used to draw the solder 3204 into the voids 3210 and 3310 and use pressure to deform the material ( 3204) may be modified to enter the void, thereby a) ensuring good electrical connectivity, and b) helping to align the chips.

34 and 35 illustrate cross-sectional views of FIGS. 32 and 33, respectively, after coupling the chips together. As shown, the solders 3202 are respectively centered on the contacts 3202 and 3302 of the respective electronic chips 3200 and 3300 to which the chips are coupled, with the contacts 3206 and 3306 of the chips relatively centered. Is pulled into the empty spaces 3210 and 3310.

As shown in FIG. 36 for the embodiment of FIG. 34, the insulator or conformal coating 2800 may optionally be performed (although the same applies to the implementation of FIG. 35 (not shown)).

As briefly mentioned above, irrespective of the variant used, the above-mentioned annular trench can take any closed form (as well as the perimeter of the semiconductor material, if that variant is used). However, as an extended concept of the foregoing, most of the implementations take the same form to facilitate implementation, as well as capacitance or resistance, or both, but the via trenches do not have to take the form of annular trenches. Note that the width of the annular trench need not be uniform. 37A-37F show several representative examples of cross sections of annular trenches to illustrate this point. In FIG. 37A, the annular trench 3702 is shown in a triangle. As a result, the width 3704 of the trench 3702 is larger at each point 3706 than each side 3708 of the triangle. In FIG. 37B, the annular trench 3710 is shown rectangular. As a result, the width 3704 of the trench 3710 is larger at each edge 3712 than each of the sides 3714 of the rectangle, and the long sides 3716 are farther than the short sides 3718. In FIG. 37C, the annular trench 3720 is shown such that the boundary is defined by two different ellipses. As a result, the overall width of the annular trench 3720 varies with location. In FIG. 37D, the annular trench 3722 is shown square. As a result, the width of the trench 3722 is larger at each corner than at each side, but each side is equally spaced from each other. In FIG. 37E, the annular trench 3724 is shown as a rectangle on the outer circumference 3726, but is circular on the inner circumference 3728. In FIG. 37F, the annular trench 3730 is shown as a rectangle on the outer circumference 3732, but is square on the inner circumference 3374. In FIG. 37G, the annular trench 3736 has an uneven shape (or kidney), wherein the outer circumference 3738 and the inner circumference 3740 are reduced / expanded at a constant rate with respect to each other and the width of the trench is constant. Do. In FIG. 37H, the annular trench 3742 has an outer circumference 3734 similar in shape to that of FIG. 37G and has an inner circumference 3746 that is hexagonal.

The concept extended from the above is equally applicable to the variant having the annular portion of the semiconductor material. That is, the shape of each peripheral surface may be the same as the others, and one or more principal surfaces may be different from one or more other principal surfaces as required or needed in a particular application.

In addition to the effects originally obtained from using the method described above to finally form a connection between two chips, the method described above has a great effect in terms of area of chip, die or wafer stacking. In the case of a chip, die or wafer being pre-machined, for example, in terms of the transistors, capacitives, diodes, switches, resistors, capacitors, etc. that it will contain, any device that functions will be formed on the functional side. In the case of a complete formation, there is especially such an effect.

By forming vias using an annular hollow process, a method is obtained in which the wafers can be stacked in such a way as to achieve electrical conductivity and to require little or no post-treatment after melting the wafer. This is very effective in terms of cost and yield, especially at the wafer level where two wafers are combined or one wafer is placed with several individual chips. When joining wafers, one of the major implementations is that the combined two-wafer piece (after joining two wafers) will have a much higher value than the single-wafer piece (which is one wafer just before joining). . Similarly, stacking three pieces of wafers together results in much higher values. Any post-processing performed after integrating a series of stacked dies adds a great risk because damage will result in the destruction of very largely added pieces.

Therefore, according to the above processes, a much better manner is obtained because via processing and thinning occur before lamination. As a result, pieces ready to be stacked are formed and one piece can be placed to join (ie, join) on top of another, without additional wafer processing, and forming vias after and before the formation of the on-chip device. This is a completed state. As the chips are stacked in the manner described above, the value of the combination gradually increases, i.e., the number of steps of attaching another layer (i.e., another die), i.e. if thinning is not required and thinning was performed prior to bonding. Is usually just one. This minimizes the risk of yield loss for expensive components due to the post-processing that originally occurs in conventional stacking schemes in which chips are stacked and subsequently made electrical contacts.

Thus, as compared with the prior art, forming the vias before lamination makes it possible to:

1) there is no post-treatment on the laminated piece at all or a reduction (thus, less labor and increased yield);

2) The alignment tolerance becomes very large (ie, unlike conventional stacking where all pieces must be aligned in common with the bottom piece, each chip only needs to be aligned well with the chip just below it).

38 is a diagram schematically illustrating a general outline of a process of preparing a wafer for lamination. 38A shows in simplified form a portion of an initially fully formed wafer, in particular the apparatus 3802 and its lower substrate 3804. The general process is as follows. First, material 3806 is laminated to the device side of the wafer (FIG. 38B). The material 3806 and its underlying portions for contact are etched to form a trench 3830 (FIG. 38C). The walls 3810 of the trench 3808 are insulated (3812) to prevent the possibility of shorting of the contacts to be formed with the contacts to be formed (FIG. 38D).

Instead of this treatment, material 3806 may be automatically formed during the lamination of insulating layer 3812. For example, the first stack of material 3806 is removed, the trench 3808 is etched and then the TEOS is placed over the wafers by stacking the TEOS (oxidation material). Because of the way this material is stacked, 2.5 microns of material are placed on top of the wafer and 1.25 microns are placed on the walls in the trench. This results in another way of obtaining a thick top layer while covering the walls of the trench. That is, in this manner, the process of placing the material 3806 as a separate step can be omitted or can be used with the remaining steps depending on the topology of the wafer.

Metal 3814 is then implanted into the trench to provide a seed layer for plating of the conductor (FIG. 38E). The remaining via volume is then filled with metal 3816 to be the conductor (FIG. 38F). The extra metal (and optionally the insulating layer 3812 and a portion of the metal 3806) is then removed, for example, by chemical or mechanical treatment or any combination thereof (FIG. 38g). The wafer is then etched to form openings 3820 and 3822 to allow access to the original contact portions 3824 and 3826 (FIG. 38H). Metal 3830 and 3830 are then applied to interconnect existing contact portions 3824 and 3826 with contacts 3832 and 3834 formed by new processing (FIG. 38I). Subsequently, the rear portion 3826 of the wafer is thinned to expose the other ends of the formed contacts 3832 and 3834, and optionally to remove the insulating portion 3812 at the bottom of the trench 3808 (FIG. 38J). ). Subsequently, the rear portion 3826 of the wafer is etched to form raised posts 3838 and 3840, and if the insulation 3812 at the bottom of the trench 3808 has not been removed in the previous step, the insulation 3814 is removed. (FIG. 38K). Instead of this process, in some embodiments, if the insulation 3812 is partially removed, or if electroconductivity is not needed (eg, used to simply align or form non-conductive post-shaped connections) It may not be completely removed. Finally, if the exposed filling material to be the post is of a type that can oxidize or cause adverse reactions to later forming connections, the optional barrier layer 3842 is formed on the raised posts 3838 and 3840. Application to prevent oxidation or other adverse reactions.

According to another variant, a soft or malleable material is applied on top of the metals 3828 and 3830 to protect the metals and then the steps of FIGS. 38J, 38K, and 38L are used as described below. Can be performed. According to this variant, the number of steps to be performed after thinning the wafer can be reduced.

In this case, a general through-chip connection is formed, and the stacking may be facilitated on a chip, a die, or a wafer substrate, and one or more wafer units may be formed.

Figs. 39-41 are views generally showing certain portions of chips stacked to form such a unit after being fabricated to form through-chip connections using other variations of the above-described processes. In particular, FIG. 39 shows corresponding portions 3900 of a series of stacked chips interconnected with each other using a variation of the basic scheme. 40 shows corresponding portions 4000 of a series of stacked double conductor modified chips. FIG. 41 shows corresponding portions 4100 of a series of stacked triple conductor modified chips. By using one of the processes described in the present invention, stacks and units can be formed from wafer components that do not need to be configured in a coplanar manner or in a completely overlapping manner but are still extendable in a vertical direction. It will be appreciated from the above description that there is.

Within each of the three stacks of FIGS. 39-41, optional contact pads 3902, 4002, 4102, 4104 are added as standoffs, thus providing adequate clearance and good electrical contact between wafers. Will be secured.

Depending on the particular application in which the foregoing schemes are used, the contacts can be formed in various ways. For example, the vias described above are microbumps formed therein by prior art C-4 solder type processes, where the two points to be electrically connected are brought into contact and the solder turns into a liquid phase, which is then cured to form the two pieces. It is to be physically and electrically coupled. In another variant, one of the pair of contacts is rigid and the other is using a pair of contacts that are relatively soft relative to it and the two can be joined using the process described herein. According to another variant, both of the contact pairs can form a ductile material thereon and combine the two using the appropriate process described in the present invention or other techniques. Alternatively, conventional post and socket types may be used. In this way, the two contacts have a post fit that is slightly larger than the Socat, or that the Socat is slightly smaller than the size of the forcat, resulting in an interference fit between them. This takes a complementary form.

In some cases, it may be desirable to secure the strength during handling using a thick wafer (FIG. 42A). If the wafer is particularly thick and the diameter of the desired via is smaller than approximately 1/20 to 1/30 of the thickness of the desired wafer, some variations may be used to accommodate thicker wafers using a process different from the above. The process of forming such a “back to front” via is shown in simplified form in FIGS. 42B-42E. First, the back side of the wafer supporting the apparatus is etched to form a via (FIG. 42B). The via is then made conductive through other predetermined processes such as using one of the processes described herein (such as single conductor, coaxial, triaxial, etc.) or inserting a preformed post (FIG. 42c). This approach results in the rear side having either a ductile material or a rigid post material. Then, from the top (on the front or device side) over the conductor, it is etched down to the point where the bottom of the rear conductor ends, forming a corresponding via (FIG. 42D). Then, optionally, the front side devices are protected and, if desired, contact or rerouting to the devices is carried out (not shown) using, for example, the manner described herein. The vias are made conductive in substantially the same manner used on the back side (FIG. 42E). According to some variations, the material at the bottom of the backside conductor has the advantage that it can serve as a seed layer for plating the etch stop film and / or the conductor from the front side. This can reduce the number of processing steps compared to the method used to form the conductor on the back side. Further, according to another variant, where it is desired that there is no physical connection between the conductors from the rear vias and the conductors from the front vias, between the two conductors in a connection made via capacitive coupling Appropriate amount of wafers may be left.

This method can be applied with two existing via forming processes in which a single via is formed and the insulator and metals are stacked in one hole, or in the process of the present invention described above, it can be applied in conjunction with the annular via method to provide a high degree of control. Impedance vias can be formed.

Also, on one side there are vias that are not fully filled so that the unfilled portion of the via serves as a “slot” to receive a “post” (ie a pressure or interference fit connection) to provide alignment and / or electrical connectivity and Where physical connectivity can be achieved, a scheme from rear to front can be used. This type of pressure or interference fit is shown in FIG. 42F.

According to another variant, the above-described method of forming vias from the back to the front can be used to form the connection partially passing through the chip in such a way that capacitive coupling can be used for data transfer between the chips. Since capacitive coupling operates when the contacts are close and the density of the connections is limited by crosstalk, variations of the schemes described herein are ideal for forming chips using communication types. These methods can easily minimize crosstalk by close connections, since the distance between the contacts can be minimized by using coaxial or triaxial posts to provide blocking means. In addition, capacitive contacts have the advantage that no substantial electrical contact is required between the components. In this way, as shown in Figs. 43A-43D, the vias are close enough to the contacts on the top of the chip to physically remove them from the contacts, but the good capacitive coupling of the signal applied between the filling material and the contact when charged. The vias are etched from the back of the chip to form vias in such a way that the vias are close enough to allow this (FIG. 43B). This via is then filled with a metal stud and a single conductor, coaxial or triaxial conductor to obtain good capacitive coupling (FIG. 43C). In this way, it is possible for the wafer to maintain the overall thickness at which the connections have the proper distance and at the same time obtain sufficient strength for wafer handling. This approach has the additional advantage that a stack can be produced by stacking the back side of one wafer on the front side of another wafer. In this way, multiple stacks of chips (ie, stacks of three or more chips) can occur as shown in FIG. 43D. The way in which the chip should face forward and backward rather than face to face is to avoid the possibility of crosstalk, as the third chip is placed behind one of the other two chips and communicates across the wafer. The contact density will need to be low, so it is not easy to cause chip stacking. Of course, according to the scheme described in the present invention, coaxial or triaxial vias can be used to improve the signal blocking property to prevent crosstalk.

Also, for example, if there is no true rear-to-forward connection in that the two vias are not connected to each other (i.e., material remains between the vias formed from the front side and the posts on the rear side), Capacitive coupling can be used with pressure fit connections. In such a case, the front via will be formed independently like the rear via according to one of the variants described herein.

In addition, capacitive coupling can occur between one or more contacts on the chip surface (whether or not formed via a via or other method). This approach is, for example, because the chip or metallization is kept between two complementary contacts or is isolated by other structures, or one or both of them are insulators, photoresists or the like such as TEOS. Since it is covered by oxides other than the above, it is preferable when the height of the chip is such that, for example, the height of the chip is not easily physically easily contacted by the topology even though two complementary contacts are close by the lamination method. can do.

  It will be clear from the foregoing description that the various functions of the inventive method are more clearly understood. It is also possible to form another variant that represents the broad and varied possibilities achievable using the methods of the present invention. One such variant is shown in FIGS. 44A-44I. This approach is a “pre-connect” variant, in which a preformed lower wafer 4402 (hereinafter “base”) is formed before any processing described herein begins (ie, before forming the annular trench). This method is different from the above-described method and others because it attaches a wafer to be processed to a wafer (“wafer”). In this variant, any of the basic linkage forming processes may be used. This deformation | transformation process is performed as follows.

First, the initial wafer is thinned down to the extent necessary to allow the via to fully penetrate the substrate (FIG. 44A). This step is optional and need not be performed if the particular etching process to be used can penetrate the entire chip without difficulty. The initial wafer is then aligned (FIG. 44B) and attached to the base wafer using bonding or wafer fusion, or covalent bonding if the wafers are very flat (FIG. 44C). Next, an annular via is formed in the initial wafer across the pads of the base wafer such that the annular via extends down to the base wafer to surround the desired pad on the base wafer (FIG. 44D). The annular vias thus formed are then filled with insulator so that subsequent conductor deposition is insulated (FIG. 44E). Subsequently, all or a portion of the center post is etched down to the desired pad on the base wafer to form a void on the desired pad of the base wafer (FIG. 44F). Finally, the voids are metallized (FIG. 44G) and, optionally, completely filled with voids with a conductor (FIG. 44H) using one of the methods described herein, or by the metallization of the voids. If the center is not completely filled, it can be filled with insulators (Fig. 44I). As a result, the metal injection creates an electrical connection to the base wafer, which effectively extends the base wafer pad up through the initial wafer, causing the two chips to be physically coupled. Using this approach, the advantage is obtained that the center post of the semiconductor material can protect the pad of the base wafer so that the insulator does not interfere with the base wafer pad. This is quite different from what is obtained when trying to do the same thing using the existing method, since according to the conventional method it can be contaminated by the applied insulator by leaving the base wafer exposed.

In some cases, however, pressure fitting connections may not be appropriate due to the lack of control. In such a case, an alternative alternative method according to the present invention may be called a "post and through". Ideally, the post and penetrating methods can and will be used in conjunction with the tack and melting process, as there are other benefits of using the post and penetrating methods and the “tack and melt” process respectively. .

This approach uses a combination of two contacts, a rigid “post” contact and a relatively soft pad contact (relative to the post material). In some cases, one or both of these contacts have a lower rigid support structure or standoff. Briefly, one of the two contacts is a contact made of nickel (Ni), copper (Co), or palladium (Pd) or other suitable rigid alloy as described herein. This contact acts as a "post." The other of the two contacts, when the two contacts are brought together by pressure (by external forces, or by, for example, the bending of the wafer), the post penetrates through the flexible material ("Post and through" part), two contacts when heated above a predetermined temperature (choose during the tack and melting process) and when the two contacts cool to a temperature at which neither of them will become liquid It is made of a material that is softer than the posts so that it can be tack bonded.

As used herein, the term liquid phase means that the metal or alloy mentioned is in a completely (or substantially completely) liquid state. When the metal is in a non-liquidus or semi-liquidus state, as used herein, the metal is soft enough to be attached as described above, but the same metal or alloy is a complete liquid. Or in a liquid state sufficient to move or flow as if in a liquid state. Most variations of the processes of the present invention will be applied with metals or alloys in non-liquid and non-solid states. That is, on a phase diagram for a metal or alloy, a variant according to the process of the present invention is applied between a solid phase (complete solid) temperature and a liquid phase (complete liquid) temperature, most of which are equilibrium points between these two temperatures. Applied nearby. 33 and 36, the difference may be better understood by referring to, for example, coupling a chip to another device. In these figures, if the material 2404 is a solder (metal or alloy) in liquid phase, the chip will then float on the molten solder, and the capillary action pulls the solder toward the vias 3210 and 3310. The vias 3210 and 3310 will then center themselves on the solder ball. In the non-liquid or semi-liquid state as used in most variants of the tack and melting process described herein, during the period of both the tack and melting steps, the metal or alloy is very ductile (ie, some materials Liquid), but not enough liquid to float the chip or to center the vias 3210 and 3310 themselves. Thus, in order to allow the metal or alloy to enter the vias 3210 and 3310, it is necessary to apply some force (whether from external or external forces resulting from the weight of the chip).

Subsequently, a second heating that raises above another temperature above the “tack” temperature (the melting phase of the tack and melting process) causes the solder to become liquid and out of the liquid phase (ie, melted and cured again). In contrast, the materials are each interdiffused.

The tack and melt bonding process is divided into two main parts, the “attach” or “tack” stage and the “melt” stage. The tack step allows a very uniform electrical connection between the tack pairs. Combining the formation of post and through junctions with tack bonds can easily penetrate any surface oxides on any of the contacts. This non-oxide inhibited contact enables a simple melting process without the need for high pressure. In the absence of a combination of post and through and tack steps, the melting process is intended to allow the contact to penetrate oxides formed on the surface of the rigid and malleable material during the hot portion of the tack process or at an early stage of the melt process. Will actually require greater pressure. By allowing such oxide “crusts” to pass through the initialization of the tack phase, a fusion step occurs at substantially lower pressures, and in some cases a fusion step occurs without adding pressure beyond the weight of the chip itself.

At this point, other terms will be defined. As mentioned in the present invention, "daughter" and "mother" are generally used for convenience to mean whether a particular contact on the wafer mentioned is rigid or soft, and the term "mother" is associated with a rigid contact. And "daughter" is associated with soft contacts. Although the present invention has been illustrated in a consistently one-sided manner, it should be noted that "mother" and "daughter" may be arbitrarily applied. The contacts on each wafer may be either rigid or soft as long as the corresponding contacts on the other wafer to be joined to each other are of opposite types. Thus, there may be exclusively one or the other type of contact on a given wafer surface, and depending on the variant, both types may be mixed on one side of the wafer. However, depending on the application, mixing the types on one surface may cause problems. In such an application using the same, the different types may be limited to discrete areas without mixing with each other in one area. Mixing types on a single surface complicates processing unless it is not intended to include only one contact type across so that an area comprising the other type can be easily protected when certain processing steps are performed.

During the attach or tack phase of such a process, "daughter" chips are placed on the "mother" wafer. The mother wafer is kept at a single temperature. In other words, the mother wafer is held as an isothermal substrate during the attachment process. Increasing the isothermal temperature of the mother wafer above room temperature may increase the speed of the attachment step of the process, but may reduce the isothermal temperature of the mother wafer to about room temperature. However, not only the tack or melting temperature, but also the isothermal temperature are maintained below the melting point of the soft material on the daughter chip. Thus, when two chips are contacted to produce a post and through connection, the small daughter chips are each heated to a high temperature so that the interface for that chip reaches or slightly exceeds the appropriate “tack” temperature. A tack process can be performed. In general, for the main materials mentioned in the present invention, the tack temperature is between about 190 ° C and about 320 ° C, and typical typical tack temperatures are about 270 ° C. In this way, the contacts of other chips on the mother wafer can change the performance of the contact and some contacts will experience the elevated temperature for a much longer time than other contacts, the elevated temperature as a condition. Will not be heated above the point where the contact of the other chips will be experienced and possibly result in uneven performance.

The tack or attach process, for example, maintains the mother wafer at an isothermal temperature below the malleable temperature, takes the daughter chip to a mother chip, such as below the malleable temperature, and then makes contact between the two chips, thereby reducing the temperature of the daughter chip. This can be done by rapidly rising to an appropriate tack temperature. Thus, when the daughter chip is attached to the mother wafer, the machinery to align the parts (heating the daughter chip) and the mechanism only provide enough pressure (e.g. per pair of contacts) to allow some contact between the parts. A pressure of 2 g or less, preferably 1 g per pair of contacts) is applied and then the pressure is released from the daughter chip.

After release, the cap / adhesive layer on the daughter chip (or the soft layer, if the soft material also performs the function of the cap / adhesive layer) is a reduced temperature that can be thought of as the overall temperature of the mother chip at that point. It becomes less flexible. For example, in the baseline materials described herein, the mother chip / wafer substrate may be maintained at a temperature of approximately 230 ° C. to 250 ° C., and the daughter chip may reach the mother chip at a nominal temperature of approximately 270 ° C. After the temperature rises rapidly and the contact is made, the temperature rises to about 310 ° C. to 330 ° C. The order of the contact for rapid temperature rise (ie, whether it occurs before or after the contact with the mother wafer) is changeable. Obviously, the inventors have found that contacting the chips first and then raising the temperature minimizes oxide formation on the surface of the ductile material, thus allowing more reproducible contact. Preferably, the use of soft materials can lower the amount of pressure in the unit contact pair. The inventors have specified a range of pressures applied to unit contact pairs of approximately 0.001 g to 10 g, although a lower range is possible, the lowest pressure being the effect of gravity on the mass (ie weight) of the chip itself. .

In addition, as mentioned above, in the case of a tack process, a daughter wafer temperature as low as room temperature can be used if sufficient pressure is applied to break any surface oxide. In this way, daughter chips can be mounted to the entire mother wafer before the tack state begins. Even with this method, due to the speed at which the process takes place, there is no time for the mother wafer to be heated to a significant extent. Thus, the attachment of the second daughter chip to the mother wafer does not soften the cap / adhesion layer of the first chip, even if the size of the first chip in the horizontal and vertical directions is within 100 microns, thus meaning or significant You won't be able to do that sort.

Preferably, both the tack and melting processes are typical non-liquid process. This means that the process is carried out so that the soft material is significantly softened, but does not turn completely liquid during the tack or fuse process. The reason is that if the ductile material is in a liquid state, there is a great risk that the resulting liquid will flow and cause a short at adjacent contact sites. By keeping the materials in a non-liquid state, higher contact densities can be achieved. However, in some variations, a semi-liquid state may be acceptable (ie, a portion of the ductile material, notably less than the whole, may temporarily become liquid). However, these variants contain a liquid soft material in a confined region to avoid the possibility of a short in adjacent contact sites, for example, a pad to which the soft material is applied may be a nonmetal that is not easily fuseable with the soft material. By having the material surrounded or covered on its periphery, it has in common the common features of using some other type of bondage mechanism to prevent the liquid soft material from causing side effects.

In some variations, with respect to the "tack" state of the tack and melting process, the soft material (e.g., Sn) may be made of an adhesive layer (e.g. Sn) that For example, it may be desirable to cover the Au / Sn alloy). In addition, in some variations, the melting temperature is such that bond degradation does not occur when the chip is mounted at that temperature for an extended time under uncontrolled environmental conditions (ie, the time it takes for the chip to mount to the entire wafer). It may be desirable to maintain the mother wafer at an isothermal temperature of the highest possible temperature below. Although the temperature may be even higher to speed up the treatment, we typically use a temperature of 230 ° C. The effect of lower temperature is a change in temperature and pressure profile of the penetration state of the attachment. Moreover, in order to speed up the processing, it is desirable to allow a series of processes (ie, location and heat) to take place as soon as possible. Another aspect to note is that, in some variations, the longer the time spent in the tack state, the less the decisive influence on the yield or the like of the molten state. For example, at one extreme on FC150 (silicon-to-silicon), we had a tack state that lasted approximately 1 minute, and no fusion state was needed. This is summarized in FIG.

At the other extreme, in the case of a solid, the alignment is typically about 1 second and the tack state is held for 2 to 4 seconds before the molten state. Thus, in these variants, the environment for the transition from the tack state to the molten state may be important for obtaining good contact.

Between these two extremes, there is a continuum of process options where adjustments are made between 1) throughput, 2) complexity, and 3) criticality of the melting process. For a very fast tack process of 2 to 4 seconds, the chips may remain light and thus require a reduced environment during the molten state or a substantially higher applied pressure during the molten state. At the other end of the spectrum, a one-minute tack process is performed at higher pressures and temperatures, and the tack itself performs a relatively good function of the preliminary "melting operation" of the chips. In this case, the subsequent "melt" process may simply be a contact anneal combined with a method of ensuring consistency across the wafer, provided that the flatness of the chip placement is met during a particular environment (or 'tack' state). , No specific pressure). Such a continuum is illustrated in FIG. 46.

An important advantage associated with the tack state is that the inspection of the chip can be performed after the tack process is completed but before the fusion process begins, since the electrical connection is not final and can be easily restored. This can be accomplished by inspection and identification of bad dies before and after the first state of hybridization, in which individual chips that were being performed prior to hybridization to another chip were adversely affected by the hybridization process, or with the chips to which they were attached. Allows a judgment as to whether it is ineffective in the combination of. Moreover, when the daughter chips that are cut are mounted on an uncut mother wafer, inspection can be performed before the mother wafer is cut or cut.

Another important advantage associated with the use of the tack state is that because the chips are so tightly coupled, they can be easily separated if the subsequent inspection determines that one of the combined chips is not being performed. The separation of the two chips can be done using heat or pressure, or both heat and pressure. In the case where individually cut daughter chips are mounted on a mother wafer that is cut or not cut, another "known good" daughter chip may be attached to the mother wafer if there is a problem with one daughter chip. It can be noted that when a particular mother wafer chip is bad, no more daughter chips are attached, and in both cases significantly increasing the overall yield, it is easy to identify the subsequent subsequent cutting of the wafer immediately. In addition, if the mother chip is not functioning properly, the daughter chip that has already been removed can be retained for later attachment to the mother chip, resulting in increased yields and potentially cost savings. For example, assuming that the soft contacts of the daughter wafers are made of gold-tin or gold-silver-tin alloys, and that the soft cap is made of tin, the tin can be attached at low temperatures, so that if it is thin enough, a thick solder ball Does not spread like If the inspection indicates that the daughter chips are bad, the individual chips on the mother wafer are heated, separated from each other, and another daughter chip is attached. If all daughter chips are attached and the inspection shows good bonding, the entire mother wafer is fused together.

Thus, the tack and fusion method allows the use of only one integrated well known die. In addition, this method significantly reduces the risk incurred when stacking multiple dies, since a single bad chip does not require fragmenting the entire stack. If chips and stacked units are expensive, this is an inherently and naturally significant advantage.

Moreover, tack and melt conditions provide another advantage of performing the process at low pressures. The forces used in the tack and melt conditions are typically less than 2 g per unit contact pair of contacts on a pitch of 50 microns or less. In the molten state, we demonstrated the use of a force between 0.8 g and 0.001 g per unit contact pair. For 400 contact chips we used 300 grams and for 10,000 contact chips we also used 300 grams in the range of 0.75 to 0.03 g per unit contact pair. For larger numbers of contacts, for example 900,000, we used 3 kilograms under conditions of 0.003 g per unit contact pair. Ideally, to speed up, use the least possible force, and under appropriate circumstances, do not use any force beyond the force exerted on the chip by gravity (ie the weight of the chip).

Conventional processes for attaching dies together require attachment strengths of several grams to several tens of grams per unit contact pair. This puts a great deal of stress on each of the semiconductor chips and can often damage or crack the semiconductor chips. Thus, the method described above can dramatically reduce or avoid the application of stress found when using conventional methods.

In addition, more conventional methods are not suitable for the small dimensions that we can employ. Typical soldering processes are liquid processes, which are not suitable for such small sizes and pitches, and do not apply several grams of pressure per unit contact pair. In other words, typically at 5 g per unit contact pair, 50 kilograms are needed to attach a chip with 10,000 contacts in a size of 1 cm x 1 cm. In contrast, the pressure in the molten state of the process is typically less than or equal to the pressure used in the deposition process. For example, using the melting process described herein, 10,000 contact chips, which required 300 grams under pressure at the tack state, needed only 9 grams in the melt state of the process.

In addition, if you use little pressure or no pressure at all, you can make multiple reflow / multi high stacks practical. In order to produce high stack multiple chips, the amount of pressure exerted on the chips is such that during the fusion of the chips thereon, especially when some chips on the mother wafer receive a larger daughter chip stack than others, It should be as low as possible to prevent chipping, to prevent yield loss, and to prevent the possibility of separation of underlying chips in the stack. If actual pressure needs to be applied to the mother wafer and daughter chips during the fusion process, and if some of the mother chips have a larger stack than others, it is difficult to maintain the correct pressure on each chip. A tool set is needed. In contrast, using the method of the present invention, which requires a slight external force or does not require an external force at all, avoids this, making multiple high chips more practical, allowing for double height or higher stack differences. can do.

Another advantage of the variant of the methods described herein is that the strength after completion of the melting process is high. The strength of the contacts after the melting process is more than a few hundred kilograms per square centimeter, typically 1000 kg / cm 2. Of course, as a result, once the melting process is completed, the reprocessing potential is significantly reduced.

Representative, non-limiting examples of soft materials are gold-tin (Au / Sn) alloys, silver-tin (Ag / Sn) alloys, and other materials also identified herein. It should be noted here that the term "post" is simply used to indicate rigidity. It is not intended to be used to limit or constrain the size, shape or geometry in any way. Thus, as described below, and as described in the section “Specific Variants”, the term “post” is either large or has a cross-sectional profile sufficient to achieve the intended purpose described herein. Its meaning may be broader. In addition, the term "post" may be generated as part of the processes described herein, for example, by thinning the back of the wafer without thinning the metal coating or metal contacts, or after being separately produced, It may be attached or inserted.

When a stack is included, certain electrical connections through the wafer may have rigid contacts at one end and soft contacts at the other end. In this case, for the sake of simplicity, once a wafer is referred to as a "mother" or "daughter", these terms refer to a post in which, in the subsequent stack layer, the "daughter" wafer is referred to as a "mother", And because it is a rigid contact for forming a penetrating connection. For greater clarity, the subsequent "daughter" wafer, connected at its other end, will be referred to as "daughter wafer 2".

One example of such a method is illustrated in FIGS. 47 and 48. 47A and 48A, complementary contacts 4702, 4704, 4802, 4804 are shown disposed over each of the two chips 4706, 4708, 4806, 4808. For simplicity, electrical connections 4710 and 4810 as well as other elements are shown to be located just beyond the perimeters of contacts 4702, 4704, 4802, 4804.

As shown in FIGS. 47A and 48A, one of the contacts 4704 and 4804 is a rigid contact, and the other contact 4702 and 4802 is a soft contact. 47B and 48B show respective contacts 4702, 4704, 4802, 4804 in the location where they are in contact with each other. By applying pressure before or in the tack state, rigid contacts 4704 and 4804 penetrate through soft contacts 4702 and 4802. 47C and 48C show the contacts after the molten state, where the two materials are now fused together to form a strong bond between the two.

In addition, the "width" of a flexible contact may be "minimum" because it has the same or smaller width than the contact (before joining) to which the connection is to be made, or "extension" because the width may exceed the minimum width. It may be noted that it may be a "contact". In the examples above, FIG. 47 shows an example that includes “minimum” contacts, and FIG. 48 shows an example that includes extended contacts.

In general, it is desirable to make the size of the soft contact slightly larger than the rigid contact, ie to use an extended contact. By doing so, the flexible contact surrounds the rigid contact, and precise alignment between the two chips is achieved during integration. The reason is that in such a case, the rigid contact needs to penetrate somewhere within the area of the flexible contact. As a result, a larger alignment offset can be adjusted. This is best understood by example through consideration of soft contacts having a circular cross section of 12 microns in diameter and rigid contacts having a diameter between 10 and 6 microns. If the diameter of the rigid contact is 10 microns, an offset of 3 microns will occur at the edge of the rigid material and extend beyond the range of the flexible contact. If the diameter of the rigid contact is 6 microns, the offset of 3 microns still remains sandwiched within the 12 micron diameter into the soft contact material. Typically, the rigid contacts generally span less than 40 microns at the widest point and may span less than 25 microns, less than 15 microns or less than 10 microns at the widest point. Moreover, using the method of the present invention, the flexible contact can be at least as wide as the rigid contact, preferably at least 20% wider. Moreover, the post height can be larger or smaller than its width, but typically is wider than the height.

In view of the above basic description, the method of the present invention is flexible, for example, by employing a suitably rigid material as part of a metallized or conductive material to be used as a rigid contact, and for attaching or laminating to other components. By applying a second, soft material to another portion of the metallized or conductive material so that it can be used as a contact, its scope of application can be extended to the modifications described above.

FIG. 49 shows a portion of a stack of semiconductor chips having through-chip connections made in accordance with any one of the foregoing embodiments, in a manner similar to FIG. 41. For the sake of simplicity and clarity, the through-chip connection is not shown as being connected to and through the device on an individual chip, since the presence or absence of such a connection is essential for understanding the post and penetration approaches. Because it is not.

As shown in FIG. 49, to allow each chip to be easily connected to and / or down, optional contacts 4902 and 4904 are added above and below metallization 2412 and conductors 2802. It is provided with. As mentioned above, metallization or metal contacts may be used directly. If any contacts 4902, 4904 are added according to a particular embodiment, these contacts 4902, 4904 are conventional contact pads of a simple configuration of one of the prior art types, or the posts formed as described above It may be formed in the form of a through contact without or a through contact with a post.

Thus, it will be appreciated that the lamination operation can be performed more easily by using the post and through approach of FIG. 49. A portion of a simplified form of the stack of chips shown in FIG. 49 stacked using this post and through approach is shown in FIG. 44.

It will also be appreciated that variations of some of the foregoing embodiments are possible to facilitate the use of such post and through contact approaches. For example, in an embodiment similar to that shown in FIG. 15 (ie, where the metallization of the trench bottom is not completely removed) except that the junction substrate 1102 and the finish substrate 1302 are not present. Thus, the metallization 1502 can be used as either a rigid or malleable contact, and the second material inserted into the void is rigid if the metallization has the "malleable" property. If the metallization is " rigid, " In this embodiment, as shown in FIG. 51, the voids inside the metallization can be filled, for example, with preformed posts 5102 inserted at appropriate points during processing. Optionally, the metallization 1502 and the second material may be made of the same material when the soft material is coated at an end that contacts the other "rigid" material to form a bond.

52 briefly illustrates the form after the chip of FIG. 51 is coupled to another electronic chip 5200. Here, the electronic chip 5200 is shown with a drive and control circuit diagram 5202 for controlling the laser 5104 shown in the chip of FIG. 51 for illustrative purposes. The electronic chip also includes a post 5204 that is rigid compared to the metal plating material 1504 used for the chip of FIG. 51. Thus, by making the two chips into one under suitable conditions, the post and through connections 5206 are formed, so that the drive and control circuit diagram 5202 and the laser 5104 on the electronic chip 5200 are electrically connected.

53 through 71 illustrate simplified variations of the basic contact formation and engagement approach. For the sake of simplicity and clarity, this approach is pre-processed (i.e., to include device and associated contacts and traces), but a pair of conventional ones that have not yet been cut into cubes with individual chips. It is shown in relation to the chip of. As shown, the chip shown in item “a) in each figure is a daughter chip, and then to be combined into the mother chip shown in item“ b) in each figure. It has a contact rerouted from one IC pad to another. One thing to note is that while such treatments are shown to occur in parallel, it should be understood that this is for understanding only. In practice, one process may be performed before another process, and these processes may be overlapped to some extent, or may be performed simultaneously.

First, the daughter wafer shown in FIG. 53A and the mother wafer shown in FIG. 53B will be described. Chips are sufficiently formed on each of these wafers, and a plurality of elements (not shown) are formed on each chip. In view of the state of the art, the same approach can be used for contacts with significantly smaller pitches on the order of 2 microns to 7 microns, however, as shown, the contacts 5302 and 5304 on the daughter wafer are 25 microns to 50 microns. It is formed with a pitch between microns. For ease of illustration and understanding, the contacts 5308 and 5308 on the mother wafer are shown to have a larger pitch than the contacts 5302 and 5304 of the daughter wafer. These contacts 5302, 5304, 5306, 5308 are conventional aluminum IC pads accessible through chip cover glasses 5310, 5312.

Next, dielectric layers 5402 and 5404 are deposited thickly on the chip (FIGS. 54A and 54B). Then, through the photolithography patterning process, the area above the contact is opened upward so that access can be made through this open area (FIGS. 55A and 55B).

Subsequently, etching is done through the dielectric, allowing access to the IC contact pads (FIGS. 56A and 56B). Thereafter, the photolith is peeled off (Figs. 57A and 57B).

Optionally, the thick dielectric layers 5402 and 5404 as described above may be thick photoresist layers (FIGS. 54A and 54B). In this case, thick layers 5402 and 5404 are removed by stripping the photoresist (FIGS. 57A and 57B).

Next, a seed layer is deposited on the wafer to facilitate subsequent plating processes (FIGS. 58A and 58B).

Thereafter, a dielectric layer is coated (FIGS. 59A and 59B), and a photolithography patterning process is used to define and control where the plating is to be made (FIGS. 60A and 60B).

Next, the wafer is plated until there is a predetermined amount of metal (Figs. 61A and 61B).

The dielectric is then removed, leaving a "standoff" or protruding contact (FIGS. 62A and 62B).

In general, the mother wafer and the daughter wafer may have an insulator. The purpose of the rigid structure on the daughter wafer is to provide an insulator so that the entire contact can accommodate the non-planarity of the two chips so that the contact can be formed quickly while in some cases the contact may not be needed. The purpose of the rigid structure on the mother wafer is to serve as a post and penetrable into the flexible material on the daughter wafer. In addition, since the isolator can be used to allow for a height difference between the top IC cover glass and the IC pad, some contacts may be disposed above the glass and the remaining contacts may be disposed above the pad.

Returning back to the process flow diagram, an additional etching process is performed to remove the unwanted seed layer (FIGS. 63A and 63B). As shown in FIG. 63A, the rerouting of the original contact is completed by leaving the seed layer material on the daughter wafer between one of the contacts and the new insulator / contact. Optionally, additional or alternative reroute layers may be disposed prior to or after completing the process. In addition, it may be desirable to plate a rerouted layer of a region thicker than other regions prior to performing an etching process to remove the seed layer.

Next, a barrier layer is coated on the contacts on the daughter wafer (FIG. 64A). In this case, the barrier layer is made of nickel and prevents the diffusion of metal into the IC pads 5302, 5304, 5306, 5308, or the individual chips as the metal penetrates under the cover glass 5310, 5312 of the chip. It serves to prevent it from being damaged. Optionally, cap layers 6402 and 6404 are placed on top of the barrier layer to prevent unwanted diffusion during the joining process, particularly when used in tack and fuse joining processes involving post and through contacts. Is deposited, in which case the cap layer is made of gold. The cap layer is also coated on the mother wafer (FIG. 64). At this point, the rigid contact on the mother wafer is complete.

Again, dielectric 6502 is coated on the daughter wafer (FIG. 65A). Further, through the photolithographic patterning process, regions 6602 and 6604 above the insulator contacts 6660 and 6608 are opened upward (FIG. 66A).

Thereafter, flexible contacts 6702 and 6704 are built on the insulator (FIG. 67A), and the dielectric is removed, leaving the fully formed flexible contact (FIG. 68B).

The daughter wafer is then flipped and aligned with the mother wafer, and through a photolithography patterning process, the area above the contact is opened upwards to allow access therethrough.

The two chips are then formed into one chip under pressure, so that the rigid contacts penetrate the flexible contacts (FIG. 70).

Finally, the two chips are permanently attached to each other via the melting phase (FIG. 71). One thing to note is that as a result of this process, the two chips are spaced at a distance of less than 10 microns, usually less than 5 microns, measured between the top of the rigid post and the top of the contact to which the post is connected on the other wafer. Is the point. If the wafer is perfectly flat according to its use, this distance will be the distance between the two wafers. However, if the wafer is not perfectly flat, the distance may be longer or shorter due to the geometry of the wafer.

72-87 show a simplified process of a variant for making contacts on the daughter wafer (FIG. 72A) and the mother wafer (FIG. 72B) and then joining the two chips together. As with the above-described example, description will be given with respect to the two wafers. As shown in Figs. 72A and 72B, the cover glass openings above the contact pads for the IC have a size between about 8 microns and 14 microns. Of course, the size of these openings may be on the order of 4 microns, and in some cases may be as small as 1 micron or less. Using one or more of the processes described herein, it is advantageous that the treatment of such relatively small openings can be made quickly at the same rate as the treatment of relatively large openings.

Also, as shown, the spacing of the pads on the daughter wafer (FIG. 72A) is typically formed with a pitch of 25 microns to 50 microns. However, likewise, the approach described herein can be readily used with a contact with a pitch of nominally 7 microns and can also be used with a contact with a pitch of 2 microns or less.

This modification proceeds as follows. First, a dielectric is coated thickly on the wafer (Figure 73). Thereafter, a photolithography patterning process is performed to allow the area above the contact to open upward to allow access through it (FIG. 74). The dielectric is then etched away to remove the contacts above (FIG. 75A), the photoless is stripped from the mother wafer (FIG. 76B), and a new reroute path is formed (FIG. 77).

 The exposed areas above the contact and reroute paths on the daughter wafer are metal plated with the barrier layer (FIG. 78A) and the seed layer is coated on the mother layer (FIG. 78B). Optionally, a barrier layer is coated on the mother wafer to protect the associated IC pads (not shown).

Thereafter, the photoless is peeled off from the daughter wafer (Fig. 79A). A new photolithography patterning process is performed to define the area where the contact is to be established (FIG. 80).

An appropriate material is deposited to create a soft contact on the daughter wafer. In this case, the suitable material is a gold-tin (Au / Sn) alloy in which the separation layer of tin (Sn) is topping and subsequently the layer of gold (Au) is topping. Then, by plating the exposed seed layer with copper, a rigid contact is formed on the mother wafer (FIG. 81B).

Thereafter, the photoless is peeled off from the daughter wafer and the mother wafer.

The remaining unwanted exposed seed layer is then removed from the mother wafer (FIG. 83).

Finally, a cap (optionally after the barrier layer is first formed) is coated on the mother wafer contact (oxide cap) to prevent oxidation (FIG. 84B).

According to the above modifications, the wafers are then aligned (FIG. 85) to one, then tacked (FIG. 86), and at some points thereafter also melted (FIG. 87).

It will be appreciated that, as outlined above, several variants have been outlined in a somewhat superficial manner, and that there may be additional variations that include more details of the various steps of the process described above. However, it is to be understood that these details are equally applicable to the foregoing modifications and other variations.

88-91 and 95-102 are briefly shown in a manner in which two additional variations of the approach for forming a rigid post on the backside of the daughter wafer are parallel. Here, it is appropriate to use "daughter" as a reference term, because the aluminum IC pads form a flexible contact and the back contact is "mother-type" but the rigidity on the other "mother" wafer Because it is connected to the post.

Moreover, although some variations are shown in a parallel manner, the processing processes described herein do not necessarily have to be performed in parallel, and these processes are performed on different wafers at different times or on the same wafer. Other variations are also possible.

This example begins with the wafers 8800 and 8802 shown in FIGS. 88A and 88B, respectively, and includes a first example as a preparatory operation for a portion where contact reroute, ie, vias, are not aligned with a pad on the wafer surface. 88A to 99A and a second example (FIGS. 88B to 99B) in which the via is aligned with the pad due to no rerouting process of the contact. In addition, by allowing the widths of the two vias to be generated to differ from one another, the widths of the vias may differ from the widths of the pads on the chip while illustrating the fact that different widths of vias can be used for a single wafer or chip. (Ie, the vias may be formed the same width as the pads, or may be formed wider or narrower than the width of the pads). To reiterate, it is noted that the components shown in the figures are not drawn to scale and need not be formed in precise portions thereof.

First, dielectric layers 8902 and 8904 are thickly coated on wafers 8800 and 8802. In this case, a silicon wafer having aluminum IC pad contacts 8904 and 8806 is used as the wafer (Figs. 89A and 89B). This thick dielectric layer serves to protect the chip, and serves as a blocking area in subsequent processing steps if the top surface becomes thin after the electroplating process. One thing to note is that in a subsequent step, a) the vias are not filled through electroplating, or b) the via metal filling process is not during the thinning process (ie, etching process or photolithography liftoff process). If the via is filled in a manner that allows for the removal of excess deposition material, this step can be done arbitrarily. Suitable materials for the deposition of thick dielectrics include, but are not limited to, for example, TEOS, oxides, nitrides, spin-on glasses, polyimides, BCB, other polymers or epoxies, thick photoresist layers, and the like. (If photosensitive polyimide or thick photoresist is used, in some variations, no separate photoresist deposition step is required in subsequent steps).

Next, a photoless layer is coated and patterned to prevent unwanted portions of the wafer from being etched (FIG. 90). This step is to define the location of the via to be created later.

Thereafter, etching of the wafer is performed through the dielectric (FIG. 91), and also the semiconductor and the substrate are etched, so that in the case of rerouting, vias 9102 are created in the wafer at the location where the rerouted contact is to be formed ( 91A, vias 9104 are typically formed in the wafer through the dielectric and aluminum IC pad contacts 8906 (FIG. 91B). Here, it should be noted that the desired depth is such that it can tolerate the exposure of the " post " formed through the thinning process of the wafer backside, as evidenced by the figures below. Typically, this depth is about 75 microns. Forming vias of this thickness may not be indispensable, but assuming that thousands or even millions of contacts are formed per square centimeter, by forming at such depths, they do not require a carrier wafer. It is possible to allow the entire daughter wafer to be processed in a wafer-scale fashion with good yields during subsequent processing steps. Optionally, vias may be formed in all directions through the wafer. In such a wafer through variant, the thinning and etching steps as described below on the backside of the wafer may not be necessary to expose the metal inside the via. Also, although the vias in this example are shown as single conductors, the same approach can be applied to coaxial or triple coaxial conductors in a manner that directly incorporates these production steps into the process.

At this point, it is necessary to highlight certain attributes and advantages obtained through the use of the illustrated process in certain embodiments. The attributes and advantages caused by this approach include the fact that etching and generation of vias can be made prior to the bonding (between chip to chip, between chip and wafer, or between wafer and wafer) steps. In other words, it is easily performed before connecting the chip, die or wafer to other elements. Moreover, this approach allows etching the vias from the device (ie, active) side of the pre-formed usable electronic chip. This approach can be used virtually anywhere on the chip where no schematic is directly formed in the invisible etch path. Thus, vias formed using this approach may or may not be aligned with the pad as needed. In addition, by forming vias on the pads and / or in some cases by forming the vias considerably smaller than the pads, in particular in the area of the chip with little or no circuitry, the " real state " losses can be minimized.

In connection with the formation of such vias, in some cases it may be desirable to give the vias an inclination so that subsequent deposition material can be properly coated on the sidewalls. In this case, the inclination may be set to a normal nominal inclination of approximately 88 degrees from the direction perpendicular to the vertical axis of the via (ie, the width of the via decreases slightly as the depth increases). A cross-sectional photograph showing an example of such an inclined via is shown in FIG. 92.

Typically, vias with a depth of at least 75 microns and a width of at least 5 microns are used. For the vias shown in FIG. 92, they are 20 microns in diameter and about 150 microns in depth. FIG. 93 is a photograph showing an example of a via (already filled) having a depth of 100 microns and a diameter of 20 microns. Widths as small as 0.1 microns are also possible, in which case you can make the depth shallower (eg, only 5 microns deep). However, the use of widths smaller than 0.1 micron may degrade the integrity of the final joint to be formed. Similarly, when using a depth less than 5 microns, it may be necessary to thin the wafer to the extent that the schematic (if any) of the wafer base may be damaged. Currently, in order to achieve sufficient production yields using ideal commercial equipment, depths in the range of 75 microns to 150 microns and widths in the range of 5 microns to 20 microns are commonly used. Of course, in certain applications, depths and widths outside this range are possible. For example, vias may be formed to a depth of 300 microns, and in some cases may be formed to fully penetrate the wafer. Of course, current commercial equipment does not have sufficient robustness to allow acceptable yields at such high value depth conditions, including the number and density planned for large commercial manufacturing purposes. However, advances in such equipment may reduce or eliminate such limitations over time, resulting in minor variations in depth, number, and density as defined in the approach without modification of the approach as described above. You can expect.

Optionally, the bottom of the via may be formed with dots. This form of formation is the method used to achieve strong rigid posts, good penetration of the rigid material into the soft material, and strong final contact (contact to maximize the surface contact force between the rigid material and the soft material). To accomplish this approach, the rigid posts are pyramidal (or pyramidal on top of the cylinder), ie the bases of the posts have the same width as the contacts below them (structures that maximize the bond strength of the posts and contacts). The upper side of is tapered to a considerably smaller size than the contact, so an approach has been used that allows an alignment relative size factor to be achieved. The advantage of this variant is that the pointed posts can be formed so that, when used for posts and through connections, a penetration similar to that of a pyramidal profile formed after the rigid posts can be achieved. FIG. 94 is a photograph showing a cross section of a chip having a pointed via formed therein.

The photoresist is then stripped off (FIG. 95) and coated on the exposed via surface (not shown) with a dielectric or insulating layer to prevent electrical shorts between any circuitry of the metal inside the via and the semiconductor. The thickness of this layer is typically between about 2000 angstroms and 1 micron. However, for certain applications, a thicker layer may be formed to balance the coefficient of thermal expansion or reduce the capacitance of the via. Examples of insulating materials that can be used include TEOS (oxides), other oxides, nitrides, polymers, CVD diamonds, and the like.

A metal barrier layer is then deposited on the dielectric (Figure 96). The barrier layer acts to prevent metal from moving to the insulator and the semiconductor. Although all barrier materials described herein are suitable at this stage, the illustrated barrier is titanium-tungsten (TiW) for illustration purposes.

Next, in certain variants, when the metal is plated, a plating “seed” layer is coated (FIG. 97). This seed layer is used as the base for the electroplating of the vias. Copper seed layers are preferred, because these copper seed layers exhibit excellent electrical and thermal conductor properties and are used dominantly in industry today and are very easy to work on standard semiconductor and packaging lines. However, any of the other materials as described herein with respect to the rigid material and / or seed layer for the rigid material may be used. If the via is filled by a method other than electroplating, this seed layer may only cover the via itself, not the wider portion of the wafer, or may not exist at all. For example, when vias are filled by CVD or evaporation, no seed layer is needed.

Barrier and seed layers are typically deposited by sputtering or physical vapor deposition (PVD), but electroplating may be used, in some embodiments, electroplating provides an important advantage over sputtering or PVD.

Vias are filled with metal or other conductors to form electrical conduits through the wafer (FIG. 98). Usually, the filling material is copper for plating approach. However, a material comprising any of the other materials described herein may be used as a suitable rigid or soft material. It should be noted that vias do not have to be fully filled with conductors if a simple electrical connection is required and good thermal conductivity or low electrical resistance is not required. In this case, the rest of the vias can optionally be filled with other materials, such as oxides or epoxies. The entire via must normally be filled with some type of material, because if air is trapped in the voids in the via while the chip is packaged and sealed, the air will expand and compress through temperature cycling during operation. This is because a defect can be caused. When fully filled with metal, the resistance is at its lowest and the thermal conduction contact is at its maximum. In addition, when larger diameter vias fully filled with metal are used, this metal may contribute to heat conduction through the wafer.

As shown in FIG. 98, the vias are filled by plating the seed layer using an electroplating process. Optionally, when the plating process is complete and the voids remain in the interior center of the plating material, the voids may be filled with filler material, such as oxides, additional metals, solder, or other materials suitable for the application.

Advantageously, when vias are filled with the same material as the rigid material for the mother wafer or with the same material as the soft material for the daughter wafer, there may be an advantage with respect to lamination. Optionally, the vias may be filled with the same material as the soft material if the mating contacts on the chip to which the vias are attached comprise a rigid material thereon.

As shown in FIG. 98B, it should be noted that when the beads are aligned with the pad, filling the via with a conductor essentially allows the via to contact the pad.

When a particular wafer is connected to another wafer, as expected in most embodiments, the configuration of the barrier and via filling material of the daughter wafer will follow the same guidelines as the rigid material for the barrier and mother wafer, so that the daughter chip When bonded to the mother wafer, it is important that the daughter wafer behaves in the same way as the mother wafer.

Back to the process flow diagram, as a result of the plating in the previous step, a large amount of conductor must be deposited on top of the wafer and then removed. This step can be accomplished through lapping, polishing, or chemical-mechanical processes (CMP). This thinning is performed up to the thick dielectric deposited in the first step. The actual thickness used for the coated dielectric as in the first step is chosen to give an error margin to this wrapping step. This step may be unnecessary if the conductor filling the via is not deposited by electroplating. As shown, a chemical-mechanical process (CMP) is then used to remove excess plating material and underlying seed layer up to the surface dielectric layer and to the extent that it slightly invades the surface dielectric layer (FIG. 99).

Next, the photolithography etching process is again used to help access the wafer from the top of the wafer by coating of the photoresist to the IC pad contacts 8904 and 8806 (FIG. 100), followed by etching the exposed dielectric 10002. (FIG. 101). If only the contact from the pad to the via itself is needed (FIG. 101B), and if no contact is needed between the same pad and the mother chip for the particular pad, that particular pad may precede this step (i.e. May remain covered by the photoresist). In a variant, a photolithography process may be performed such that at the same time as the seed layer is deposited (and functionally forming part of the seed layer) or during the plating or filling of the vias, connections to the IC contacts are formed. In such a variant, a photolithography step may be unnecessary.

Thereafter, the photoresist is stripped off and the wafer is cleaned, leaving the post completely formed inside the daughter wafer (FIG. 102).

At this point, it is assumed that the wafer is additionally prepared for bonding with other chips, dies, or other elements such as wafers (ie, this approach is between chips and dies, between chips and dies, chips and wafers). The same applies to all predeformations for bonding between die, between die and die, between die and chip, between die and wafer, and between wafer and wafer). This further treatment process is briefly shown in a parallel manner in FIGS. 103-125. This processing begins with the daughter wafer as shown in FIG. Also, for ease of understanding, a process performed on a wafer that serves as a “mother type” contact element is also shown.

This process takes place as follows. First, a dielectric layer is coated on the mother wafer except on the IC contact pads (FIG. 103B). This dielectric layer is already provided on the daughter wafer (FIGS. 102A and 102B).

Next, a barrier layer is deposited on the daughter wafer (FIG. 104A), some of which, in the case of rerouted contacts, ultimately become an electrical connection between the original IC contact and the preformed post. It is advantageous to use a barrier layer because the barrier layer prevents the soft material from interacting with the IC pad or the rigid or insulator metal afterwards.

As shown, a barrier material, such as Ni / Au, Ti / Pd / Au or Ti / Pt / Au, etc., is deposited on the daughter wafer through sputtering. In addition, such a barrier can generally be used as bump metal (UBM) or used in rerouting that does not require removal of the seed layer. This layer is typically formed using electroplating, optionally in combination with a sputtering and / or evaporation process or an electroplating process for forming the top layer.

In addition, as shown, a seed layer is deposited on the mother wafer using, for example, electroplating or deposition techniques (FIG. 104B). As shown, the mother wafer is formed by coating TiW + Cu and is used as the UBM and seed layer for electroplating a rigid contact on the mother wafer. When copper is used on top, copper electroplating and subsequent rigid post forming processes can be made easier. The UBM on the mother wafer may, in some embodiments, be used as a dual purpose of seed layer and rerouting for electroplating of rigid members, or may act as an RF barrier between wafers (patterning for which But not in the etching step).

Optionally and optionally, the barrier and seed layer may consist of the same components. In this case, a single material can function as both layers.

As shown in FIG. 104, a barrier is formed over the entire wafer. This allows subsequent electroplating steps to be performed. After completion of this electroplating, however, the seed layer and barrier must be removed in areas where no contact exists so that the various contacts do not remain together in an electrical short (unless specifically preferred for other reasons that are not suitable in this case). In other words, the barrier and seed layer act as electrical rerouting material of the points).

Subsequent materials may be formed by a process other than electroplating, for example sputtering or evaporation, after which the mother wafer step optionally comprises a patterning process using photolithography around the pad, a barrier metal deposition process, a subsequent metal Deposition processes, and lift-off processes. The net result of the barrier and the metal formed preferentially around the pad or where rerouting is needed is the same.

Thereafter, a lithography process is performed on the daughter wafer to expose the barrier material covering the original contact (FIG. 105A). In addition, as shown in the present case, the mother wafer is patterned using an undercut to provide any patterned contact, eg, in the form of a pointed pyramid, cone or mushroom (FIG. 105B). Optionally, the mother wafer may be patterned to form some other contact shape in order to increase the effective surface area of the contact or to form a contact having a smaller cross-section at a meaningful level than the corresponding soft contact to which the contact will ultimately be connected. . Through this patterning process, penetration force can be improved because the coating pressure is dispersed over a smaller area.

In this step (FIG. 105A, 105B), the area | region in which subsequent metal is arrange | positioned is defined. If subsequent metals are deposited by means other than electroplating, this step is performed prior to the deposition of the barrier and seed layers described above. Here, it is assumed that electroplating is used. It should be noted again that lithographic patterning may be made to allow subsequent electroplating and / or etching of the seed layer (or subsequent liftoff process if electroplating is not used) to define the rerouting layer.

The daughter wafer is then metal plated by depositing a suitable metal on top of the exposure barrier (FIG. 106). According to certain embodiments, one or more of the following subsequent layers may be formed on the daughter wafer. These subsequent layers include an insulator layer (if necessary) to handle the non-planarity of the wafer, a diffusion or soft layer (the area to be deformed or form a contact), and a cap or adhesive layer to assist the adhesion operation during the tack phase ( If necessary), and / or an oxidation barrier is included to prevent the adhesion / diffusion layer from oxidizing.

In addition, on the mother wafer, the voids generated by the lithography process are filled by plating (electro or electroless plating) the seed layer exposed by the lithography process (FIG. 106). According to certain embodiments, rigid materials used to form posts for use in posts and through connections may be added at this stage.

107 shows in greater detail one example of a fully plated pyramid contact for a mother wafer.

108 is an enlarged view of a portion of a variant of the mother wafer contact having a profile similar to that shown in FIG. 107. According to any of these modifications (modifications applicable to profiled and non-profiled contacts), some metal of semiconductor pad 10802 is etched before plating (metal plating) the metal for rigid posts, An undercut profile 10804 is formed at the edge of the pad 10802. Once the rigid material 10902 is built up (FIG. 109), some of the rigid material 10902 is used to fill the undercut 10804. This additional filler acts as an anchor for supporting the rigid contact structure during further processing or during stress during operation due to thermal cycling. As shown, the rigid material 10902 is nickel (Ni).

Upon completion of metal plating and / or plating, the photoless is peeled off to expose the contacts established on the daughter wafer and the mother wafer (FIG. 110). However, it should be noted that when the barrier for mother contact is electroplated, this step may optionally be performed prior to metal plating followed by stripping off the photoresist.

 A photolithography process is then used to remove unwanted barrier and seed material from the daughter wafer and mother wafer, respectively, while protecting the established contacts or posts (FIG. 111). Note that this step can also be used to define and / or reroute contacts. Moreover, if other metals are not electroplated, the order of these steps can be changed slightly, because a liftoff process for subsequent etching may be used.

However, the seed and barrier materials of this example are electroplated, so etching is used. Thus, unwanted seed and barrier materials are etched away (FIG. 112). In another optional variant, only a small amount of the barrier and seed material are etched away as needed to prevent undesirable short-circuit phenomena caused by a single contact, so that most of the surface of the wafer is barriered. And because it remains covered with the seed material, it can be used as an EMI shield to prevent noise or undesirable signal coupling between stacked chips, especially when the remaining barrier / block is attached to the ground plane.

Thereafter, the photoless is peeled off and removed (FIG. 113).

At this point, the daughter wafer contains functional rigid posts suitable for use in forming posts and through-fitting connections with other wafers.

However, as evidenced by the description herein, during the treatment of the mother wafer, a process of electroplating a ductile (relative to the material on the daughter wafer post) into the contact continues (FIG. 114B). One thing to note is that although this step is shown as an electroless plating step, an electroplating step may be used as a variant of this approach. In this variant, the above-mentioned part of the process takes place as part of the metal plating step or, optionally, between the stripping off of the photoless used in the metal plating step and the coating of the protective photoless as described above. It can be made as a plating operation. In either case, however, deposition of the barrier is important because the barrier prevents intermixing of the flexible and rigid materials and constrains the flexible material between the IC pad and the rigid material on the daughter wafer.

At this point, the mother wafer has a functional flexible post that is used to form posts and through-fitting connections with other wafers.

However, in this example, after the post is formed in the wafer, the third chip is supposed to be stacked on the upper side of the daughter wafer. Therefore, further processing of the daughter wafer is required, as described below.

First, the first side of the daughter wafer (i.e., device and contact bearing side) is protected by coating with a suitable removable protective material, thereby protecting the daughter wafer from contamination during subsequent thinning process (FIG. 115A). Such covers may consist only of simple photoresists or dielectrics, or rigid members such as glass plates or other semiconductor wafers (“carrier” wafers) attached to daughter wafers using photoresist, wax, polymers, epoxy, other adhesives, and the like. It may be made of. In some variations, very thick layers (eg, layers having a thickness of at least 50% of the thickness of the daughter wafer after the thinning process) are used. In other variations, rigid carrier wafers may be used. In either case, an extra strength reinforcement of the daughter wafer can be made through a very thick layer, allowing wafer handling without risk of fracture during thinning.

The backside of the daughter wafer is then thinned down so that the backside is exposed to the via fill material (eg, preformed posts). Such thinning is typically accomplished until the thickness of the daughter wafer is approximately 75 microns, given that the via depth is approximately 75 microns. If the vias extend deeper, the thinning process may be shorter. Depending on the particular application, the thinning process is performed until the posts extend over the backside of the wafer or in some applications until the posts are flush with the backside (FIG. 116A). However, if the bottom of the via is pointed, if the pointed portion is preferably pyramidal, conical or mushroom-like, then the thinning process at the point of completion of the process is sufficient to remove the pointed portion of the bottom in a meaningful amount. It is preferred that it is not performed.

In this case, because other posts and through connections are desired, an etching process is performed on the back side so that the posts extend above the back side (FIG. 117A). This etching step is necessary for two purposes. First, the etching process removes a portion of the substrate around the vias, allowing the vias to extend beyond the surface (thus allowing the beads to act in exactly the same way as rigid posts on the mother wafer). Second, the etching process cleans the surface of the contact, allowing for good adhesion of the metal in subsequent processes.

Of course, for daughter wafers without through-connections, thinning and etching processes may generally be unnecessary in view of other heights, but it is nevertheless desirable to carry out these processes.

In the case of variants using very thick layers or carriers on the front surface, when thinning is carried out, the finished thickness is likely to significantly exceed 75 microns. Indeed, according to this variant, the thinning results in a thickness reduction of approximately 10 microns. Moreover, if the carrier wafer is not removed after the tack and melt process, the thickness of the wafer can be thinned down to approximately 5 microns.

Note that, in a variant embodiment, the thinning step can be performed after the joining process between the mother wafer and the daughter wafer. In this variant, the process consists of electroless plating, tacking, melting, daughter wafer thinning of the mother contact, etching the backside of the daughter wafer until the contact extends over the backside, coating the barrier and cap to the backside contact, and the like. In this case, the front side protection treatment and the removal process of the protection portion are omitted if unnecessary.

The barrier and cap or cover layer is then deposited on the post (FIG. 118). This barrier layer and cover are important for the protection of the via material. The barrier layer (and barrier cover) performs exactly the same function as the barrier cover deposited on top of the rigid material of the barrier material and the "true" mother wafer. A soft material can be pinned between the barrier material on this new post and the subsequent second daughter wafer (ie, "daughter wafer 2"). As shown, the barrier and cap are deposited using an electroless plating process. In this example, 1 micron thick Ni and 0.3 micron thick Au are used. The advantage of using electroless plating is that it does not require a photolithography step on the backside of the wafer, thus making the process simpler while allowing the use of thinner wafers. This advantage is even more significant when wafers are thinned to more extreme limits and cost-effective during the via etch and via fill phases of the dielectric etch and via creation process. In addition, specific materials that can be used include any of the barrier materials as referenced herein.

In addition, this barrier does not have to be deposited by electroless plating. Instead, in some variations, electroplating may be used when the seed layer is deposited on the backside, plated and etched in a similar manner as described above. In other variations, patterning and evaporation or sputtering or other types of deposition processes may be used to coat these barrier layers. If it is necessary to perform additional steps on thin wafers, the approach of this variant provides several advantages, for example, through a lift-off process in the process flow of the deposited metal or in the electroplating process flow. Etching the layer may define a rerouting layer, barrier or ground plane on the backside of the wafer. Thereafter, the protective layer is removed from the front surface of the daughter wafer (Figure 119).

Optionally, if any material formed as a protective layer or adhesive for attaching the carrier wafer to the daughter wafer can withstand the temperature of the tack and dissolution process, this step may be postponed after the dissolution process is complete. This makes it possible to thinner the daughter wafer while allowing individual dies to be handled during the tack process without causing cracks or damage to the chip. In this scenario, the schematic of the daughter chip is directed upwards (ie, facing away from the mother chip) so that a soft material is placed on the mother chip. Of course, the mother / daughter practice is at its sole discretion and vice versa, and for certain well attachments or other variations, the soft material may be in the via itself and may even be added later. shall.

In another alternative variant, for example, if vias are not formed so as to stack a third chip on top but allow the chip to be combined with the upward facing circuitry rather than downward, or for example an optical element If is present on the daughter wafer and the upper carrier wafer can have built-in microlenses or other inactive elements, or if it is desired that the daughter and mother wafer are RF elements and the two electronic schematics are not immediately adjacent to each other, The step may be omitted entirely and the protective layer may remain permanent. In addition, it is usually necessary to configure the mother chip to have a soft material on the upper side.

At this point, the individual chips can be connected, assuming that the aforementioned contacts on the mother wafer and daughter wafer are paired into one. This connection process is described below.

First, the daughter wafer is flipped and individual contacts connected on the mother wafer and the daughter wafer are aligned with respect to each other (FIG. 120). This alignment step is used to align the mother wafer and the daughter wafer. This alignment should take into account ± tolerances around the size of the pads. Due to the exaggerated soft contact, this alignment tolerance can be set somewhat larger. In general, alignment occurs in such a way that the entire upper side of the rigid contact hits the soft contact at some point. By way of example, if a flexible contact is 15 square microns wide on one side and the top of the rigid contact is 5 square microns wide on one side, the edge of the rigid contact is 5 from the edge of the soft contact if it is perfectly centered. Micron difference, and the alignment accuracy is ± 5 microns.

The contacts are then brought together under pressure to form posts and through connections (FIG. 121).

One important advantage of this approach to lamination is that the rigid material penetrates into the soft material. Thus, a strong bonding can be achieved between the two wafers because the surface area between the two contacts is larger than the size of the individual contacts themselves. Moreover, this bonding is stronger because the errors required to pull the two parts apart from each other require a thin layer separation of the horizontal plane of the post and a shear error of the vertical plane of the post. Note that the latter is a less likely form of error, and the risk of overall error is less likely than when alone.

In fact, the amount of protrusion is also important. Typically, projections of at least 1/2 micron are preferred. In some embodiments, the amount of protrusion may be small, but at such a low level of protrusion, the strength is greatly reduced. Indeed, for soft materials having a total height of 8 microns, it has been determined that the rigid material typically extends in the range of 2-3 microns into the soft material. If the soft material is 10 microns, the rigid material extends into the soft material, typically 5 microns in length. According to the general "law of thumb", it can penetrate at least 10% of the thickness of a soft contact, but it can penetrate up to 90% or less through a soft contact.

Another important advantage is the penetration of the post, which allows a significant level of nonplanarity of the daughter chip and the mother chip over the pitch of the contact. For example, for a contact that is 12 microns wide and 20 microns in pitch, the height of the ductile material may be quite high, for example, the height may rise to a level that matches the height and pitch. Similarly, the deviation of planarity from contact to contact can be as large as the thickness of the soft material. For example, if the post is 5 microns in height and the soft material is 8 microns in height, the difference in planarity between the contact and the contact may be as high as 8 microns. In this case, some of the posts will penetrate the ductile material as a whole and others will penetrate less.

Returning back to the process flow diagram, the tack phase of the tack and dissolution process may be performed following or concurrently with the penetration of the rigid contact into the flexible contact. As shown in FIG. 121, the two processes occur simultaneously. Electrical connections between two wafers are formed during the tack phase of the process. Advantageously, no intermediate epoxy or other material is needed to hold the chips together and can act as a barrier between the connections.

Optionally, for example, if potential reprocessing is not included as part of the process, an underfill may be inserted between the two chips to fill the voids between the two chips prior to the tack phase and also this underfill The material is not adversely affected by the temperature used in the tack or melting process.

At this point, the mother wafer and daughter wafer can be connected and tested (in some cases one is replaced if there is a problem).

Once the permanent connection between the two chips is determined to be necessary, the dissolution phase of the tack and dissolution process is performed (FIG. 122) to form connection pairs (e.g., coupled units) 12202, 12204. During the dissolution process, the mother diffusion / cap, daughter oxide cap, and daughter soft material are all diffused into one to form the final composition of the entire contact.

Optionally, underfill can be inserted between the chips prior to the fusing process, if not previously done. This assumes that the temperature is independent or that the dissolution process is followed. The advantage of using such an underfill is that the underfill can reduce the air trapped between the two chips, thereby reducing damage to the chips or connections due to temperature cycling (because the tack and melting process forms a hermetic seal) .

Once the mother wafer enters the tack process (i.e., in the process between the die and the wafer, the alignment and tack processes are repeated at each good position throughout the mother wafer without processing at known bad mother die positions, In the wafer-to-wafer process, these two wafers are tackled together as a whole and the location of the defective chip is recorded for future removal operations if any test is performed). All daughter chips are permanently attached. This can be done at a temperature significantly higher than the tack phase. Moreover, the same time is taken for each chip, and the process is performed on the wafer one at a time, resulting in a fairly homogeneous connection across each chip.

The temperature of the dissolution phase is usually, for example, 320 ° C. to 400 ° C., depending on the particular material involved.

Advantageously, by separating the tack process from the dissolution process, it is possible to prevent the slowing down of the equipment for performing the tack process by heating or cooling each part. By performing this process in a controlled manner at the wafer level, all contacts can have very similar final compositions.

During the tack phase, the dissolution phase or the tack and dissolution phase, an inert or reducing environment can be used to reduce or remove oxides on the material surface and to lower the temperature or pressure required in each step. Typically these materials are nitrogen, argon, other inert gases or foaming-gases or other environments containing formic acid or hydrogen or other reducing gases.

As described above, the process is not completed because the third chip is connected to this newly formed unit. By connecting the mother chip and daughter chip, the unit can be connected to another chip. Thus, as shown in FIG. 123, the second daughter wafer is in contact with and aligned with the appropriate contacts on the units 12202, 12204.

Advantageously, due to previous processing steps, the exposed side of the via on the upper side of the first daughter chip has the same composition as the upper side of the original rigid contact. Thus, for subsequent "daughter" wafers, the bonding process takes place in the same manner as the two first wafers (ie, aligned, penetrated, tacked (optionally tested) and dissolved). The soft material is secured between the individual barrier layers and the posts on the vias penetrating into the soft material. An important advantage of this process is that the via and base bonding processes are thus set to operate in the same material system and in the same process flow, facilitating repetitive lamination beyond conventional stacked chip pairs.

As a result, the mother wafer is provided with a set of chips and several other sets of chips (daughter wafer 2) and the like, and in some cases, a tack, tack, tack, melt, Using an ordered approach, the process can be done in the same manner as each layer if necessary.

Thus, a second tack phase is performed on the second daughter wafer, bonded to the second daughter wafer unit, and once completed, this newly formed larger unit is further optionally tested and if the second daughter chip is bad, This bad chip is removed and replaced (FIG. 124).

Finally, if a permanent connection between the second daughter wafer and the unit is required, the dissolution phase of the tack and dissolution process is performed again to form new, larger coupling units 12502 and 12504.

After this step, the process is repeated over and over so that a plurality of additional chips can be incorporated into, for example, "daughter wafer 2" or other chips present on the wafer (not shown). Because electrical connections are formed during each tack process, each chip is aligned only to the chip just below it, so that the accumulation of alignment errors as in other stacking techniques where all chips must first be stacked before attempting through-connection There is no additional advantage achieved.

Moreover, to the extent necessary, testing of each larger combination unit can be performed subsequent to each successive layer (and reprocessing can be carried out if necessary). In addition, this provides distinct advantages and very effective cost savings and increased yields, since if the dies are stacked in multiple layers, conventional techniques require that the entire building unit be completed before electrical testing is done. Because it will. Thus, a typical part can only be tested after an expensive unit has been created, and if bad and reprocessing is not possible, only the choice remains to discard the expensive unit as a whole. In addition, according to the conventional technique, for example, if there was an error on the first row of chips, the risk of damage to the unit during the construction of the component is high, or the risk of disposal of the component is significantly increased.

In contrast, using one of the approaches described herein, multi-stack shapes can be created without great risk. In addition, according to a specific case, as described above, the approach may be repeated as many times as necessary in the order of alignment, tack, dissolution, alignment, tack, dissolution. Under conditions where the tack process is sufficiently high, for example 500 or more contacts, the process may optionally be performed as many times as necessary in the order of alignment, tack, alignment, tack, and all chips stacked in a vertical direction ( And dissolution is only performed after good testing if the option is used. Such a second approach may be more effective when the different number of chips are stacked at different positions.

Note that at this point, using the post and through connections and the tack and melt processes, subsequent processes may be performed to connect the second wafer (and subsequent wafers) to the unit without adversely affecting previously formed internal unit connections. It is beneficial to do In fact, by using the approach of tacking, melting, tacking and melting (depending on whether an additional thinning process has been carried out), it has been surprising to find that successive melting steps actually have the effect of lowering the resistance of the previous connection. This is an important issue in view of the common common sense that subsequent dissolution tends to weaken or degrade previously formed connections (this is especially true for "well" connections as described below). Turns out).

126 to 139 show further variations starting with the daughter wafer to be rerouted and the corresponding mother wafer of FIG. 103 in an abbreviated form without exaggeration. However, the daughter wafer of this example is processed as shown briefly in FIGS. 77A-104, but this time includes the process of creating a post to facilitate this when the second daughter wafer is stacked up as in the previous example. do.

The process starts with the wafer of FIG. 104 in such a way that the area for rerouting on the daughter wafer (FIG. 126) is defined via a photolithography process. The barrier layer is then coated to reroute the contacts on the daughter wafer, and the seed layer is coated on the mother wafer (FIG. 127). The photoless is then peeled off and removed (FIG. 128), and a new photolithography patterning process is used to protect all areas on the original contact (FIG. 129). The contacts are then metal plated (FIG. 130), where the daughter layer comprises a gold-tin (Au / Sn) alloy doped with a separate layer of Sn and a cap of gold, with the mother wafer having copper contact Plated with. Repeatedly, the photoless is stripped off (FIG. 131) and the unwanted seed layer is removed by etching (FIG. 132). Finally, a cap of Ni / Au is coated onto the mother wafer contact via electroless plating (FIG. 133).

The wafers are then aligned with respect to each other (FIG. 134). The contacts can then be processed to form one post and through connection, and the tack, selective testing, and possible dissolution processes can be performed to produce a combined unit of combination (both of which are described and illustrated above). In order to avoid duplicate explanation, nothing will be shown).

In this example, a second daughter wafer is also added on the upper side of the daughter wafer, and this additional step will be described later. First, the backside of the daughter wafer of the combination unit is thinned to expose the previously formed backside contact (FIG. 135). Thereafter, the substrate is etched such that the posts protrude above the substrate surface (FIG. 136).

This is followed by the addition of other subsequent joining steps, including so-called thinning, while the process may be stopped here if sufficient for the particular application. The advantage of doing this is that there is no need to add a lithography patterning process or material deposition process that requires labor for additional contact and is a major source of risk of yield loss. Optionally, a cap may be added (ie additional processing is required) where oxidation may be a problem due to time delays for the connection operation to other elements, materials, or other factors.

137 is a photograph illustrating an example of a contact after completion of the steps illustrated in FIGS. 135 and 136. 137 clearly shows the post 13702, barrier 13704, and substrate 13706.

If oxidation is suspected to be a problem, the cap is coated on the non-risk portion of the post (FIG. 138), completing the back contact forming process.

As with the first daughter wafer, the next daughter wafer is aligned over this back contact, which is the position where the post and through connections between the two can be formed with the tack process or the like, or following the tack process (FIG. 139).

In general, there are a number of materials suitable for use as barriers. Such materials include but are not limited to Ni, Cr, Ti / Pt, Ti / Pd / Pt, Ti / Pt / Au, Ti / Pd, Ti / Pd / Au, Ti / Pd / Pt / Au, TiW , Ta, TaN, Ti, TaW, and W.

Suitable materials for the seed layer include, but are not limited to, Ni, Cu, Al, Au, W, Pd, and Pt.

Suitable materials of the variant are, but are not limited to, Ta / Cu, TaN / Cu, Ni / Au, Ni / Cu, Ti / Pd / Au, Ti / Pd / Cu, chromium, in a flat manner (eg Conductive epoxies, or mixtures thereof, which may be deposited through evaporation or spraying).

However, it should be noted that not all barriers on individual chips or paired chips should be formed of the exact same material.

In general, when a barrier is used, the material should have the following properties.

 i) be compatible with certain pad materials (usually made of aluminum, copper and gold);

ii) If small (<15 μm) IC pads and large (> 50 μm) IC pads coexist on the wafer, they should be selected so that they can be placed in good yield on these pads of the wafer.

iii) If the lower bump metal is also used as a rigid material or acts as an insulator, it should be able to form several microns (> 3 μm) while satisfying the above conditions.

In addition, the barrier material is preferably compatible with the deposition material on top of the IC pad and on the top cover glass / passivation layer of the chip.

The use of a barrier may also provide one or more of the following advantages.

i) Allowing for high yields, while increasing the reliability of the mating contacts.

ii) When deposited on the pad top and the top cover glass / passivation layer of the chip, the barrier layer can then be used as follows. In other words,

1) as a signal reroute material

2) a material for preventing crosstalk between chips, as an electrical barrier between two chips, and / or

3) can be used as a seed layer for subsequent steps that can be performed by electroplating (eg, rigid post formation and coating of soft materials).

iii) The shelf life of the daughter material is increased because the barrier acts as a cap to prevent or delay oxidation.

iv) pre-patterned to be used as a rerouting or barrier film.

The materials of the foregoing modifications may provide advantages in some embodiments for the following reasons.

i) The barrier performance of Ta and TaN is believed to be superior to that of TiW.

ii) Nickel-based process simplifies the process by allowing UBM and subsequent rigid materials to become one and the same.

iii) In the case of the modification in which the copper does not remain exposed, the shelf life becomes longer, thereby improving compatibility with a predetermined manufacturing process.

iv) if a subsequent electroplating step is not required (e.g., for the deposition of a rigid member or insulator member on the daughter wafer), either of these materials can be accurately patterned over the pad and rerouting or blocking regions It is possible to eliminate the need for a step for forming subsequent seed layers and an etching step for defining these regions.

With regard to the use of the barrier layer, in many variations it is important to ensure that: 1) it is a suitable metal on the premise of the interaction, and 2) the same metal is in compliance with the norm after the final composition. 3) other metals used in the stack (e.g., rigid and insulators) must not interact to cause contamination of the metal, and 4) the barrier is a package for the tack part of the process. Soldering conditions (e.g., Pb / Sn at appropriate temperatures or some lead-free solder that typically operates around about 240 ° C to about 270 ° C) and processes that can typically be between about 300 ° C and about 350 ° C Multiple hot cycles at temperatures above this temperature up to the temperature for the melted part should be allowed. The barrier maintains the integrity of the attachment material by preventing the metals that must be kept separate for better integrity of the bond.

This is illustrated with reference to FIG. 140 by way of example. 140, the daughter wafer contact 1402 and mother wafer contact 1404 just before the tack phase are shown. As shown, the barrier layer 14006 of the daughter wafer contact is made of Ti / Pd / Au, and the barrier layer 14008 of the mother wafer contact is made of Ni. The "stiff" material 14010 on the mother wafer is copper and the soft material 14012 on the daughter wafer is Au / Sn. In addition, the caps 1414 and 14016 on each wafer are formed of gold, and since the two metals of the initial contact are made of the same material, the tack process can be easily made while preventing oxidation of the individual materials on each side. Used for dual purposes. In practice, however, it should be noted that the caps 1140 and 14016 typically enclose completely other materials, although in most variations only the top side is shown for simplicity of illustration. 141 shows the same contact briefly after the fusion process is completed. After the final metal composition is obtained, the two gold cap layers are Au / Sn while nickel and Ti / Pd / Au act as barriers to prevent Au / Sn from mixing with the pad and copper on top of Ti / Pd / Au. It is mixed with the Sn layer to form Au / Sn alloy 14102. Thus, the Au / Sn 14102, which has undergone a dissolution process, is “captured” between these two barrier layers 1406, 14008 to maintain the composition of Au / Sn uniformly and consistently over a number of subsequent high temperature steps. do.

In contrast, for example, in the absence of nickel barrier layer 1406, Au / Sn 14102 is in direct contact with a very thick copper layer 1410 (in a practical embodiment the thickness of the copper layer is Au / Sn More than 60% of the thickness). As a result, Sn diffuses into copper under a predetermined temperature, and the alloy thus obtained starts to change its properties significantly. For example, the melting point of copper is 1084 ° C. As Sn initially diffuses into copper, the upper side of the rigid post becomes a mixture rich in Sn content, which has a significantly lower melting point (for example, a mixture with 97% Sn and 3% Cu has a melting point of around 230 ° C). Have). As Sn diffuses further into copper, it has a lower melting point than Au / Sn, and the copper posts become rigid members in the tack and melting process. Equally important, copper 14010 filters Sn out of Au / Sn 14102 and increases the temperature to make it ductile. Thus, rigid members that are becoming more and more soft are allowed to penetrate into the rigid members that are becoming more and more rigid. This affects contact strength and uniformity, which ultimately affects the density of available contact spacing. Moreover, these effects accumulate over time. Depending on the length of time the fusion process occurs, the composition and performance of the contact can vary significantly. This is the case if the contact has gone through multiple melt cycles, for example if the chips are stacked in multiple layers in the vertical direction. The bottom chip of the stack exhibits significantly different mismatch behavior compared to the later dissolved chips of the stack. By using such a barrier metal, Au / Sn is greatly limited, and thus it is possible to maintain the same composition and properties through a plurality of dissolution cycles. Even in the case of using a barrier in this way, interdiffusion can occur between, for example, Au / Sn and Ni, but its diffusion rate is significantly slower than in the case of only Cu, for example, at an ideal level. It should be noted that chips of, for example, 100 chips or less are negligible. Thus, for any embodiment, no matter what material is used, the barrier should normally be a component of the final interconnect alloy to prevent or minimize adversely affecting interdiffusion.

In a typical post and through approach, although the two mating contacts are shown to be fairly flat, this is not a desirable configuration or a requirement for all applications. Since the quality (or defect) of the electrical connection between the two points directly affects the resistance of the connection and the bad connection lowers the yield, it is desirable to minimize the bad connection. Advantageously, the yield can be increased by allowing the post and through approach to be immediately adapted to reduce the risk of high resistance connections being created (without increasing the "footprint" of the contact). This approach includes creating a pattern or profile on the through or soft contact to improve the penetration efficiency while increasing the contact surface area.

In the case of making the soft contact larger than the rigid contact by making the size relatively, if the soft contact is located directly on the IC contact pad, the soft contact can be nearly automatically profiled. By patterning the soft contact metal in an area larger than the opening for the IC contact pad where the contact is formed thereon, a natural depression is formed near the center of the contact due to the relative height difference between the cover glass on the IC pad and the IC pad itself. 142 shows such a profiled soft contact 14202. As shown, the flexible contact 14202 is formed wider than the IC contact pad I4204. As a result, the rise of the glass 14206 relative to the contact pad 14204 naturally results in the formation of the depression 14208 in the malleable contact 14202. [ Advantageously, these natural depressions 14208 make the soft contacts 14202 more suitable for receiving rigid contacts 14210 and even when the rigid contacts 14210 are fairly close to the size of the depressions, respectively. Natural shape aids alignment.

Profiling a rigid contact reduces the initial contact area, effectively increasing the force applied per unit contact area that improves penetration, while increasing the surface area provided by the wall of the profile in the depth direction, Sufficient area of mechanical contact can be achieved.

For illustrative purposes, FIGS. 143A-143H and 143w illustrate some representative, non-limiting examples of the myriad of possible mother contact profiles. These figures show cross-sectional and top views of contact pads of circular, hexagonal, and rectangular cross sections taken along lines A-A. Also shown in FIGS. 143i-143p are complex contact pads, e.g., only the inverted truncated cone (FIGS. 143K and 143L) and the inverted truncated pyramidal base section, the base being pyramidal and the cube on the upper side. It has a shape (FIGS. 143M and 143N), or a post-in-well shape (FIGS. 143O and 143P). Examples of other shapes are shown in side view only in FIGS. 143Q-143V. Or for contact pads of ring-shaped or pyramidal “tire” laminates, or any other three-dimensional shape for use with the two to three conductor variants described above, or any other simple or complex combination shape. It will be appreciated that similar approaches may be used for the stereoscopic geometric sections.

In another variation, a "wing" as shown in FIG. 143V may be used at the base of the contact. Here, the wings can increase the surface area of the contact by simply increasing the lateral area to the contact.

It may also be desirable to use asymmetric or elongate contacts (ie, contacts having different widths in different directions to absorb strain in a particular direction, as shown in FIG. 143x). Alternatively or additionally, a set of such asymmetric or elongate contacts can be used together such that they are arranged symmetrically around the stress zero point but can be oriented in one of several directions as shown in FIG. 143y. . Thus, a more complex version of the contact regarding the shape of FIG. 143y is shown in FIG. 143t.

In addition, the profile of the contact may include an undercut as shown in FIGS. 143j, 143l, 143n, 143q, 143r, 143s, and 143u. This undercut serves to increase the strength of the contact because it provides an area that allows the soft material to be "grab". Likewise, the posts can be patterned to have a wider opposing or total surface area to ensure a sufficient area of contact even when incomplete connections are provided. In addition, as shown in FIG. 143T, a given contact itself may consist of a plurality of contacts, in which case the individual parts are in an electrically independent state. Alternatively, some or all may be electrically connected to each other. This variant provides a wider surface area and redundancy effect for more similar shear strength, so that if one or more sub-contacts are misaligned, the entire connection can still be formed while providing sufficient contact area to deliver the required current. To be equipped.

In addition, one thing to note is that the specific shape of the contact pad or the shape or configuration of the profiling used is independent of each other. As an important aspect, some profiles have been used to increase the effective contact surface area while providing the shape suitable for a particular application. If a particular contact or profile is not used, it is subject to engineering requirements that the total current requirement of the contact can be handled by the minimum allowable amount of contact; if a specific profile is used, profiling is not used It is possible to increase the surface area to a level sufficient to achieve the desired goal of the possibility that bad connections may result. Moreover, although discussed in conjunction with rigid / mother contacts, flexible / daughter contacts that are profiled similarly may be used. In this case, however, the configuration of the contacts would include the rigid well configuration on the mother wafer in the most conventional form.

144 is a photograph of a profiled flexible contact of a variant, which has a shape similar to a pyramid base with rounded corners and slightly concave top.

145 is a photograph of a profiled rigid contact configured to penetrate the flexible contact of FIG. 144.

Hereinafter, the above-described contact will be briefly described with reference to FIGS. 146A and 146B in which portions of a pair of chips 14600 and 14602 similar to the chips of FIG. 47 are shown. However, in the discussion below, unlike the chip of FIG. 47, one chip 14602 has a profiled rigid contact 14604 opposite to the unprofiled rigid contact of FIG. 41. The other chip 14600 has a soft contact 14606 similar to the soft contact of FIG. 47. When two contacts 14604 and 14606 are joined together, a post and a through fit are formed, as shown in FIG. 146B. However, unlike the contacts of FIG. 47, each of the individual miniposts of the profiled contact 14604 penetrates through the soft contact 14606 and is connected to the soft contact 14606 using the same amount of pressure. Provide a contact surface area for diffusion connections that is greater than the "profile" of an unprofiled contact. Moreover, some implementations of profiled contacts provide additional advantages of minimizing the risk associated with incomplete connections. This independent aspect is also shown in FIG. 146B. Despite the fact that the connection between the two contacts 14604, 14606 is less than ideal (i.e., there is a gap 14608 near the valley 1462 of the rigid contact 14604), the rigid contact 14604 The additional contact area provided by the profile side 14610 on C) means that the connection is acceptable.

As otherwise stated for illustrative purposes, if the rigid contact 14604 is not profiled, the contact area is assumed to be equal to the minimum contact area that can meet the total current requirement of the contact. In this case, if any part of the contact does not make a good connection, the connection is unacceptable and may lead to premature failure during use or even no use at all. In contrast, the rigid contact of FIG. 146 is profiled in this example. 146A and 146B, assuming a profile (easily achievable) that increases the contact surface area by at least two factors, if only half of the total surface area produces a good connection, this connection Can meet the minimum total current requirement. Thus, as shown enlarged in FIG. 146B, although there are areas where no contact is formed, these areas are well below one quarter of the contact area required for a good connection, and the contact meets the acceptable usage criteria. have.

Alternatively, profiled contacts may be created using a plurality of small rigid contacts in conjunction with one or more larger soft contacts to create a single total contact. For example, a contact may have electrical connections consisting of three sets of contact pairs, where each pair of contacts consists of a plurality of rigid contacts and one (or a plurality of) soft contacts.

Other variations associated with the profiling concept include the creation of "wells" that are configured to assist or improve alignment, constrain soft materials, or assist in the formation of good connections, depending on the particular implementation. As shown in the following figures and described with reference to these figures, such well-attached variants provide additional advantages and benefits for certain embodiments.

147 through 152 illustrate a process of one variant to implement the well attachment concept when the mother wafer contact and the daughter wafer contact are paired (FIG. 147). In this variant, the cover glass opening of the daughter wafer is used as a template and is being built into a permanent well using, for example, polyimide, SU8, other epoxy, glass, and / or dielectric (FIG. 148A). Similar approaches are used on the mother wafer, except that the wells do not surround the entire area delimited by the cover glass. The soft material and (optional) soft cover material are then inserted into the wells of the daughter wafer, in which case it is noted that this material is not filled over the entire depth of the well (FIG. 149A). Similarly, a rigid material is built up from the pad surface of the mother wafer (FIG. 149B). The wells on the mother wafer are then removed (FIG. 150). Such a well on the daughter wafer is held in place.

As a result, the wells of the daughter wafer confine the bonding material (eg, cover and soft material) during the tack phase (FIG. 151) and dissolution phase (FIG. 152) as well as during the through process. In addition, the well can set a threshold of depth, since the well can be formed to a height that affects the surface on another wafer or well before any other processing takes place.

Advantageously, this approach allows the wells to consist of a material that reaches the point where the cover or cap material or soft material is semi-liquefied or at the exact melting point or at least a point that is soft enough to diffuse normally. This is useful when the contacts are placed in close proximity to one another, and the flexibility that occurs during melting allows the material to expand laterally in an effort to reduce surface area. For those contacts where the spacing between the edges of the well-free contacts is less than or equal to about three times the height of the soft material, a pre-integration scheme for such use may be desirable (eg, the soft material is 8 microns high). If the spacing between contact edges is less than or equal to about 25 microns, this approach should be considered).

Also, if too close to the melting temperature, certain materials may wet the wafer surface rather than diffuse, and may flow along the surface. In the case of unexplained soft contacts, this action can short between adjacent contacts. Advantageously, the wells retain these materials, which can prevent the material from flowing by surface tension and prevent the material from retaining in the wells shorting adjacent contacts.

For example, if a post bonding process is performed that can melt the bonded contacts, the wells may also be important in any embodiment. For example, if a contact is made at a suitable temperature for the rigid-soft contact to be made, the bonded chip needs to be soldered to the package but the temperature required for the soldering step is greater than the melting temperature of the contact as it exists at the completion of the melting step. high. Thus, because the molten material is encapsulated and reattached by the wells upon cooling, the contact remains intact during the process.

In addition, because the wells are patterned using semiconductor lithography techniques rather than conventional mask printing or soldering techniques, the well approach is well suited for making many densely arranged connections.

In other variations, the "recess" of the well process described above may be used. In these variations, the process is performed so that the wells are not filled with soft material. These variations are included in one of the four classes shown in FIGS. 153-156.

Class I (FIG. 153): In well connections of this class, the daughter wafer comprises a soft material and the mother wafer has a rigid well (appearing to be etched in the semiconductor wafer). The walls of this well are coated with a diffusion layer metal, for example Au. In order to join the two wafers, the soft material on the daughter wafer is inserted and fixed into the well so that the soft material deforms. The addition of temperature and pressure during the tack step causes the soft material and the diffusion layer to form a tack connection. During the melting step, the ductile of the daughter wafer and the diffusion layer of the mother wafer diffuse together to form a metal bond. Depending on the particular embodiment, the soft material comprises a volume of material that is slightly larger or at least larger than the well so that the fixation between the two wafers during the tack step is strong and no voids are created after the melting step is complete. This class violates mother / daughter rules.

Class II (FIG. 154): This class is similar to Class I except that a well or soft post is formed into a shape to automatically or facilitate alignment between two wafers. This class also violates mother / daughter rules.

Class III (FIG. 155): In this class, the post is a rigid material and the wells are coated to a certain thickness with a soft material. This is the same as the basic profiled soft contact approach described above except that the soft material has a more pronounced recessed profile and a simple indentation that naturally occurs from the height difference between the cover glass and the IC pad. The dimensions of the posts and wells are preferably chosen such that no voids occur after integration (ie, after completion of the tack and dissolution process).

Class IV (FIG. 156): In this class, the wells are coated with a diffusion layer (as with classes I and II, the posts are made of a rigid material but the outside is coated with a layer of soft material). This means that if the material ratio of the rigid material is less than the material ratio of the soft material, for example, if the rigid material contains copper as the main material but the soft material contains gold as the main material, the cost of the daughter wafer may decrease. Same as Class I and II except that it is.

Advantageously, in the above-described approach, the wells can be made or recessed using, for example, a dielectric (ie made by etching the semiconductor). The wells may also be by-products of the via formation process. For example, the well may be part of a via that is not fully filled. 157A-157B are longitudinal cross-sectional photographs of sets of 15 micron diameter vias extending to 135 microns deep and 25 micron diameter vias extending to 155 microns deep, respectively. 158 is a photograph of a similar via without all of the passages to the bottom. As a result, by thinning the back side of the wafer until the bottom of the via is exposed, a natural well will be formed. This well can be used as is in class I wells. Alternatively, a flare or taper may be etched at each inlet to obtain a class II well.

159-167 illustrate another variation of the class II type rigid well attachment approach. This version of the rigid hole well begins with one of the fully formed wafers and pads 15902 exposed through cover glass 15904 (Fig. 159). First, a barrier layer 16002 is deposited over the IC pad 15902 (FIG. 160). Photoresist patterning then exposes a region around IC pad 15902 that includes a portion of cover glass 15904 (FIG. 161). The wells are automatically formed by the process of depositing metal into the recesses formed by the cover glass on the IC. This makes patterning easier than some of the other rigid well hole processes. The strip of photoresist removes excess unwanted metal remaining behind a well formed rigid well (FIG. 163).

In another class II variant, the wafer 16402 supporting the counterpart in the wafer of FIG. 163 does not have a rigid “post” in the sense described above, but is insulated 16404 coated with a cap 16406 of a ductile material at appropriate portions. This variant violates the daughter / mother rule (Fig. 164). The rigidly formed hole allows penetration of the soft portion on the insulator with good fit and adequate surface area (FIG. 164). As shown in FIG. 165, the soft cap melts and attaches to the post by heating. As shown in FIG. 166, during the tack phase, the soft cap becomes liquid or semi-liquid and fills the voids of FIG. This is desirable because the gas trapped in the void, such as by expansion and contraction during the thermal cycle, makes the contact potentially unreliable. If the soft cap fills the void during the tack phase or at the start of the melting step, the melting step diffuses into the soft material that forms the rigid cap and the final spliced fusion splice.

Another well attachment variant may be formed using the profiled contacts of FIG. 144O, 144P or 146. In this variant, the wells are formed by a pattern of rigid material to form walls that can prevent passage of the liquid material. Thus, this approach is advantageous in terms of rigid-flexible paradigms because, if properly designed, allowing high yields at high contact densities, the wells can contain any liquid material or prevent the soft material from expanding laterally. Allows the use of the process with or without it and allows very dense connections.

168-170 show another variation of the well attachment approach where chips are attached to each other by separate remote contacts. This approach is advantageously applicable in at least three cases.

1) It is not desirable to place the cover material on the soft material because it can adversely affect the way the material is bonded.

2) For example, in the case where each wafer has a very flat surface, after the adhesion is performed at a very low temperature (or sometimes even room temperature) to improve the processing speed, the chips may be attached by van der Waals' forces or Suspension atomic bonds form covalent bonds that enable connection by insulators such as oxides, nitrides or other dielectrics (this avoids or reduces the waiting time to reach the temperature of the part, Not required, potentially reducing the cost of major equipment)

3) As described above, spillage or creep may occur and limit the potential density of the actual contact, so that the primary contact does not change completely in liquid phase and reflows the adhesion material to self-center the chips for subsequent dissolution process. If it is desirable to have a (liquid phase change) (in this case too low cost equipment can be used to perform the attachment, because the remote attachment contact can indirectly provide that level of precision so that the equipment can You don't have to have the necessary sorting precision)

By way of example, the remote contacts 16802 and 16804 may be made of a material such as light indium at room temperature, and may therefore be attached using only the pressure that compresses the parts together. Alternatively, some other low temperature materials may be used if the particular material is not of great importance and does not adversely affect the whole (ie, cause a short circuit, etc.), which can be adhered even if not at a high temperature. For example, low temperature solders (less than 250 ° C.) may be used. If in the liquid phase, the surface tension aligns the two chips so that the attachment process can be performed with low cost equipment with low alignment accuracy, such as conventional pick and place machines. In addition, the remote contact may be configured such that simple covalent coupling aligns and connects the chip when very flat.

In this process, as shown in FIGS. 168-170, the detached contact is used to connect the device during the initial attach phase (discharge phase). 171A and 171B show plan views of alternative remote contact variants similar to those of FIGS. 168-170. This separated contact may be completely separated from the electrical contact, for example, formed at or around an individual chip edge (FIG. 171A), or may be disposed together with the actual electrical contact (FIG. 168, 171B). Advantageously, the remote contact described herein is compatible with all variations of the primary contact and may have a greater height and width than the primary electrical contact since it does not have to be made of cloth pitch. Preferably, the primary contact should be high enough so that it does not touch during the attachment process (FIG. 169). Note that it does not have to be high strength in this attachment or adhesion process. Subsequent dissolution of the primary contact may provide strength to the bonded chip. FIG. 170 illustrates the wafer of FIG. 169 after the dissolution process, in which the primary contacts were permanently bonded with high strength bonding.

In general, as with the tack step, the dissolution step may occur at temperatures and / or pressures greater than those required for the attachment or adhesion step of this variant.

In other words, like a material that can change into a liquid or semi-liquid phase during the tack and dissolution steps, the compression of the attachment contact may laterally increase the attachment contact and / or the heating of the material may cause the material to turn liquid and increase, 1 Opening up to the car contact can potentially cause an electrical short. Thus, one advantageous choice is to apply the principle of forming a "well" based electrical contact described herein to a remote contact. Likewise, they can become liquid or elongate laterally without contaminating or shorting the primary contact at pressure application or at temperatures during the tack or dissolution process.

Advantageously, the remote contact may be configured to enable testing of the two chips, regardless of bonding in the tack and dissolution steps or before joining the actual contacts together prior to bonding. If the chip is designed such that the location of the remote contact is the location of a special pad capable of interchip communication to test whether a particular individual chip combination is operational, then if one or both chips are inoperative (i.e. nonfunctional or non-functional), The chip is separated and a new chip is attached.

In addition, with proper design, the counterfeit hybridization testing approach is very useful because the coupling can be included in the design, whether it occurs on a wafer-to-wafer, chip-to-wafer or chip-to-chip basis. Thus, the selection of the type of bond to be used for a given application (i.e. wafer to wafer, chip to wafer or chip to chip) may be partly a factor of the function to be tested. For example, if testing is possible on a wafer basis, all chips on the two wafers can be hybridized in parallel on the wafer basis by cutting the non-operating chip once and then flagging for reprocessing. Alternatively, this approach can be used where the individual dies are from one or more castings and there is no preferred way to know if a given die is a known good die hybridization.

In another alternative form, the remote material may be a material such as a primary contact (eg, rigid and soft) as long as it is higher than the primary contact so that the primary contact does not come in contact during the initial attachment step. Then, during the dissolution process, the remote contact will be compressed more than the primary contact. Advantageously, by using the same material for remote and primary contacts, the process is simplified.

From the above technique, derived deformations that establish and combine concepts from multiaxial through vias, well attachment, profiled contacts and remote attachment deformations can be derived.

Variations of the first group include complex contact forms (ie, contact forms other than conventional single square or single point). As such an example, in the simplest case, more complex, irregular open or closed (FIG. 172C) geometry, similar to a coaxial or triaxial through-chip connection having a square (FIG. 172A) or circular (FIG. 172B) cross section. There is a creation of a shielded contact.

In the case of coaxial or triaxial contacts, the inner contact is connected such that the outer closing ring is signaled while the outer closing ring is connected to the ground or ground. When used with coaxial vias (FIG. 173), the contacts are reliably shielded all the way to the other chip. In addition, or alternatively, coaxial contacts may be used separately from the via itself (FIG. 174) such that each contact itself is blocked. This allows interchip contacts to be spaced together closer together than valid without a coaxial approach. In addition, the outer contact ring of each contact may be connected and / or connected to the electrically insulated metal together and / or over the wafer to form a ground and / or interchip shield (FIG. 175).

Using the outer ring of the contact as ground allows for chip-to-chip shielding because only the area where the signal travels is through a very small opening in the shielding layer. The same is true for triaxial connections where other signal pairs may exist in the outer ground. Thus, such contacts are particularly suitable for chips that carry high speed or RF signals.

Variants of the second group may be used between two chips (or chips and a package or board) to protect a connection pad, such as an I / O pad, or an external device (eg, an optical device) that may exist between two external devices. The explanation will focus on using a contact approach for forming a sealed chamber between the layers. In this case, the connection pad and / or the optical device were previously present or introduced simultaneously and inserted between two elements (eg two chips or one chip and a package or board). The ring is formed on two elements outside the area to be protected and configured to be joined using a ductile / rigid or well attach process, so that when the two elements hybridize together, they form a hermetic metal seal around everything therein. do. This hermetic package allows the metal's nonporosity to withstand most environmental conditions and thus withstands most arbitrary environments.

An important advantage of some variations of this approach is that, because of the use of flexible and rigid connections (in contrast, other connection approaches, such as metallic solder, which are liquid), the connections can take a variety of geometrically sealed shapes. This is in sharp contrast to liquid materials that reshape (e.g. cubes into spheres and rounded corners, etc.) through surface tension to the lowest effective surface area, and the technique uses liquid materials along a predetermined surface of the chip by capillary action, for example. While used to be transported, it is not possible to reliably ensure proper distribution of the material with respect to the contact, avoid void formation, or potentially short the contact when some material is depleted in certain areas or contains complex shapes. none. On the other hand, with this variation of the approach, the approach is the same regardless of the shape, so the simplicity or complexity of the shape is irrelevant-except for the ability to define the shape photolithographically and to deposit the appropriate metal. There are only restrictions.

176 through 179 show two simple examples of what has been described above. Specifically, FIG. 176 has a region 17602 with an inserted device (not shown), as described when connecting and coupling the rigid 17604 and flexible 17606 contacts surrounding the perimeter of the device region 17602. The corresponding chip surface is shown as configured to form a hermetic seal around the periphery. FIG. 177 shows a cross-sectional side view along A-A of the same chip of FIG. 176 after mating. 178 illustrates a more complex arrangement in which the rigid 17802 and soft 17804 contacts have a more complex shape and, in effect, form three different enclosed chambers around the device region 17806, 17808, 17810. FIG. 179 shows a cross-sectional side view along A-A of the same chip of FIG. 178 after coupling.

In this case, the via formation deformations as well as the rigid / soft contact deformations may be summarized in a tabular form using the tables of FIGS. 180 and 181a and 181b.

180 is a table summarizing other approaches for forming other variations utilizing the stiff / soft contact paradigm. This table is read downward circumferentially by each text containing box representing a step in the process and each empty box (or a portion thereof) indicating that no action is required.

Similarly, Figures 181A, 181B and 182 are tables that include those described and summarize the different approaches for forming via variants. These tables are also read downward circumferentially by respective text containing boxes representing the steps in the process and respective empty boxes (or portions thereof) indicating that no action is required. The bottom of FIG. 181a is connected to the top of FIG. 181b.

The various examples described the above approaches with reference to alternative metal deposition or plating of the daughter wafer on the daughter wafer (daughter wafer). For purposes of understanding, FIGS. 183 through 192 illustrate in more detail a particular example process flow involving metal deposition on a daughter wafer. 196-205 then show the process flow of plating of the daughter wafer with the same starting wafer.

The process starts with each daughter wafer and mother wafer (mother wafer) of FIG. 183. Photolithography patterning is performed on daughter wafers using, for example, 10 micron resist objects of Hoechst AZ4903 or Shipley STR1075 (FIG. 184). A barrier and rerouting layer of 200 angstroms Ti, 3000 angstroms Pd and 400 angstroms Au is deposited on the daughter wafer and on a barrier layer of 1000 angstroms TiW, and a seed layer of 3000 angstroms copper is deposited on the mother wafer (FIG. 185). ). A thick dielectric (7 micron) or photoresist is then applied to the mother wafer to form a 14 micron wide IC pad with an opening of 10 microns (FIG. 186). The daughter wafer is then metallized by depositing an Au / Sn layer at a height of about 6 to 8 microns on the daughter contact on the IC cover glass (usually larger than the smaller one) and finishing with 400 Angstrom Au. (Figure 187). The mother wafer is metalized to a height of 4.4-5 microns on the IC cover glass (FIG. 187). Thereafter, the photoresist is removed from both wafers (FIG. 188). Next, photolithography patterning is performed on the mother wafer to form openings 15-15 microns wide in preparation for barrier deposition (FIG. 189). Alternatively, self-aligning seed etching is performed to the extent necessary for the undercut to not affect the bumps. Thereafter, a barrier made of 2 micron Ni finished with 3000 Angstroms Au is deposited (FIG. 190). Thereafter, the photoresist is removed (FIG. 191). Finally, unnecessary seed layers are etched away (FIG. 192). This is done as a self-aligned etch with a spray etcher, so no photolithography is necessary because Ni / Au allows etching through Cu / Ti / W. For example, if a spray etcher is not available and a self-aligned etch cannot be performed, additional photolithography patterning steps (FIGS. 193, 194, 195) may be needed to protect the areas that will not be etched. However, for some etching approaches, there is a potential for significant undercuts, so in such lithography, the protective photoresist should be wide enough to prevent undesirable undercuts (FIG. 193). For example, etching with contacts at 50 micron pitch is performed and, as a precaution, it protects twice the width of the IC pads, in this case an area of 27 microns for a 14 micron pad. However, using a spray etcher to perform self-aligned etching, undercutting of less than about 1 micron is possible, thereby protecting very small areas by such approach. Dicing, registration, tack and dissolution processes are then performed to combine the two.

In contrast, the following process flow for the plating case is shown in FIGS. 196-205. Again, the process begins with the wafer of FIG. 183. First, the daughter wafer and mother wafer have a barrier and rerouting (daughter wafer) of Ti0.1 / W0.9 and a seed (mother wafer) layer of 3000 Angstrom Cu, respectively (FIG. 196). Next, as shown in FIG. 197, photolithography patterning is performed on the daughter wafer to limit the barrier area to be applied, and as shown in FIG. 186, a thick dielectric (7 micron) or photoresist is applied to the mother wafer. Form a 14 micron wide IC pad with an opening of 10 microns. Thereafter, a barrier layer is added to the daughter wafer (FIG. 198), and when the photoresist is removed from the daughter wafer, unnecessary barrier metal is lifted off (FIG. 199). Next, photolithography is performed on the daughter wafer using, for example, a 10 micron resist object of Hoechst AZ4903 or Shipley STR1075 (FIG. 200). Next, the daughter and mother wafers are metallized by plating to a height of 4.4 to 5 microns on the mother wafer on the IC cover glass and to a height of 6 to 8 microns on the daughter wafer (as in FIG. 187) (FIG. 201). . Also, for example, a cap of 400 Angstroms Au is applied depending on the plating complexity. Thereafter, the photoresist is removed (FIG. 202). Next, photolithographic patterning is used to prepare for barrier addition on the mother wafer (FIG. 203). Next, a barrier is deposited on the mother wafer (FIG. 204). Again, the photoresist is removed from the mother wafer (FIG. 205). The excess seeds are then etched away using self-aligned etching as in FIG. 192. As with the deposition example above, if spray etchers are not available, additional photolithographic masking, etching and removal steps are required to make the protective area large enough to allow for etch undercut.

At this time, the dicing, matching, tacking and dissolution process may be performed as required to combine the two.

Based on the above it is useful to note the advantages and disadvantages of each approach to assist in the selection of the process method to be used for a particular application.

The deposition approach for daughter wafers has the advantage of no seed layer and no electroplating, which is a mask process that automatically has Au / Sn composite precision. However, this approach has the following disadvantages. That is, run-to-run thickness control is difficult, a metal "wing" may occur when the deposition direction is deviated, and an Au regeneration program may be required.

The plating approach for daughter wafers has the following advantages. In other words, it is inexpensive, requires no regeneration, and can be supported by major equipment suppliers as it is possible to use conventional widely available plating equipment. However, the disadvantage is that the required compounding precision is +1.5% /-2.5% and potentially requires additional mask steps.

There are three important process variants using the mother wafer.

1) Electroless plating (shown in FIGS. 206a (chip), 206b (plating with 6-8 microns Ni), and 206c (caps with 3000 Angstroms Au))

2) thin resist electroplating process using copper (FIG. 207a (first masking), FIG. 207b (4.5 micron Cu), FIG. 207c (2 micron Ni wrapped with a cap of 3000 Angstrom Au), FIG. 207d (second masking), FIG. 207E (excess seed etch removal)

3) Thick resist electroplating process using copper (Fig. 208a (first masking), Fig. 208b (copper plating), Fig. 208c (second masking, barrier and cap), Fig. 208d (third masking), Fig. 208e (excess) Seed etch removal)

Each of the accompanying advantages and disadvantages is as follows. Advantages of the electroless approach include no barrier deposition, no seed layer deposition, no seed etch, and no mask processes. However, electroless plating of nickel may be difficult to control for high capacity wafer yields due to difficult control over thickness or nodule formation that may affect yield. The advantages of the thin dielectric process are as follows. That is, the process is more controllable using thinner Ni, copper exerts lower stress on the IC cover glass, the use of copper is more mainstream, and the electroplating of copper is more controllable. However, Ni / Au penetration into the mushroom sidewalls is inconsistent, potentially exposing some copper, and the mushrooms are not suitable for the tack process and require additional processing steps (ie seed deposition, seed etching). Etc).

The advantages of thick dielectric deposition processes include better contact or “bump” shapes, full coverage of copper by barrier / cap, better control of uniformity and shape, lower Ni nodule formation, and higher yield processes in terms of typical capacity. Includes provision. However, this approach may require this approach spray etch, since if the self-aligned seed etch is invalid, it potentially requires an additional mask step.

Regarding the description of deposition and plating variations, some parent and daughter contacts are described in detail to better understand the process.

209 shows examples and general dimensions of mother wafer contacts with 14 micron wide contact pads disposed at 50 micron pitch prior to barrier deposition.

FIG. 210 shows the contact of FIG. 209 after barrier and cap deposition.

211 shows the general dimensions of a mother wafer contact with an 8 micron wide contact pad disposed at a 25 micron pitch.

212 shows examples and general dimensions of daughter wafer contacts having 14 micron wide contact pads disposed at 50 micron pitch formed by deposition.

213 shows examples and general dimensions of daughter wafer contacts with 8 micron wide contact pads disposed at 25 micron pitch formed by deposition.

214 shows examples and general dimensions of plated mother wafer contacts with 14 micron wide contact pads disposed at 50 micron pitch before self-aligned seed etching is performed.

215 shows the contact of FIG. 214 after self-aligned seed etching is performed.

The ranges of Au / Sn presented in connection with FIGS. 212-215 are representative of a more general range. In practice, about Au _{0 .7} Sn _{O .3} to _.9 Au ₀ Sn _{0. If} a range of ₁ or a suitable temperature adjustment (that is, an increase in temperature with increasing Au content and a decrease in temperature with decreasing Sn content) is made, a wider range can be used.

Having described various through-chip connection variants and applications relating to the electrical aspects of the various chip-to-chip connections, they do not specifically include any additional alternatives or chip-to-chip signal transfers that utilize embodiments that include an unfilled internal trench or void. Explain the deformation.

In particular, if the deepest void is in an unfilled state, it is possible to create alternative advantageous stacking deformations. By sealing the voids in the peripheral parts but leaving each other open, the voids can be used, for example, to help cool the stack of chips.

In this variant, the series of wafers with vias is stacked to protect the via sidewalls in the resulting semiconductor wafer and creates a continuous and adjacent air and liquid fill tube when the wafers are attached. The stacked portion is arranged such that the tube extends through some or all of the stack. A portion of the tube through the chip stack is covered by the configuration with the condensation region, for example, the stacked portion is connected to a tube embedded in the heat sink. When filled with a suitable fluid (and wick, if necessary), each of the tubes acts as a heat pipe to more efficiently dissipate heat from the IC stack.

Optionally, the electrically insulated metal is connected to or extends out of a heat pipe (fin or plate) between stacked chips on unused chips to increase heat transfer capability. In addition, such fins or plates may be formed by barriers or seed layers to perform multiple roles, for example, by operating as a shield or ground plane and fins that simultaneously provide multiple roles.

This is accomplished using an internal via as part of the heat pipe configuration, for example, as shown in FIG. 216. 216 shows, in simplified form, a portion 21600 of a stack of chips consisting of any number of individual stacked chips 21602-1 through 21602-n + 1 that are the same or different. In this example, each internal metallization film 2402 is connected to the top or bottom (using a process such as post and through connections or any other approach such as wafer fusion or equivalent bonding) to seal the internal voids to each other Create a tube 21604 within. Appropriate fluid 21606 (and wick 21608, if necessary) is contained within the tube at a suitable pressure to provide individual chips 21602-1 through 21602-n +, for example, to transfer heat to heat sinks 2216 or other cooling devices. Heat pipes are created that can help transfer heat from 1).

Depending on the particular embodiment, one end of the tube is a surface of a doped semiconductor material or substrate 21612 (ie, the tube does not go through all the passages) in the chip or other chip that does not include a portion of the tube but acts as a stopper or plug. Sealed with material. In addition, multiple tubes are formed with different working fluids or different pressures for each working fluid (same or different) to have different evaporation and condensation temperatures. In this way, a wider range of heat pipe operations can be obtained. In addition, these heat pipes may be grouped or distributed with respect to the chip relative to thermal "hot spots" on the chip.

In some variations, the wick 21608, if present, is, for example, porous or capillary structure, sintered powder, grooved tube, mesh, carbon nanotube structure, graphite, or any other suitable wick material. It may be made of. In addition, the working fluid may be any heat pipe fluid as long as it does not corrode, degrade, or adversely affect the contacting surfaces (ie, doped semiconductors, substrates, insulators, conductor metals, etc.). Common working fluids may include water, alcohols, acetone or in some cases mercury. In addition, in any variation, materials that are solid at Atm (101.3 kPa) and 68 ° F. (20 ° C.) may be used if evaporated or sublimed in a suitable manner to provide the transfer of evaporative heat required for the heat pipe. Finally, preformed (ie prefabricated heat pipes) can be used, as long as they fit the dimensions of the insert into the inner via.

Advantageously, this approach can increase the effect even if additional cooling methods are employed because the heat pipes are placed close to where heat is generated and these heat pipes can be scattered throughout the chip. In addition, the above-described approach can be used to create heat pipes in chips where electrical connections are needed.

It is desirable to electrically insulate the chips from each other to prevent electrical crosstalk. In addition, if devices are stacked to benefit from one of the via processes (or variations thereof) described herein, there may be applications where it is desirable to connect two chips to a third chip that communicates with them, and communication between them Can interfere. As evident from the above description, the process of forming an inter-wafer connection may include one or two contacts, even where paired chip contacts for the rest of the wafer are disposed (ie on one or more chips) or And the number of contacts. This means in any case a single daughter chip connects two or more mother wafer chips or a "daughter wafer 2" chip connects two daughter chips or mother and daughter chips. Thus, the connection is a simple application of an additional process of "daughter wafer" or "daughter wafer 2", wherein the set of connections where the process is the same but the daughter chip is not connected in mode has a counterpart on the same chip. However, in any case of this variant, the two base chips (ie the chips to be connected by a single chip) may have different heights. Therefore, it is necessary to handle this height difference. Advantageously, another variant of the via process can achieve this. 217A-217B show two examples of the method. FIG. 217A shows the separation form of this modification, and FIG. 217B shows the connection form. In both cases, the same shield gain can be obtained. In combination with the previous approach, in step 1, one or more chips with vias are attached to the base chip. In this case, a via (or another contact post connected to the top chip) is made to extend a certain distance on top of the chip to which it is attached. This may be accomplished by exposing more metal, for example by plating a metal or removing substrate material, depending on which via process variant is used. In this approach, vias are typically made before the chips are bonded to each other. In the case of the chip of FIG. 217B, in step 2, the wafer may be coated with a layer of non-conductive dielectric such as polyamide, BCB, another polymer, oxygen or nitrogen dielectric or other non-conductive material that may be deposited on the surface of the wafer. have. In the case shown in FIG. 217A, the thickness of the layer is determined by the need to separate two chips stacked vertically from each other. Since signal strength decreases with distance, capacitive coupling decreases with distance, and EMI interference decreases with square of distance, this thickness is typically greater than the width of the signal line (e.g.> 5 microns), but arbitrary In variants of, it may be larger (for example 25 microns or more) for better separation. As shown in FIG. 217B, the two attached chips may have different heights. The reason for the height difference is not related to the process but may be differently etched or thinned and produced on substrates having originally different thicknesses or depending on storage during the process due to lapping or polishing, resulting in height differences of 100 microns or more. Can be. In some cases, a coating material may be added so that it is flush with the top of the thickest chip attached to the base chip. If no rerouting layer is required (described below in conjunction with step 4), this step 2 is optional in any variation of FIG. 217B. In step 3, the wafer is wrapped or polished to expose the vias or other large contacts that are plated or metalized of the various chips. In step 4 (optional), to facilitate the connection, the surface of the polished / wrapped wafer can be patterned and (if necessary) an electrical rerouting layer can be deposited on the surface. This may allow two chips without matching pads to be connected to each other by routing the signals that need to connect the chips together. Again in the situation of FIG. 217B, the rerouting may cause the two chips of the lower layer to be spaced farther apart than the corresponding connections on the upper chip disposed in step 5. In step 5, in FIGS. 217A and 217B, another chip is attached to the structure by one of the joining method variants, for example using a flexible or rigid joining process. The process of steps 2 to 5 is repeated to add the subsequent layer (assuming the chip attached in step 5 with or without posts extending an appropriate distance upwards from the surface). Advantageously, the chip of step 5 does not have a via unless it is connected to an additional layer on top of the structure.

218A and 218B illustrate alternative modification methods to achieve the operation of FIGS. 217A and 217B. In this alternative variant, rather than thinning the chip as in step 3 of the process of FIGS. 217A and 217B, the holes are etched with a planarizing material such as polyimide. Then, if necessary, the rerouting layer of step 4 is used to change the route of the electrical signal and connect with the underlying chips. Next, hybridization may occur as shown in step 5 of FIG. 218A or 218B. Since electrical contact is required after bonding, this procedure is more complicated than the method of FIGS. 217A and 217B. However, as shown in step 6 of FIG. 218B, this process is more advantageous for simultaneous connection with multiple other layers of the chip later than in FIG. 217B. Since the wear process in step 3 of FIG. 217B can wear all posts to the same height, it is more difficult to do the same work in the method of FIG. 217B, so that the top level daughter chip is at the lowest level. Hard to adhere to daughter chip

As noted herein, any number of devices can be stacked high. However, in some special cases, the tack, fuse, tack, fuse approach, or the tack, tack, tack, overall fuse approach In addition to the determination of whether or not applied, the effect and geometry of the stack needs to be taken into account. For example, in a wafer scale stacking process as described herein through through via connections, whether the original daughter wafer must be thinned before being diced in order to join with the mother wafer, or the daughter wafer is a mother wafer ( It should be determined whether it should be thinned after being bonded to the chip or the entire wafer basis. This difference is as follows. Tack, fusion, thinning, tacking, fusion, thinning methods have a small number of steps and, more importantly, lower yields when thinned before dicing and bonding. The advantage is that there is no need to handle very thin wafers. However, this has the disadvantage that it requires lower labor on the joins, i.e. thinner on the more expensive bonds compared to the daughter wafer (s), which can lower yields.

Another disadvantage arises when multiple daughter stacks, each with a different number of chips, are located on the mother chip. Since a separate thinning step needs to take place in each layer of chips on the mother wafer, the placement and order of the thinning is important. As a result, without proper planning, some stacks may not have additional chips because they are located below the height of the adjacent stack. This makes it difficult or impossible to thin the chip.

In contrast, there is an advantage that the thinning before bonding can always be carried out, but as described above, there is a disadvantage in that the risk for having a thin wafer is great.

One application of a number of different alternative, selective, and complementary variations described above is described with reference to FIGS. 219-221. 219 through 221 illustrate some additional advantages that can be achieved in certain applications, ie, microprocessor applications.

219 briefly illustrates a conventional microprocessor chip 21900 in the prior art. This means that each component, namely the conventional coplanar arithmetic logic unit (ALU), registers (REG), buffers and other logic units (BUFFER & LOGIC), input-output (I / O), 1 level cache memo L1, 2 level cache memory L2, memory control device MEM CTL, memory read-write control device R / W CTL, RAM, ROM, and memory Decoding circuitry (RAM / ROM DECODE). As shown, these components occupy a significant area and the distance between any one given part and the other parts is quite long.

220 schematically illustrates how an alternative microprocessor is formed from the same components using the methods described above. On the other hand, such microprocessors have a smaller footprint, a mixture of high speed and low speed technologies, and the distance between components is substantially reduced. Especially. 220A shows an example microprocessor chip 22000 having a reduced footprint through the use of through-chip connections and stacking of components as described herein of the components of FIG. 219. Through stacking, the components are formed of chip devices 22002, 22004, 22006 (side view), which are also shown in exploded views 22008, 22010, 22012, respectively, to show the footprints covered by their subcomponents. Reduce overall. In addition, as shown in each side view 22008, 22010, 22012, the distance between all subcomponents of each chip device 22002, 22004, 22006 is substantially reduced due to through-chip connections. Moreover, the chip-to-chip connections in the chip device 22002, 22004, 22006 do not need to be approximately circumferential, but in practice at almost any position on the subcomponent chip. There may be.

221 directly compares the footprint of chip 21900 of FIG. 219 with the footprint of chip 22000 of FIG. 220. Both are small in size and have a small number of components, but apparently, the latter footprint is substantially less than the former print.

If the chips are designed with the possibility of stacking, other advantages can be achieved. For example, in the example of FIG. 220, different mix end matches of the processing devices 22006, 22012, since each subcomponent chip can be designed independently and only need to share a common interface with other chips. Mix and match configurations can be designed. Thus, a number of different arithmetic logic units (ALUs) having different speeds can be designed, thus making it easier to form a collection of cavities of processing chip devices. Likewise, second size cache memories L2 of different sizes may be designed for use in the processing chip device 22006 for discrimination or performance enhancement that is price-critical within groups. This concept is a specialized case as described below as discerning and active packaging.

As can be seen from the immediately preceding discussion, the result of the processes and aspects described herein is the ability to form different types of packaging more efficiently than previously used.

Currently, integrated integrated circuit chips are fabricated and packaged as shown in FIG. 222A. Through front-end processing, low speed functions, high speed functions, input / output and high speed (ie core analog and digital) functions can all be formed on one chip. Next, back-end processing adds metallization in the layer to form connections between the various on-chip devices. Finally, once the chip is complete, the chip is bonded to a separate package, such as a pin grid array, a ball grid array, or a conventional IC package. This method has a number of drawbacks, including the requirement that all devices be located on the same chip, all of which must be implemented with the highest speed / highest cost technology essential for any on-chip device. As a result, expensive "real estate" is wasted on low and / or low cost devices that can be easily implemented with low or low cost technology.

However, by using the aspects described herein, various forms of packaging can be used, to name a few, helping to optimize cost, process time, and risk of low yield. For example, through the use of the aspects described herein, configurations as shown in FIGS. 222B-222F can be made.

222B illustrates an example deployment made using the aspects described herein. This is called a routingless architecture because it separates the routing process from the chip forming process and allows them to run concurrently. In this arrangement, the first chip Chip 1 is formed using low speed functions and front end processing with input / output and core analog and digital functions. The second chip Chip 2 is formed using back end processing to form metallization layers connecting the devices on the first chip Chip 1. The first chip and the second chip are then joined together, for example, using a method described herein, such as through wafer-to-wafer or covalent bonding, wafer fusion, or the like. Such a combined device can then be treated as a conventional chip and connected to a conventional package in a conventional manner, or processed for coupling with another wafer, chip, or device as described herein.

Another alternative method is shown in FIG. 222C. This method is called a "chip package" method because the chip connections are part of a package. This method is true for the first chip except that in this method, the back-end processing is performed on the wafer portion where the back-end processing can serve as a package or the back-end processing for forming the routing is executed on one wafer. Similar to the method of, the package is formed on another package, the two being processed and joined together as described herein to form a second chip in this method. Thereafter, the first chip and the second chip of the method can be processed and joined together as described herein. Alternatively and alternatively, the processing necessary for the joining of the first chip and the second chip may be performed in whole or in part as part of the processing necessary for joining some routing portions to the package portion. Advantageously, with this method and proper design plan, the second chip design is inclusive of a number of different first chip designs, resulting in potential cost and other savings.

Another alternative method is shown in FIG. 222d. This method is called a " active package " method because it adds low speed functionality to the packaged second chip facing the portion of the primary first chip. Thereafter, the first chip and the second chip can be joined together and connected together through means suitable for a particular application. This can reduce the use of expensive real estate by low speed / low cost devices. In addition, if the low speed function is more comprehensive, more advantages and savings can be achieved.

Another alternative method is shown in FIG. 222E. This method is similar to the method of FIG. 222D except that the input / output is moved from the first chip technology to the second chip, and is called “active package with I / O”. Thus, in this method, the first chip contains only core analog and core digital functions. Here, the chips may be coupled or otherwise connected to each other for operability. Again, since the input / output is typically slow and large in size, substantial savings can be achieved in this way. Likewise, by careful design, the second chip of this method is comprehensive for a number of first chip designs, thus providing the advantages according to the conventional method of FIG. 222A.

Another alternative, the most sophisticated of the methods, is shown in FIG. 222F. This method is called "system on chip" or "system stack". In this method, only core digital functions exist on the first chip of the appropriate speed / cost technique. The second chip is similarly formed and has the core analog function of the proper speed / cost technique. In addition, the third chip is formed and includes only input / output functions executed by its own appropriate technology. Finally, a fourth chip is formed which essentially corresponds with the second chip of FIG. 222D. Advantageously, through this method, in many cases, important mixing and matching can occur because the first, second, third and fourth chip designs are designed with only the chip in mind to be attached. . Moreover, this method can obviously allow each chip to be one chip in a group of chips, for example, all of which share a common interface for that function.

Thus, all of the methods of FIGS. 222B-222F allow for the formation of sensible and active packages, allowing designers to disassemble their designs so that most, if not all, circuits use the most appropriate technology for that function. In some cases this means creating an entirely new design, in other cases using a combination of existing chips. Both of these cases use one or more aspects of the variants described herein. In this regard, the functions appearing in these examples are not intended to mean that particular aspects should be disassembled in the manner shown, but merely to illustrate the concept. Also, for example, a chip having some analog functions and some digital functions and another chip facing a single chip for each functional group can be formed, the point being that parts of the overall design are appropriate for them. Is in the ability to adapt to the technologies. And, through the methods of the present invention, a functional result similar to that made conventionally (e.g., Figure 222A) or an inherent limitation in the conventional method of Figure 222A has been achieved which was previously impossible or costly prohibited. can do.

As a result, low performance circuits can be designed on one chip, and high performance chips can be designed for higher performance technology. Moreover, this type of method is more cost effective because a significant amount of high speed technical real estate can be saved by moving the low speed circuit off-chip without the need for powerful signal drive circuits. Some examples of the myriad possibilities associated with the high level description of the processes described herein are shown in FIG. 223.

As such, some of the above aspects are further discussed in detail. At present, in order to manufacture electronic chips, the wafer must undergo two sets of processes, front-end processing and back-end processing. In front-end processing, practical devices are fabricated, including transistors and resistors. In the case of silicon chips, this may be, for example, growth of silicon dioxide, patterning and implantation and diffusion of dopants to obtain desired electrical properties, growth or deposition of gate insulators, and growth of insulating materials for isolation of adjacent devices and Relates to deposition.

In back-end processing, various devices fabricated during the front-end process are connected to form the desired electrical circuits. This involves, for example, not only the insulating material but also the deposited layer of trace metals forming the connection and etching into its desired pattern. The metal layers are typically composed of aluminum or copper. Insulation materials are typically silicon dioxide, silicate glass, or other low insulation constant materials. The metal layers are connected by etching vias in the insulating material and depositing tungsten therein.

Currently, for 12 "wafers, each of the front and back-end processing takes about 20 days to complete using 90 nm processes, which occur continuously. As a result, 40 to 40 wafers from start to finish to produce one wafer. It takes more than a day.

Advantageously, using the processes described herein, the above methods are the most well known submicron design rules based on chip fabrication technology, since the front and back-end processing occur simultaneously in different unrelated factories. In this case (eg 0.5 μm, 0.18 μm, 0.13 μm, 90 nm, 65 nm, 45 nm, etc.), this time can be reduced to almost half. This runs front-end processing on one wafer (front-end or FE-wafer) and back-end processing on another wafer (back-end or BE-wafer) in parallel, as if both are one wafer. By doing so. In this way, routing with a transistor or other device can be implemented in a factory where routing is inexpensive, each taking approximately 20 days. The junction points are then obtained by thinning the wafer and forming junction points on the back side of the FE-wafer using one variation of the via processes described herein. In a similar manner, the processes described herein are used to form a set of complementary connection points in the BE-wafer corresponding to the connection points of the FE-wafer. Then, for example, where malleable and rigid corresponding connections are formed (typically, the FE-wafer is a daughter wafer of the above processes with malleable contacts) and a tack and fuse approach, as described herein. Remote attachment approaches, covalent or other wafer surface joining methods (alone, through-via methods, and / or use of simple filled vias that serve to hold the two wafers together to maintain alignment, or these Two wafers are joined together by use of a combination of the &lt; RTI ID = 0.0 &gt;

Advantageously, through this method, the metal layers required by the topology and stress constraints imposed by increasingly sensitive transistors need not be limited in thickness or density. In addition, by separating the process into two chips, the lines can be larger and more layers can be formed, increasing the inter-chip intercommunication capability and lowering parasitic resistance for faster chip-to-chip communication.

Advantageously, the processes described herein are different because the method of the present invention is independent of the specific fabrication or connection technology used to make a particular FE-wafer or BE-wafer, or the design rules applicable to such fabrication. The techniques can be used to implement together at the nano-level. In other words, the methods described herein require that any chip design rule be applied to devices or their connections to particular materials (Si wafer, GaAs wafer, SiGe wafer, Ge wafer, InP wafer, InAs wafer, InSb wafer, GaN wafer, GaP wafer). , GaSb wafers, MgO wafers, CdTe wafers, CdS wafers, etc.) are suitable for ensuring that they do not overlap or interact with each other in an undesirable manner, or submicron or sub-nanometer whether any methods due to high resolution masks or non-masks are used to form nanometer properties or to define the spacing between devices, their connections, or the geometries of the connections themselves; and It doesn't matter. Thus, as described above, chip fabrication techniques may be derived from, for example, SiGe, silicon-on-insulator (SOI), connections due to carbon nanotubes, biochips, molecular electronics or the like from current technologies such as CMOS and silicon. Move to other methods designed to provide high performance and / or reduce power requirements.

224 through 231 briefly illustrate this method. As shown in FIG. 224A, the FE-wafer 22402, which has been subjected to front-end processing to form transistors and other completed devices, may employ front devices protected by a photoresist or other removable protective material 22502. To provide the support (FIG. 225A). The FE-wafer is then thinned down to a few microns or more in thickness (ie, removing some or all of the underlying substrate) as needed due to the required or desired height for the mixed FE / BE chip. The vias are then run from the back of the FE-wafer to the appropriate device connection location points, for example, using a back process as described herein or a front via process as described herein, which is simply performed from the back. Formed (FIG. 227A). Optionally, one or more through-vias 22702 having a slightly open shape on the device surface, for example, with malleable contacts on the back, may be, for example, well or reverse well approaches. Or one side of a pressure fit connection is formed around each die. These vias serve to secure the FE and BE-wafer chips together transversely to each other when a shared or wafer side bonding method is used. In addition, a receptacle for the connections between the chips in the form of vias to be part of the heat pipe arrangement or the non-electrical communication arrangement (both described in detail below) can be added. The vias then become conductive (FIG. 228), ready for the FE-wafer to bond to the BE-wafer.

At the same time, a metallization layer 22404 is formed on the BE-wafer (FIG. 224B). In this structure, since the semiconductor material serves as a protection / support, no protection / support is required. However, when substantially overly thin, application of a removable support layer may be necessary. Then, the front face of the BE-wafer is thinned (FIG. 226b), and if necessary or if a complete penetration into or a simple access to a particular inner metal layer is required (FIG. 227B, 228B), vias are formed (FIG. 227b), and metallized (FIG. 228b). In addition, depending on the particular implementation, contact with the inner layer may be made by physical connection or non-physical (ie, capacitive) coupling. If not, complementary connections, such as complementary connections to the post or well, reverse well or other connection, for example when a post and penetration / tack and fuse approach is used Are formed. Likewise optionally, complementary fixed vias (22704 in FIG. 227B) may be added to the BE-wafer, or vias that are part of a heat pipe arrangement or non-electrical communication arrangement may be added. Moreover, when a heat pipe arrangement is used, it is preferable to use BE-wafer metallization (FIG. 228B) to seal one end of the heat pipe. This is especially the case when malleable and rigid tack and melting methods are used due to the strength and sealability of the seals that can be formed.

The FE-wafer and BE-wafers are then aligned with respect to one another (FIG. 229), and once they are brought together (FIG. 230) and bonded (FIG. 231), they form the completed wafer unit of the respective electronic chips. do.

233 to 235 show other variations of the method described above. As in the Figures 224 through 231 approach, these alternative variations may include an FE-wafer (Fig. 2) consisting of semiconductor devices 23202 (i.e., transistors, lasers, photodetectors, capacitors, diodes, etc.) doped on a substrate 23204. 232A) and a BE-wafer with metallized device interconnects (FIG. 232B). However, unlike the method of FIGS. 224-231, the BE-wafers are flipped over, aligned, and joined to the top of the FE-wafer, which occurs before the substrate is thinned (FIG. 232A). Alternatively, the same method as in FIG. 232A can be performed as shown in FIG. 232B so that the BE-wafer can be thinned before bonding.

Another alternative method is shown in FIG. 234. In this case, the BE-wafer is thinned to expose the innermost layer of the original chip from FIG. 232B, which is glued on top of the FE-wafer.

235 illustrates another refinement or alternative variation. As a result of the methods of FIGS. 231, 232b, 233b, or 234, after adhesion, the other side of the metal of the BE-wafer is exposed. Thus, another chip can be bonded to this metal to make another form of chip stacking method.

Another advantage of these methods is that, if desired, other rerouting of connections can be made on the FE-wafer or BE-wafer (or possibly both wafers). Thus, the FE-wafer and the BE-wafer can be formed more comprehensively, providing suitable connection positions for a particular application. Moreover, mixed FE / BE-wafers or FE / BE / FE-wafers or chip stacks can be treated like other wafers formed using all of the conventional processes, so that other wafer (s) aimed at the subject matter described herein. May be a mother or daughter wafer.

Moreover, through the use of chip-to-chip optical connections, chip devices can be designed that use higher speed communication between chips rather than having wired connections due to problems with crosstalk causing interference. . For example, by placing a semiconductor laser on one chip in the stack and a corresponding photo detector on the other chip in the stack, optical connections, rather than wired connections, can be formed between the two. If this semiconductor laser and the photo detector are located close enough, the possibility of optical crosstalk is minimized. This aspect is briefly shown in FIG. 236 showing a portion of a chip device 23600 that includes two chips 23602 and 23604. One of the chips 23602 has a laser 23606 on top of it, and the other chip 23604 has a photodetector 23608 on top of them, so that both of the chips have optical signals emitted from the laser 23606. Arranged to be received by the detector 23608. Moreover, the techniques described herein facilitate optical communication between chips even when one or more chips are placed between the two chips. For example, as shown in FIG. 237, even if the other two chips 23702 and 23704 are placed between the two chips 23602 and 23604, the light from the chip 23602 with the laser is provided with the photodetector. One variation of the heat pipe configuration may be formed to reach the chip 23604. For this purpose, a through-chip approach is used, but the interior space is not filled with any electrical conductors and left open for use as a heat pipe. That is, the interior space is filled with an optical transmissive medium 23706, such as an optical epoxy or other light transport material, to form the optical waveguide. With the use of optical waveguides, metals and / or insulators confine light, allowing the vias to act like optical fibers. Moreover, by adjusting the via size and the components of the outer metal or insulator, the waveguide can have essentially the same characteristics as a single mode or multiple mode optical fiber. In addition, in a variant with a "central island" of silicon, if the central island is not thermally oxidized and removed, this oxidation causes the central island to be silicon dioxide so that a substitute for the "core" of the optical fiber Be sure to Thereafter, by placing the laser at one end of the waveguide and the photodetector at the other end of the waveguide, laser light can be transported through the optical transmission medium 23706 through the chip (s) interposed therebetween.

Specific substitution of the contact material and the example (Alternatives)

As discussed below, a fairly complex contact surface due to its own characteristics of the tack and melting process is repeated in simple form as shown in FIG. Accordingly, it is important to note the alternative materials available for the components of the daughter wafer 23802 and mother wafer 23804 contacts.

In general, for any use, the daughter wafer contact 23802 of FIG. 238 will include the functional layer shown in FIG. 239. Similarly, the mother wafer contact 23804 of FIG. 238 will also include the functional layer shown in FIG. 240. It is noteworthy that contacts 23802 and 23804 may each consist of one or more material layers, or one material layer may serve as a multiple functional layer. This can best be explained by a specific example of the daughter wafer contact shown in Figure 241 and a specific example of the mother wafer contact shown in Figure 242. [ As can be seen from the figure, any particular layer can be made of a part material, an alloy thereof or a superlattice.

Referring again to FIG. 239, in the electroless variant, daughter contact 23802 includes the following components.

Barrier Layer: Ti / W + Pd

Standoff Layer: None

Diffuse / malleable layer: gold / tin (80/20) (1 to 12 microns)

Cap / Adhesive Layer: Gold (> 500 Angstroms; typically 1,500 to 10,000 Angstroms)

Oxidation Barrier: The cap / adhesive layer also serves as an oxidation barrier. The flexible layer can be configured by combining an insulator layer, a diffusion layer, a cap layer, and a barrier layer. In the present invention, the flexible layer is a combination of the diffusion layer and the cap layer.

Likewise, with respect to the mother contact (see FIG. 240), mother contact 23304 includes the following components:

Barrier layer: no Cu / Al pad

Rigid Layer: Copper (> 2 micron)

Diffusion barrier layer: nickel (5000 angstroms; typically 0.5 to 3 microns)

Cap / diffusion layer: Gold (> 500 Angstroms; typically 1,500 to 10,000 Angstroms)

In connection with the foregoing, non-limiting examples of alternative materials available for particular contact layers will now be described.

Barrier (Mother or Daughter) / Diffusion Barrier (Mother): Examples of these include Ni, Cr, Ti / Pt, Ti / Pd / Pt, Ti / Pt / Au, Ti / Pd, Ti / Pd / Au, Ti / Pd / Pt / Au, TiW, Ta, TaN, Ti, TaW and W, but may be omitted if the pad is made of the same material as the insulator. Examples of insulator layer (daughter) / rigid layer (mother) include Ni (particularly when the barrier is nickel), Cu (particularly when the pad is copper), Al, Au, W, Pt, Pd, Co and Cr. Can be mentioned. When sputtering instead of plating, any metal having a melting point higher than the melting point of the flexible layer (generally above 50 ° C) may be used. Such metals may also constitute a barrier material.

Ductile (diffusion) materials: Metals with a low melting point are metals having a melting point lower than 1,000 ° C., such as tin, indium, lead, bismuth, aluminum, zinc, and magnesium, combining two or more of these, or combining them with silver, copper, titanium, and the like. It is an alloy combined with a high melting point metal such as water. Examples of the combination include Au / Sn, Cu / Sn, Cu / Zn, Bi / Ag, and the like. Important to this choice is that the selected material is not used in the actual deposition process because the process speed is very slow, the cost increases, and creep or running problems arise that limit the density by causing contact shorting. It is not suitable for melting. The soft / rigid layer combination ultimately gives strength to the contact. In general, it is preferable to select an alloy comprising a compound containing at least one mixture selected from Au, Ag, Bi, Cd, Cu, Fe, In, Pb, Sn, Sb, and Zn. If an insulator layer is present, the most important requirement is to have a melting point that is equal to or lower than that of the rigid post. In general, the inventors used a melting point difference between 100 ° C. and 500 ° C., but the flexible layer should be at least 50 ° C. below the melting point of the rigid layer. Soft materials have the advantage of being able to give the appropriate height necessary to resolve the non-planarity of the contact, which consists of several types of materials. In fact, the soft material may be formed on top of the insulator post of the rigid material. For example, in some cases, the soft material consists of Au / Sn and is up to 5 microns. In other cases, it may consist of a pile of rigid material (nickel 4 microns, etc.) covered with a thinner layer of soft material (eg, 1-1.5 microns).

Flexible cover materials (cap / adhesive layers): They have a wet at temperature, such as low temperature metals (or alloys) such as tin, indium, lead or zinc. It is important to note that such cover materials are generally much thinner than layers of soft material. For example, usually about 10 to 20 times thinner. For example, the soft (including insulator) material is up to 5 microns, the soft cover material is 0.5 micron, and generally ranges from 0.1 to 1 micron (or about 50 to 5 times thinner than the soft layer thickness). Tin (Sn) is preferred as such cover material. These cover materials have a low melting point and turn liquid in the tack process. However, because the thickness of the layer is very small, short circuits do not occur between adjacent contacts, even if they are not sufficiently liquefied. At the same time, since the tack step is a liquid phase process, the cover material can be attached to the rigid cap more quickly. In general, the cover material should be chosen to be compatible with the soft material after melting, so that the resulting combination is suitable for strong bonding. Taking tin as an example, this approach can be applied to most Au / Sn contacts that include mostly tin caps.

Flexible cover material (oxidation barrier) / rigid cover material (diffusion cap): When used in a "tack" process, the adhesive layer is a material that is susceptible to oxidation, such as tin or zinc, and can be covered with a very thin oxide barrier. have. Alternatively, in the tack process, the oxide must be removed using a reactive gas or liquid, or the oxide must be decomposed using a sufficiently high pressure, which can occur when using indium as a cap. The cover material may be epoxy. For most materials, a thickness ten times thinner than the cap is used. The soft cover material may be a high temperature material that becomes a low temperature alloy (or adhesive) when the soft cover material begins to mix in contact with the rigid cover material or the soft cover material. For example, two covers may be two parts of a miscible epoxy, or the oxidation barrier is gold and the soft layer is gold / tin and the adhesion In the process, when tin is intermixed into the oxide layer, the material has a lower melting point. In general, this layer may be a metal / material that cannot be easily oxidized (Au, Pt, etc.).

243A-243C are photographs of cross sections of actual contacts (mother and daughter) formed using the above modifications in the tack and melting process, showing examples of other layers and how they do or do not interact.

FIG. 243A shows a pair of contacts engaged with the mother wafer and daughter wafer after the tack step in the tack and melting process. As can be seen here, the bond between the two is good, but not as persistent as evidenced by the large area of unbound material.

243B shows similar contact pairs after completion of the melting step. Here, it can be seen that as with the barrier, the bond is persistent. It should be noted that in FIGS. 237A and 237B, the soft material is significantly trapped between the barriers.

243C is a photograph of similarly coupled contact pairs after the melting step. In the above picture, the components are not clearly visible, but there are IC pads of the mother and daughter wafers to discern the relative relationship of the sizes between the two.

Connection-related tooling Tooling )

The various approaches associated with chip, die, and wafer substrates and chip interconnections, and the details of the many substitutions, modifications, and combinations thereof described, have been described, and can be advantageously utilized to contribute to the bonding process. Can branch and describe various types of tooling. Of these tooling methods are not critical to achieving substitutions, modifications and combinations thereof, but rather they are developed to facilitate the process and to other chip-related processes such as "pick and place," and the like. It can be used, in particular, for simultaneous execution on multiple chips, and at the same time particularly preferred when the heights of the chips are different.

For purposes of explanation, tooling variations related to their use in the tack and melting process will be mentioned, but the variations are part of the method or minor variations, and understanding the method does not need to describe a simpler use.

As mentioned above, the attachment process consists of two steps. The first step is a "tack" step of lightly attaching the chips to each other, and the second step is a "fusion" step of imparting bond strength. The tack step heats the contact and closes the contact under low pressure, allowing the materials on the two corresponding contacts to diffuse together.

 During the process, if gravity alone does not provide the required pressure enough, a low pressure is applied so that the chip does not move during the process, thereby making the adhesion of the contacts unsuitable and thus preventing the mechanical handling of the attachment surface from resisting wafer handling. Reduce the possibility of shock or nonuniformity. In addition, the pressure may be reduced when the soft material becomes partially or totally liquid due to partial heating (or is simply not liquefied and is more ductile than the theory and thus interferes with pressure and surface tension or other forces). Excessive ductility), it is possible to prevent excessive single and cavity lateral movement of the part. Thus, by applying a low pressure to ensure a wider range of temperature and processing conditions in the melting process, manufacturing tolerances and deviations can be identified.

However, one of the problems with applying pressure to the chips is that when there are multiple chips with substrate elements (e.g., wafers) attached, each chip is not in plane and may even be quite different in height. to be. Thus, when simply placing a flat surface or flat plate on top of the chip, the applied voltage will be applied non-uniformly.

As discussed below, the method devised to derive the foregoing is to use an arrangement between the source of the force and the chip to follow or identify different heights so that the same pressure can be applied to all chips.

One way to achieve the use of this arrangement is based on a one-to-one arrangement, using a series of pins or posts to match each chip. The two variants of the method will now be described, with the understanding that other variations can be derived in combination with the characteristics of each tooling method, or in combination with those of other tooling methods, to be described later.

244 through 247 illustrate embodiments of tooling that perform a pin or post based method.

As shown in FIGS. 244 and 245, the method utilizes a pin or post set 24402 that is within frame 24404. Each pin or post may move along at least the longitudinal axis (in some embodiments, it may allow for a sleight angle of axis if the plane or slope is a potential characteristic). Posts or pins may be retracted and separated. The post or pin has a surface disposed to abut one chip.

According to one embodiment, the surface of a given pin or post may have a flat, pressurized chip and reverse die, or another shape suitable for a particular application. In addition, at or adjacent to the surface, the pin or post may itself be a circular intersection or non-circular (eg, oval, square, hexagonal, octagonal, etc.) closed. In addition, the perimeter and planar area of the surface may be larger or smaller than the boundaries and areas of a particular chip that may be adjacent (eg, extend around the chip, or include some or all therein). It is important to arrange the surface to exert a force on the chip without damaging the chip (especially cracking or chipping).

In use, the posts in the frame (in some cases, the frame itself) are downward in spontaneous conditions until the post is in contact with the chip (FIG. 245). In this case, the pin is fixed in the proper position. As a result, an appropriate amount of force can be applied to the frame (in embodiments, a pin or a post). As the tool moves down, it only applies a force in the vertical direction to the chip so that the force can be evenly transmitted to each chip through pins or posts.

Thereafter, the joining process can be carried out in accordance with the present invention or alternatively.

Figures 246 and 247 are similar to the methods of Figures 244 and 245, except that smaller chips or groups of posts are used to join each chip, instead of using one pin or post to one chip. Or post-series method. As a result of this, according to the method, each pin or post in a group can be used to identify the nonplanarity or height difference of one chip. In addition, in one embodiment, when the at least several fins are placed outside the peripheral boundaries of the chip, the needle extends below the upper surface of the chip, causing the needle to make lateral motion. On the other hand, the method is the same as the pin / post per chip that secures the surface 24606 of the spontaneous group of pins / posts in contact with each chip so that force can be applied through a frame, group or pin. In addition, the pins / posts within the group may have circular or non-circular intersections around each surface. In addition, as can be seen below, a suitable form of fin can be selected to form or eliminate spacing of pins / posts within a group and achieve desired advantages. It should be noted that each pin / post or group (in the case of multiple pins / posts per chip) needs to be wide enough so that the chips do not break due to the pressure delivered through them and that the edges or corners of the chip do not break during the process. .

In both cases, with the frame holding the posts or pins, once secured, the posts or pins are moved only meaningfully in the vertical direction, so that the structure is only perpendicular to the structure of the chip attached to the wafer. Can be added.

Preferably, as described, when using the tack and fusion method, the force required for the "tack" step is 1 g or less per contact, and in the melting process, generally 0.001 g or less per contact. As a result, it is a matter of design choice and pins or posts can be secured without difficulty through methods such as clamping or locking, which are not critical to understanding the tooling and its use.

Preferably, in one embodiment, one of the toolings can be further enhanced by being able to apply a vacuum to the chip. In the case of pin / post tooling per chip, this can be achieved by providing passages 24412 and 24414 through the posts and openings on the post surface 24406. Alternatively, the pin / post group method may be used to provide a passage through which the pin / post itself is evacuated. Alternatively, the proper shape and spacing of the pins / posts can be determined to form (within chip boundaries) or to remove (near the chip periphery) between adjacent pins so that the vacuum passes through the passage therebetween. .

According to one tooling embodiment using this variant, the tooling itself is used in a pick-and-place process, or a vacuum is applied to the chip in a non-vertical (undesired) manner during a process such as tacking or melting. Vacuum can be applied to the chip to further inhibit movement.

Alternatively, a material that initially adheres the pin or post to the chip may be applied to the surfaces 24406 and 24606 of the pin or post, which material may be selected to "detach" upon completion of the process. May be For example, if a liquefied, molten or vaporized material can be used on the surface at a tack or melting temperature, but the residue remains on the chip or the device to which the chip is attached without damaging the chip, the residue It can be removed through a harmless process or ignored without adverse effects.

The post / pin solution imparts only vertical motion, and in embodiments of the method the chips do not actually hold in place, in some cases the force is applied uniformly to each chip and during the process such as tacking or melting. It can not be guaranteed that it is not inclined. Accordingly, in some cases, movement of the chips or non-uniform fusion between chips or chips of different heights may occur.

In this case, as shown in Figures 248 and 249, the rigidity, depending on the height of the various parts to prevent localization pressure causing scratching, chipping or chip damage while maintaining pressure on the chip, is rigid. A tooling method using a sponge flexible compliant or deformable material 24802 formed between plate 24804 and daughter chip 24906 may be used. This method utilizes a sponge or variant of a thickness (typically 0.01 '' to 0.125 '') suitable for a particular application. Non-limiting examples of such materials include high temperature polymers such as Kalrez ^® 7075, Kapton ^® , or Teflon ^® (manufactured by DuPont), high temperature silicone rubber, heat pads (manufactured by Bergquist Company of Chanhassen, MN.), Ceramic fiber reinforced alumina composites such as Zircar RS-100 (manufacturer: Zircar Refractory Composites, Inc, Florida, NY 10921), catalog numbers 390-2xM, 390-4xM and 390-8xM (x: width) from McMaster-Carr Supply Company Ceramic tapes, such as aluminum oxide-based ceramic tapes made from 1, 2 or 3), ceramic fiber strips (manufacturer: McMaster-Carr, part number: 87575K89), fiberglass paper (manufacturer: McMaster-Carr, part number: 9323K21) or other materials, but is not limited thereto.

 In addition, depending on the material used between the plate and the chip, the material may be reused for two or more times of pressure application and bonding, or may be a material used for single use only.

 As with the pin / post variant shown in FIG. 249, the plate is lowered onto the chip under pressure, so that the deformable material follows the chip and surrounds it with the chip, constraining the lateral motion. The joining process then proceeds using pin / post based tooling.

Alternatively, preferably, if the particular application is less desirable to apply force to the pin / post through the frame, this arrangement may be used according to the pin / post-based tooling. In this arrangement, pin-based tooling is applied as described above. However, the pins / posts all have the same height, and once in contact with the chip, the pin / post ends exhibit the same height difference as the chip. However, by using a plate and material arrangement at the ends of the pins / posts in the opposite direction to the chip, height differences can be utilized and a suitable force can be applied easily and uniformly. In addition, this method would be sufficient to physically remove material from the chip that does not require temperature resistance as a material that must be in direct contact with the chip.

Another method for allowing the chip to continue to bond with the device coupled thereto is similar to the plate variants of FIGS. 248 and 249 shown in FIGS. 250-254, and a relatively thin but rigid material 25002, preferably in liquid or gel form. Tooling consisting of a body 25000 formed by coating with a curable material 25004, which may be laminated and then cured.

The body 25000 is disposed on the chip 24906 array so as to be able to each adhere to the curable material 25004 while maintaining level (FIG. 251). The curable material is cured so that the entire body is rigid (or, as long as the curable material maintains thickness, the rigid portion of the melted body is a flexible compliant material, and when cured, the entire body (ie, body and curable material) Maintain enough thickness to act together.

Once cured, the chip can be moved to the attached device so that, if necessary, the body can be weighed with a separate movable weight during the attachment process (FIG. 252). In addition, since the curable material is attached to each chip and cured, the attached chips cannot move with each other in any direction (lateral, vertical, or tilt (pitch and yaw angle) except for the entire body's own motion. If the entire body maintains the same height in the attachment process, the chip will maintain a similar orientation.

Optionally, underfill 25302 material may be introduced between the body and the device to which the chip is attached (FIG. 253). Underfill 25302 can be used to fill a gap between the chip and the device to which it is attached. In addition, since the area between the chip and the body is sealed, the underfill 25302 can be introduced in a controllable manner (i.e., not flowing where undesirable).

Once bonded, a chemical process such as removing the weight (if used), applying an underfill (if used), and then not damaging the chip (e.g., bottom lapping or polishing of the wafer) Or chemical mechanical process (CMP)) may be used to remove the entire (or wider) body (FIG. 254). By removing the body, the entire chip assembly can be used to attach a new layer of chip as if it were a current underlying device.

Similarly, the "body" method can be used in combination with pin / post based tooling to identify pin / post height differences and apply force to the frame through methods other than direct application. In this case, the pin / post is in contact with the chip so that the body opposite the chip is in contact with the distal end of the pin / post and cured. Thereafter, a force is applied as described above in the preferred process. Once the chip is attached, like the normal pin / post method, the pin / post-frame-total body combination can be easily removed from the chip. Thereafter, the entire body may be separated by pin / post-frame tooling through a convenient process of softening or removing the curable material, or by simply cutting or shearing the pin at points outside the curable material.

 In addition, another advantage of this combination method is that, as discussed above in connection with certain variants, where the assembly-line method of coupling multiple chips to one or more respective sub-elements uses some of the pick-and-place method, There is a repeatability.

Finally, in connection with all of the above toolings, as well as modifications, substitutions or combinations thereof, in the melting stages of the process, gas, formic acid or flux, such as forming gas, between the frame and the chip, if necessary for a particular application It should be noted that it can be introduced into.

In either case, it should be noted that the pin / post method preferably uses a flexible or sponge material (ie, by applying too high side pressure to the chip by itself, inclining, moving during the melting process, or melting Very strict (commercially viable) resistance to process conditions may be required).

 In summary, while the present invention has been described with reference to certain types of chips including optical chips (ie, one or more lasers, one or more photodetectors, or combinations thereof), the methods described herein may be used in conjunction with optical components, or It can be used equally well to form "through-chip" electronic junctions in a type of doped semiconductor chip that includes transistors or electronic circuit components that replace them.

Likewise, certain materials have been found to be suitable for use as "post and penetration" contact materials, but the important property is not the specific material used, but the two that cause diffusion between them to occur to form a junction. Because of the relative hardness between, these materials do not mean only the available materials mentioned.

Certain substance pairs are determined to some extent by factors such as availability, cost, other components used, or compatibility with manufacturing-related processes not described herein, so that more than several potentially infinite substance pairs Itemizing doesn't help. Likewise, there are many optically transmissive materials besides optical epoxy. However, the selection criteria for a particular substance for use in a particular application will be influenced or influenced by this issue and other factors that are not appropriate. Accordingly, it should be understood that optically transmissive media (or media) inserted in the voids necessary for a particular application and transmitting laser light are considered to be preferably available materials without specifically listing all of their possible alternatives.

Accordingly, it is to be understood that the specification (including drawings) is presented for purposes of illustration of many embodiments only. For the convenience of the reader, the specification has focused on examples that represent all possible embodiments and teach the principles of the invention. This specification does not list all possible variations. Other embodiments do not present specific parts of the present invention, and other embodiments not mentioned are also intended to be part of the present invention, and are not intended to give up the scope of the other embodiments. Those skilled in the art will appreciate that many embodiments that are not mentioned are incorporated in the same principles as the present invention and that other embodiments are equivalent.

Claims (31)

In the connecting portion formed between the first chip and the second chip, A first electrical connection comprising a first electrical contact coupled to a protrusion on the first chip; A second electrical connection comprising a second electrical contact disposed within a well on the second chip, the well complementing the protrusion; Bonding metal for physically and electrically coupling the first electrical contact and the second electrical contact in a transverse direction; And A material for the side wall of the well that is peripherally bounded to prevent the bonding metal from swelling or leaking out transversely from the first and second electrical contacts , Wherein the material bounding the periphery of the bonding metal is in physical contact with each of the two chips. The method of claim 1, The portion of the first electrical connection is completely surrounded by a portion of the second electrical connection. The method of claim 1, And wherein the second electrical contact comprises a barrier layer that physically separates but electrically connects the first electrical contact and the IC pad on the first chip. The method of claim 3, wherein the barrier layer is formed of Ni, Cr, TiPt, Ti / Pd / Pt, TiPt / Au, Ti / Pd, Ti / Pd / Au, Ti / Pd / Pt / Au, TiW, Ta, TaN, At least one of TaW, or W. The material of claim 1, wherein the material bounding the periphery of the bonding metal has a height to prevent one of the first or second electrical contacts from penetrating the other of the first or second electrical contacts. , Connections. The method of claim 5, wherein the bonding metal is malleable, The well is partially filled with the soft bonding metal, Wherein the soft bonding metal is configured to deform when pressure is exerted by the protrusion. The connection of claim 1, wherein the material bounding the periphery of the bonding metal comprises one or more of polyimide, SU8, glass, dielectric, photoresist, or epoxy. 8. The connection of claim 7, wherein the first electrical contact comprises a barrier layer that physically separates but electrically connects the IC pad and the first electrical contact on the first chip. The method of claim 8, wherein the barrier layer is Ni, Cr, TiPt, Ti / Pd / Pt, TiPt / Au, Ti / Pd, Ti / Pd / Au, Ti / Pd / Pt / Au, TiW, Ta, TaN, At least one of TaW, or W. In a connection formed between complementary connections on two chips, A first electrical connection on a first of the two chips; A second electrical connection on a second of the two chips; Bonding metal coupling the first electrical connection and the second electrical connection physically and electrically in a lateral direction; And A material bounding the peripherally bounding periphery of the bonding metal to prevent the bonding metal from swelling or leaking out laterally from the first and second electrical connections, The second electrical connection defines a well, A portion of the second electrical connection comprises a material bounding the periphery of the bonding metal, At least a portion of the first electrical connection is located in the well formed by the second electrical connection, Wherein the material bounding the periphery of the bonding metal is in physical contact with each of the two chips. The connection of claim 10, wherein the bonding metal does not completely fill an enclosure formed by a material bounding the periphery of the bonding metal. The connection portion of claim 10, wherein a portion of the first electrical connection portion is completely surrounded by a portion of the second electrical connection portion. 12. The connector of claim 10, wherein the first electrical contact comprises a barrier layer that physically separates but electrically connects the IC pad and the first electrical contact on the first chip. The method of claim 13, wherein the barrier layer is formed of Ni, Cr, TiPt, Ti / Pd / Pt, TiPt / Au, Ti / Pd, Ti / Pd / Au, Ti / Pd / Pt / Au, TiW, Ta, TaN, At least one of TaW, or W. The method of claim 10, Wherein the first electrical connection, the second electrical connection and the bonding metal comprise a malleable material and a rigid material configured to penetrate into the malleable material under a predetermined pressure. 16. The method of claim 15, Wherein the soft material is configured to deform under the predetermined pressure at a temperature below the melting point of the soft material. 16. The method of claim 15, Wherein the rigid material and the soft material are interdiffuse with each other. In a connection formed between the first chip and the second chip, A first electrical contact comprising a first electrical contact coupled with a protrusion on the first chip; A second electrical connection comprising a second electrical contact disposed within a well on the second chip, the well complementing the protrusion; Bonding metal for physically and electrically coupling the first electrical contact and the second electrical contact in a transverse direction; And A material for the side wall of the well that is peripherally bounding the periphery of the bonding metal to prevent the bonding metal from swelling or leaking out laterally from the first and second electrical contacts. , The material bounding the periphery of the bonding metal has a height to prevent one of the first or second electrical contacts from penetrating the other of the first or second electrical contacts, The bonding metal is ductile, The well is partially filled with the soft bonding metal, The soft bonding metal is configured to deform when exerted by the protrusion, The lateral dimension of the protrusion is smaller than the corresponding lateral dimension of the well such that there is a gap between the protrusion and the well before insertion of the protrusion into the well occurs, When the material bounding the periphery of the bonding metal contacts the surface of the first chip, the gap is configured to be substantially filled. delete delete delete delete delete delete delete delete delete delete delete delete delete

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