WO2006134308A3 - Circuit integre protege contre les courts-circuits et les erreurs de fonctionnement suite au passage d'une radiation ionisante - Google Patents

Circuit integre protege contre les courts-circuits et les erreurs de fonctionnement suite au passage d'une radiation ionisante Download PDF

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Publication number
WO2006134308A3
WO2006134308A3 PCT/FR2006/050567 FR2006050567W WO2006134308A3 WO 2006134308 A3 WO2006134308 A3 WO 2006134308A3 FR 2006050567 W FR2006050567 W FR 2006050567W WO 2006134308 A3 WO2006134308 A3 WO 2006134308A3
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
block
passage
ionizing radiation
protected against
Prior art date
Application number
PCT/FR2006/050567
Other languages
English (en)
Other versions
WO2006134308A2 (fr
Inventor
Michael Nicolaidis
Original Assignee
Iroc Technologies
Michael Nicolaidis
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Iroc Technologies, Michael Nicolaidis filed Critical Iroc Technologies
Priority to US11/922,189 priority Critical patent/US7778001B2/en
Publication of WO2006134308A2 publication Critical patent/WO2006134308A2/fr
Publication of WO2006134308A3 publication Critical patent/WO2006134308A3/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/005—Circuit means for protection against loss of information of semiconductor storage devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G11C11/4125—Cells incorporating circuit means for protecting against loss of information

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L' invention concerne une puce de circuit intégré comprenant un grand nombre de composants semiconducteurs présentant des composants parasites à travers lesquels un court- circuit entre la tension d'alimentation et la masse du circuit est susceptible de se déclencher, lesdits composants semi conducteurs étant répartis dans des blocs élémentaires, chaque bloc élémentaire étant relié indépendamment aux lignes d'alimentation ou de masse du réseau d'alimentation principal du circuit intégré par un dispositif de limitation de courant apte à enrayer un court-circuit se déclenchant dans le bloc considéré, et chaque bloc étant dimensionné de sorte que des erreurs logiques susceptibles d'apparaître dans ce bloc soient corrigeables par des moyens de correction d'erreurs.
PCT/FR2006/050567 2005-06-17 2006-06-16 Circuit integre protege contre les courts-circuits et les erreurs de fonctionnement suite au passage d'une radiation ionisante WO2006134308A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/922,189 US7778001B2 (en) 2005-06-17 2006-06-16 Integrated circuit protected against short circuits and operating errors following the passage on an ionizing radiation

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0551663 2005-06-17
FR0551663A FR2887364B1 (fr) 2005-06-17 2005-06-17 Circuit integre protege contre les courts-circuits et les erreurs de fonctionnement suite au passage d'une radiation ionisante

Publications (2)

Publication Number Publication Date
WO2006134308A2 WO2006134308A2 (fr) 2006-12-21
WO2006134308A3 true WO2006134308A3 (fr) 2007-03-01

Family

ID=35825344

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2006/050567 WO2006134308A2 (fr) 2005-06-17 2006-06-16 Circuit integre protege contre les courts-circuits et les erreurs de fonctionnement suite au passage d'une radiation ionisante

Country Status (3)

Country Link
US (1) US7778001B2 (fr)
FR (1) FR2887364B1 (fr)
WO (1) WO2006134308A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8685800B2 (en) 2012-07-27 2014-04-01 Freescale Semiconductor, Inc. Single event latch-up prevention techniques for a semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5469065A (en) * 1989-08-18 1995-11-21 Texas Instruments Incorporated On chip capacitor based power spike detection
US6038183A (en) * 1997-03-27 2000-03-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having burn-in mode operation stably accelerated
US20020080676A1 (en) * 2000-12-22 2002-06-27 Scott David B. Reduced standby power memory array and method
US20040165417A1 (en) * 2002-04-17 2004-08-26 Xilinx, Inc. Memory cell enhanced for resistance to single event upset

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5469065A (en) * 1989-08-18 1995-11-21 Texas Instruments Incorporated On chip capacitor based power spike detection
US6038183A (en) * 1997-03-27 2000-03-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having burn-in mode operation stably accelerated
US20020080676A1 (en) * 2000-12-22 2002-06-27 Scott David B. Reduced standby power memory array and method
US20040165417A1 (en) * 2002-04-17 2004-08-26 Xilinx, Inc. Memory cell enhanced for resistance to single event upset

Also Published As

Publication number Publication date
FR2887364B1 (fr) 2007-09-21
WO2006134308A2 (fr) 2006-12-21
US7778001B2 (en) 2010-08-17
FR2887364A1 (fr) 2006-12-22
US20090128975A1 (en) 2009-05-21

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