WO2006131427A2 - Image sensor provided with a thinned semiconductor substrate with backside metallisation - Google Patents
Image sensor provided with a thinned semiconductor substrate with backside metallisation Download PDFInfo
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- WO2006131427A2 WO2006131427A2 PCT/EP2006/062043 EP2006062043W WO2006131427A2 WO 2006131427 A2 WO2006131427 A2 WO 2006131427A2 EP 2006062043 W EP2006062043 W EP 2006062043W WO 2006131427 A2 WO2006131427 A2 WO 2006131427A2
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- substrate
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- thinned
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- wafer
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- 239000000758 substrate Substances 0.000 title claims abstract description 98
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000001465 metallisation Methods 0.000 title description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 65
- 239000002184 metal Substances 0.000 claims abstract description 65
- 239000011159 matrix material Substances 0.000 claims abstract description 35
- 229910052782 aluminium Inorganic materials 0.000 claims description 39
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 39
- 238000000034 method Methods 0.000 claims description 16
- 229910000679 solder Inorganic materials 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 15
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- 239000010410 layer Substances 0.000 description 79
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 238000002513 implantation Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
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- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
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- 230000010070 molecular adhesion Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
- H01L27/14623—Optical shielding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1464—Back illuminated imager structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
- H01L27/14621—Colour filter arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
Definitions
- the invention relates to electronic image sensors with a matrix network of photosensitive points, and more particularly those which are large (several centimeters on the side) and which work at a fast sampling rate.
- the frequency of sampling is the frequency at which the image points are read. It depends on the number of points per line, the number of lines, and the frame rate (typically 25 Hz or 30 Hz for a video image sensor).
- the sampling frequency is all the higher as there are more points in the matrix network.
- thin-film semiconductor sensors which have been designed to be illuminated by the rear face in particular to improve the colorimetry of the color image sensors.
- the image capture electronic circuits are formed on the front face of a silicon substrate of conventional thickness (several hundred micrometers thick), after which this substrate is carried by its front face on a transfer substrate, and the semiconductor substrate is thinned to a few microns thick.
- the illumination by the rear face makes it possible to avoid scattering of the photons in the metal layers of the front face and thus a crosstalk between neighboring pixels, therefore to a bad colorimetry in the case of color sensors since the neighboring pixels are of different colors.
- the small thickness of the thinned substrate makes it possible to prevent the electrons generated by the light from dispersing in the substrate and also from producing a crosstalk.
- the invention proposes to deposit on the rear face of the thinned sensor a metal layer with high conductivity (in practice the aluminum), openwork facing the photosensitive elements formed on the front face. Accordingly, the invention provides a new sensor manufacturing method and a new thin-filmed image sensor.
- the method of manufacturing a thin-filmed image sensor comprises:
- the face on which the photosensitive matrix and the associated electronic circuits have been formed, by successive deposits and etchings, will be called the front face of the thinned or front face of the thinned substrate.
- the back side of the thinned slice or thinned substrate is the other side, the one that has undergone thinning machining. It is through the back side that the sensor receives a bright image to be converted into an electronic image. This is the back side that carries the openwork metal layer (aluminum).
- the metal layer preferably remains present but not perforated with respect to the electronic circuits associated with the matrix, to serve as a mask protecting these circuits from light. Without being properly perforated, this layer can however be divided into separate zones, electrically insulated from each other, especially in the case where the metal is to be used for the formation of input / output pads in one of the variants of the invention.
- the doping of the rear face of the wafer is superficially increased, creating an overdoped layer whose thickness is a small fraction of the residual thickness of the wafer.
- the openings of the metal layer is removed in the openings, at least a portion of the thickness of the semiconductor layer and overdoped.
- vias are opened in the semiconductor wafer, over most of the thickness of the latter, until bare metal strips which have been formed to from the front face in the operations of producing the matrix and the associated electronic circuits; the deposition of the metal layer in the vias makes it possible to electrically connect portions of this layer to these metal areas.
- the metal layer is used as a solder pad for the connection of the sensor. image outside. At least one other portion of the metal layer, connected to the perforated grid and connected to another metal pad, is used to establish an identical potential on the gate and on an electronic circuit part made on the front face.
- the transfer substrate is a temporary substrate; a transparent final substrate is adhered to the rear face of the wafer; the temporary substrate is eliminated; the metal beaches connected to vias are stripped by the front face of the slice.
- At least one of these ranges serves as a solder pad for an external connection to bring from the outside, through the beach metallic and the via, a reference potential on the perforated grid.
- the image sensor according to the invention comprises, on a transfer substrate, a thinned semiconductor substrate on the front face of which are formed a matrix of photosensitive zones and associated electronic circuits, and on the rear face of which is formed a conductive layer.
- perforated opaque metal having apertures facing each photosensitive zone, the metal layer constituting, facing the photosensitive matrix, a perforated grid with electrical continuity for bringing a uniform potential on the rear face of the thinned substrate, facing the whole matrix.
- At least one conductive via is provided throughout the thickness of the thinned semiconductor substrate to electrically connect portions of the metal layer to metal pads forming part of the electronic circuits associated with the matrix.
- the front face of the thinned substrate is bonded against the transfer substrate, and it is the rear face of the thinned substrate, which surface bears the opaque metallic conductive layer, which remains accessible at the end of the manufacturing of the image sensor, while the front face is inaccessible, enclosed between the thinned substrate and the transfer substrate. Portions of the metal layer serve as solder pads for the connection with the outside (some are connected to the perforated grid, others are electrically isolated).
- the transfer substrate is a transparent substrate and it is the rear face of the thinned substrate which is bonded against the substrate.
- the front face of the thinned substrate remains accessible after the end of manufacture; the rear face and its perforated aluminum layer become inaccessible, enclosed between the thinned substrate and the final substrate transparent. It is through the transparent substrate that the sensor receives a luminous image to be converted.
- the semiconductor substrate is superficially overdoped on a shallow depth of the rear face, at least under the perforated layer of aluminum, with a higher amount of doping impurities beneath this layer than in the openings of this layer.
- the aluminum layer is preferably coated with a black deposit reducing the reflectivity of the layer.
- the thinned substrate may be covered in the openings with an anti-reflection layer.
- the sensor according to the invention may be a color image sensor. Colored filters are preferably deposited on the back side of the thinned substrate, on the perforated aluminum layer; the deposit is made after the deposit and etching thereof. It is done before transfer to the final transparent substrate in the case where the method comprises first a transfer by the front face on a temporary substrate and then a transfer by the rear face on a final substrate.
- FIG. 1 shows schematically a semiconductor wafer on the front side of which formed electronic circuits among which a photosensitive matrix and metal plates;
- FIGs 2 to 7 show the steps of the method according to the invention in a first embodiment;
- FIG. 8 represents an image sensor according to the invention, obtained in this first variant
- FIG. 12 represents a sensor according to the invention in the second variant, carried on a base by a so-called “flip-chip” method
- FIG. 13 represents a sensor according to the invention in the second variant, carried on a base by a method with soldering of connection wires.
- a silicon wafer 10 whose upper part is constituted by a slightly doped epitaxial layer 12 (generally of type P, order of magnitude 10 13 atoms / cm 3 ) of a few micrometers or a few tens of micrometers thick.
- a set of image sensors intended to be subsequently separated into chips, each comprising an individual sensor, is conventionally made on the front face of this slice.
- Each sensor comprises a matrix array of photosensitive zones, interconnections in lines and columns, electronic addressing circuits, photogenerated charge collection circuits, circuits for converting these charges into electronic signals, and metal pads intended for be connected to external connections of the sensor; the external connections are intended for supplying and controlling the electronic circuits of the sensor as well as for collecting the electronic signals representing the images detected by the sensor.
- Two metal areas 14 and 15 have been shown for purposes of illustration in FIG.
- the sensors are made by conventional collective microelectronics operations: deposits of insulating or conductive or semiconducting layers, doping by implantation, thermal operations, etchings, etc. All these operations are done from the front face of the slice which is located at the top in Figure 1.
- the slice being deflected by its front face on a transfer substrate and the thinning of the slice by its rear face until it leaves practically nothing but the epitaxial layer 12 or even only a portion of the thickness of this layer.
- the slice thinned will have a thickness of a few micrometers, containing all the circuits previously manufactured from the front; this thickness does not would not ensure mechanical strength of the slice during collective manufacturing operations if there was no transfer substrate; the mechanical strength is provided by the transfer substrate.
- the transfer substrate is a definitive substrate, the rear face of the thinned wafer is accessible and may be coated with colored filters; it carries metallizations for external electrical access and these metallizations must be electrically connected to the circuits of the front face by conductive vias which will be discussed later, and in particular vias opposite metallic areas such as 14 and 15; the illumination of the image sensor is via the accessible rear face of the thinned slice.
- the transfer substrate is a temporary substrate; after thinning of the wafer and deposition of colored filters on its rear face (for a color sensor), it is carried back again, but this time by its rear face, on a final substrate, and the temporary substrate is removed; the back side is no longer accessible; the front face becomes accessible again and the metal areas such as 14 and 15 can serve as external access pads since they are flush with this front face; conductive vias are still present as will be explained later; the illumination of the sensor is still done by the rear face and the final substrate must be transparent.
- FIG. 2 shows the transfer of the semiconductor wafer by its front face onto a definitive transfer substrate 20.
- the wafer is turned over in FIG. 2, that is to say that its front face is now at the bottom of the figure while that the back side is up.
- the bonding is done with adhesive material or by molecular adhesion without adhesive material. In the latter case, it is preferably provided to first coat the front face of a planarization layer 16 before gluing it against the front face of the transfer substrate; the transfer substrate could itself be coated, if necessary, with a planarization layer before the bonding step.
- the semiconductor wafer is then thinned to a few microns thick. Thinning is done by mechanical machining supplemented by mechanical and / or chemical polishing.
- the slice thinned will be from there designated by 12 since it does not include, in practical, that the epitaxial layer 12, and even a fraction only of the original epitaxial layer.
- the back surface of the thinned slice is then superficially doped with an impurity of the same type as the semiconductor layer which receives this doping (hence an impurity P if the layer is of P type).
- This additional doping P + is intended to facilitate the subsequent electrical contact with a metal layer.
- the doping is carried out by superficial ion implantation, on shallow depth, and it is preferable to provide, before the implantation operation, a deposit of thin silicon oxide (SiO, a few hundred nanometers), which avoids damage the surface of the silicon. This thin oxide layer is then removed.
- Figure 3 shows the thinned slice on its transfer substrate at this stage of manufacture.
- the implanted surface layer (P +) is denoted by 22.
- the doping can be of the order of 10 15 atoms / cm 3 .
- a photolithography operation is then performed to open vias over the entire thickness of the thinned wafer, in order to expose metal strips such as 14 and 15 which have been formed from the front face of the semiconductor wafer in the steps preceding the postponement.
- Other vias can be provided. The vias are used to establish passages to electrically connect the metal pads of the front face to conductors that will now be formed on the back side.
- a highly conductive and opaque metal layer 26 (in practice aluminum) is then deposited on the rear face of the wafer.
- the aluminum layer 26 rests on the implanted rear face of the thinned wafer 12, and it comes inside the vias 24 and 25 in contact with the pads 14 and 15 respectively. Outside the vias, the contact between the silicon and the aluminum is an ohmic contact.
- Figure 4 shows the slice at this stage.
- the vias were represented as sloping flank trenches with aluminum deposited on these flanks; however, if the thinned slice is only a few micrometers thick, the vias may be constituted by vertical trenches with vertical flanges etched by plasma etching, which are filled with aluminum during the deposition of the aluminum layer.
- One can at this stage consider making a black deposit on the aluminum layer, to reduce the reflection coefficient of the latter.
- Photolithography is then etched in the aluminum layer 26 an array of openings distributed in a regular pattern.
- the openings are formed opposite the photosensitive areas of the matrix so that they can be illuminated; they will be illuminated by the side where this layer of aluminum is.
- the aluminum that remains after this etching comprises several zones, among which a perforated grid 30, electrically continuous, which makes it possible to distribute over the entire back surface of the silicon, in the region corresponding to the photosensitive matrix and in particular at its center, a potential constant imposed from the outside.
- the aluminum network that may remain a network of thin lines or thin columns or a cross network of rows and columns as seen in Figure 6.
- the openings in the aluminum are preferably distributed regularly with the not even the pixels so that the photosensitive zone corresponding to each pixel is the least masked possible by the crossed network of lines and columns of aluminum: the aluminum remains only around the perimeter of each photosensitive pixel without masking it.
- the rows and columns of the perforated grid may have a width of 0.25 to 1 micrometer for pixels having a pitch of a few micrometers; they may be wider for pixels having a pitch of more than 10 micrometers.
- the perforated grid may obscure a part of the photosensitive surface, it is found that it has a positive role of reducing the crosstalk between neighboring pixels and thus of the colorimetry since it reduces the proportion of light emanating from a filter corresponding to a pixel and likely to fall on a neighboring pixel.
- solder pad 35 is shown, connected to the pad 15 by the metallization 32 of the via 25.
- outside access pads such as 35 on the chip. These pads are electrically isolated from each other since they correspond to different electrical functions. At least one stud is electrically connected to the aluminum grid 30 covering the matrix to provide it with a reference potential coming from outside (mass potential for example). Conductive vias such as via 24, which do not necessarily correspond directly to external connection pads, can be part of a series of distributed vias (in principle at the periphery of the matrix) to connect the grid from place to place aluminum to front-panel drivers (always with a view to homogeneity of potential distribution on the surface of the chip).
- Figure 6 shows, in top view on the back side, the configuration of the aluminum pattern for an individual sensor. It shows the apertures corresponding to each pixel in the perforated grid 30 which covers the entire central portion of the sensor.
- the portion 38 which immediately surrounds the matrix is continuously opaque, to mask the electronic circuits located at the periphery of the matrix; it is electrically connected to the perforated grid.
- vias such as via 24.
- solder pads such as 35 for the external connections of the sensor. They are electrically isolated from each other and are each connected by a respective via to a metal pad of the front face; one of them can be connected to the perforated grid 30.
- the silicon is preferably uniformly etched (without a mask) to a thickness approximately corresponding to the depth of the implanted layer P +, in order to eliminate it completely or partially in the openings of the grid.
- aluminum the blue light penetrates shallow into the silicon and the electrons that would be generated in the P + layer would have difficulty to be collected by the photodiodes of the matrix.
- the implantation P + remains then only under the aluminum, where on the one hand it promotes the electrical contact between the gate and the semiconductor layer 12, and on the other hand it limits the risks of migration of aluminum in the depth of thinned slice.
- Implantation P + may also remain slightly outside openings, but with a lower dose (or a lower depth) than under aluminum.
- a color sensor For a color sensor, the following operations are then performed: deposition of a transparent planarization layer 40 (silicon oxide), deposition and etching of colored filter layers 42 and deposition of a transparent protective layer 44. protective layer and the planarization layer for stripping wire bonding metal pads of the sensors.
- Figure 7 shows the collective structure at this stage.
- FIG. 8 shows a sensor made and mounted on a housing base 50 with a solder wire 52. In use, the light arrives from above, that is to say from the rear face of the silicon chip, the transfer substrate 20 being stuck to the base.
- transfer substrate 20 is a temporary transfer substrate and must be able to be removed later from the wafer, either by separation or by machining.
- the vias such as 25 and the solder pads 35 are no longer necessary because the solder pads will be constituted as will be seen by the metal pads 15 which were formed from the front of the semiconductor wafer; the drawing of these beaches must of course be planned accordingly; the vias 24 for electrically connecting the metal grid 30 to a metal strip 14 remain necessary, the range 14 serving as solder pad for a connection which brings a reference potential to the perforated grid 30 (mass connection for example).
- a transparent final transfer substrate 60 in principle a quartz wafer.
- the bonding can be done with the addition of transparent adhesive material, or without addition of adhesive material, by molecular adhesion.
- the protective layer 44 must serve as a planarization layer or it must first deposit on the layer 44 a planarization layer.
- the temporary transfer substrate is removed (FIG. 10) by delamination or by mechanical and chemical machining. This operation is done so as to expose the metal pads 15 which must serve as solder pads for connection with the outside. If there was a planarization layer 16 (see Figure 2), the thickness of the latter must be reduced until the beaches 15 are flush with.
- a passivation layer 62 may be deposited on the entire exposed face, which is, as recalled, the front face of the semiconductor wafer. This passivation layer is then etched opposite the metal areas 15 which will serve as solder pads (FIG. 11).
- the slice is cut into individual chips each corresponding to an image sensor.
- the image sensor is further illuminated by the rear face of the wafer, thus through the transparent transfer substrate 60.
- the sensor can be mounted on a base 50 according to the flip-chip technique in which the solder pads receive weldable bosses ("solder bumps" in English); the front face of the chip is then turned towards the base and welded to it via the bosses. The light comes from the side (of the base) that carries the sensor
- the sensor can also be conventionally mounted according to the wire-bonding technique; in this case the transparent substrate 60 rests directly on the base 50 (FIG. 13) and it is necessary that the base, if it is not transparent, comprises a window opposite the photosensitive matrix of the sensor; the light comes from the other side of the base (the opposite side to the one carrying the sensor).
- the principle is that before deposition of the metal layer, an additional local doping operation is performed in the areas to be covered by the grid, through a mask complementary to that which defines the openings of the grid during of the engraving of it.
- a thin silicon oxide layer is first deposited to protect the surface of the thinned epitaxial layer, and then low-dose P-type impurities are implanted in the silicon at a shallow depth below this layer. Then the silicon oxide is removed, and an antireflection layer (preferably based on silicon nitride) is deposited. Then, through a resin mask complementary to that which will later define the perforated grid pattern, the nitride layer is etched where there will be the aluminum grid and is implanted in the non-protected area by the resin and the nitride a larger dose (in practice deeper) P-type impurity that will be later under the perforated grid.
- an antireflection layer preferably based on silicon nitride
- the aluminum is then deposited and a new resin mask is formed which covers the areas of aluminum to be preserved.
- the surface of the thinned substrate at this stage therefore comprises the perforated grid, the P + implantation of shallow depth and an anti-reflection layer in the openings of the grid, and a deeper P + implantation under the metal of the grid.
- a deeper implantation operation is made initially and then part of the implanted thickness. For this we proceed as follows: first depositing a protective thin oxide layer, the implantation P is carried out through the oxide. Then the oxide is removed, and the aluminum layer is deposited directly. A resin mask is formed to etch the aluminum layer according to the open grid pattern, the silicon surface is etched into the apertures of the grid to remove a portion of the thickness of the implanted layer. Then, we deposits a uniform antireflection layer (for example based on silicon nitride) on the grid and on the silicon surface.
- a uniform antireflection layer for example based on silicon nitride
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Abstract
The invention relates to electronic image sensors provided with a matrix array of photosensitive points, in particular to large-size sensors (several centimetres on side) which operate with a high-sampling frequency. The inventive image sensor comprises a transfer substrate (20), a thinned semiconductor substrate (12) provided with a photosensitive area array and associated electronic circuits embodied on the front face thereof. An opaque metal layer which is substantially conductive, perforated and provided with openings opposite to each photosensitive area is formed on the rear face of said thinned substrate, wherein said metal layer forms an aperture grid (30) which is arranged in front of the photosensitive matrix array and provided with an electrical connection for supplying an uniform potential to the rear face of the thinned substrate in front of the entire matrix array. Conductive via holes are formed in the semiconductor substrate for connecting said layer to metal pads (14) formed on the front face of the substrate prior to be transferred to the transfer substrate. The invention makes it possible to improve the performance of the high-sampling frequency sensor by means of said metal layer.
Description
CAPTEUR D'IMAGE A SUBSTRAT SEMICONDUCTEUR AMINCI AVEC IMAGE SENSOR WITH SEMICONDUCTOR SUBSTRATE AMINCI WITH
METALLISATION ARRIEREREAR METALLIZATION
L'invention concerne les capteurs d'image électroniques à réseau matriciel de points photosensibles, et plus particulièrement ceux qui sont de grande dimension (plusieurs centimètres de côté) et qui travaillent à fréquence d'échantillonnage rapide. On entend par fréquence d'échantillonnage la fréquence à laquelle sont lus les points d'image. Elle dépend du nombre de points par ligne, du nombre de lignes, et de la fréquence de trame (typiquement 25 Hz ou 30Hz pour un capteur d'images vidéo). La fréquence d'échantillonnage est d'autant plus élevée qu'il y a plus de points dans le réseau matriciel. II existe maintenant des capteurs dits à substrat semiconducteur aminci, qui ont été conçus pour pouvoir être éclairés par la face arrière notamment en vue d'améliorer la colorimétrie des capteurs d'image en couleurs. Les circuits électroniques de capture d'image sont réalisés sur la face avant d'un substrat de silicium d'épaisseur classique (plusieurs centaines de micromètres d'épaisseur), après quoi ce substrat est reporté par sa face avant sur un substrat de report, et le substrat semiconducteur est aminci jusqu'à quelques micromètres d'épaisseur. L'éclairage par la face arrière permet d'éviter une dispersion des photons dans les couches métalliques de face avant et donc une diaphotie entre pixels voisins, donc à une mauvaise colorimétrie dans le cas de capteurs en couleur puisque les pixels voisins sont de couleurs différentes ; la faible épaisseur de substrat aminci permet d'éviter que les électrons engendrés par la lumière ne se dispersent dans le substrat et n'aboutissent aussi à une diaphotie.The invention relates to electronic image sensors with a matrix network of photosensitive points, and more particularly those which are large (several centimeters on the side) and which work at a fast sampling rate. The frequency of sampling is the frequency at which the image points are read. It depends on the number of points per line, the number of lines, and the frame rate (typically 25 Hz or 30 Hz for a video image sensor). The sampling frequency is all the higher as there are more points in the matrix network. There are now so-called thin-film semiconductor sensors, which have been designed to be illuminated by the rear face in particular to improve the colorimetry of the color image sensors. The image capture electronic circuits are formed on the front face of a silicon substrate of conventional thickness (several hundred micrometers thick), after which this substrate is carried by its front face on a transfer substrate, and the semiconductor substrate is thinned to a few microns thick. The illumination by the rear face makes it possible to avoid scattering of the photons in the metal layers of the front face and thus a crosstalk between neighboring pixels, therefore to a bad colorimetry in the case of color sensors since the neighboring pixels are of different colors. ; the small thickness of the thinned substrate makes it possible to prevent the electrons generated by the light from dispersing in the substrate and also from producing a crosstalk.
On s'est aperçu que des capteurs à substrat aminci de grandes dimensions pouvaient présenter des défauts importants à fréquence d'échantillonnage élevée, et on a identifié qu'une cause potentielle de ces défauts était la résistivité trop grande du substrat, dont l'effet s'accentue d'autant plus que le substrat est peu dopé, peu épais et de grande surface. Le faible dopage est nécessaire pour éviter que les électrons engendrés par la lumière ne se recombinent rapidement : ils doivent être capturés par les photodiodes en regard desquels ils sont générés. La dimension du capteur
est liée à la sensibilité (taille des pixels) et à la résolution (nombre de pixels) désirées ; la fréquence d'échantillonnage est d'autant plus élevée que le nombre de pixels est élevé, pour assurer une transmission d'image complète en un temps suffisamment bref. Pour éviter ou limiter les défauts dus à l'amincissement dans les capteurs de grande dimension fonctionnant à fréquence d'échantillonnage élevée, l'invention propose de déposer sur la face arrière du capteur aminci une couche métallique à forte conductivité (en pratique de l'aluminium), ajourée en regard des éléments photosensibles constitués sur la face avant. Par conséquent, l'invention propose un nouveau procédé de fabrication de capteur et un nouveau capteur d'image à substrat aminci.It has been found that large-sized thin-film sensors can exhibit large defects at high sampling rates, and one potential cause of these defects has been identified as the excessive resistivity of the substrate, the effect of which is accentuates the more so as the substrate is little doped, not very thick and of large surface. Low doping is necessary to prevent the electrons generated by light from recombining rapidly: they must be captured by the photodiodes against which they are generated. The size of the sensor is related to the desired sensitivity (pixel size) and resolution (number of pixels); the sampling frequency is even higher than the number of pixels is high, to ensure a complete image transmission in a sufficiently short time. To avoid or limit the defects due to thinning in large sensors operating at high sampling frequency, the invention proposes to deposit on the rear face of the thinned sensor a metal layer with high conductivity (in practice the aluminum), openwork facing the photosensitive elements formed on the front face. Accordingly, the invention provides a new sensor manufacturing method and a new thin-filmed image sensor.
Le procédé de fabrication d'un capteur d'image à substrat aminci comporte :The method of manufacturing a thin-filmed image sensor comprises:
- la formation, à partir de la face avant d'une tranche de matériau semiconducteur, d'une matrice de zones photosensibles et de circuits électroniques associés,the formation, from the front face of a slice of semiconductor material, of a matrix of photosensitive zones and associated electronic circuits,
- le report de la tranche par sa face avant contre la face avant d'un substrat de support,the transfer of the wafer by its front face against the front face of a support substrate,
- l'élimination, à partir de la face arrière de la tranche de matériau semiconducteur, de la majeure partie de l'épaisseur de cette tranche, laissant subsister sur le substrat une fine couche semiconductrice comprenant, sur sa face avant, la matrice photosensible et les circuits associés, ce procédé étant caractérisé en ce que, postérieurement à cette élimination, on dépose une couche métallique opaque fortement conductrice (en pratique de l'aluminium), et on grave des ouvertures dans cette couche métallique pour éliminer la couche en regard de chacune des zones photosensibles, la couche métallique constituant, en regard de la matrice photosensible, une grille ajourée à continuité électrique permettant d'amener un potentiel uniforme sur la face arrière de la tranche semiconductrice amincie en regard de toute la matrice.the elimination, from the rear face of the slice of semiconductor material, of the major part of the thickness of this slice, leaving on the substrate a thin semiconductor layer comprising, on its front face, the photosensitive matrix and the associated circuits, this method being characterized in that, after this elimination, depositing a highly conductive opaque metal layer (in practice aluminum), and openings are etched in this metal layer to eliminate the layer opposite each of the photosensitive zones, the metallic layer constituting, opposite the photosensitive matrix, a perforated grid with electrical continuity making it possible to bring a uniform potential onto the rear face of the thinned semiconductor wafer facing the entire matrix.
Dans tout ce qui précède et dans tout ce qui suit, on appellera face avant de la tranche amincie ou face avant du substrat aminci la face sur laquelle ont été formés, par dépôts et gravures successives, la matrice photosensible et les circuits électroniques associés. La face arrière de la
tranche amincie ou du substrat aminci est l'autre face, celle qui a subi l'usinage d'amincissement. C'est par la face arrière que le capteur reçoit une image lumineuse à convertir en image électronique. C'est la face arrière qui porte la couche métallique (aluminium) ajourée. La couche métallique reste de préférence présente mais non ajourée en regard des circuits électroniques associés à la matrice, pour servir de masque protégeant ces circuits de la lumière. Sans être à proprement parler ajourée, cette couche peut cependant être divisée en zones séparées, isolées électriquement les unes des autres, notamment dans le cas où le métal doit servir à la formation de plots d'entrée/sortie dans une des variantes de l'invention.In all of the foregoing and in all that follow, the face on which the photosensitive matrix and the associated electronic circuits have been formed, by successive deposits and etchings, will be called the front face of the thinned or front face of the thinned substrate. The back side of the thinned slice or thinned substrate is the other side, the one that has undergone thinning machining. It is through the back side that the sensor receives a bright image to be converted into an electronic image. This is the back side that carries the openwork metal layer (aluminum). The metal layer preferably remains present but not perforated with respect to the electronic circuits associated with the matrix, to serve as a mask protecting these circuits from light. Without being properly perforated, this layer can however be divided into separate zones, electrically insulated from each other, especially in the case where the metal is to be used for the formation of input / output pads in one of the variants of the invention.
De préférence, après avoir aminci la tranche et avant de déposer la couche métallique, on augmente superficiellement le dopage de la face arrière de la tranche, en créant une couche surdopée dont l'épaisseur est une faible fraction de l'épaisseur résiduelle de la tranche. De préférence aussi, après la réalisation des ouvertures de la couche métallique, on élimine, dans les ouvertures, au moins une partie de l'épaisseur de la couche semiconductrice ainsi surdopée.Preferably, after having thinned the wafer and before depositing the metal layer, the doping of the rear face of the wafer is superficially increased, creating an overdoped layer whose thickness is a small fraction of the residual thickness of the wafer. . Also preferably, after making the openings of the metal layer, is removed in the openings, at least a portion of the thickness of the semiconductor layer and overdoped.
De préférence aussi, avant le dépôt de la couche métallique fortement conductrice, on ouvre des vias dans la tranche semiconductrice, sur la majeure partie de l'épaisseur de celle-ci, jusqu'à mettre à nu des plages métalliques qui ont été formées à partir de la face avant dans les opérations de réalisation de la matrice et des circuits électroniques associés ; le dépôt de la couche métallique dans les vias permet de relier électriquement des portions de cette couche à ces plages métalliques.Also preferably, prior to the deposition of the highly conductive metal layer, vias are opened in the semiconductor wafer, over most of the thickness of the latter, until bare metal strips which have been formed to from the front face in the operations of producing the matrix and the associated electronic circuits; the deposition of the metal layer in the vias makes it possible to electrically connect portions of this layer to these metal areas.
Pour un capteur couleur, on dépose ensuite des filtres colorés. Dans une première variante du procédé de fabrication, après découpage de la tranche en capteurs individuels, on utilise au moins une portion de la couche métallique, isolée de la grille ajourée et reliée à une plage métallique, comme plot de soudure pour la connexion du capteur d'image à l'extérieur. On utilise au moins une autre portion de la couche métallique, reliée à la grille ajourée et reliée à une autre plage métallique, pour établir un potentiel identique sur la grille et sur une partie de circuit électronique réalisé sur la face avant.
Dans une deuxième variante, le substrat de report est un substrat provisoire ; un substrat définitif transparent est collé sur la face arrière de la tranche ; le substrat provisoire est éliminé ; les plages métalliques reliées à des vias sont dénudées par la face avant de la tranche. Après découpage de la tranche en capteurs d'image individuels, au moins une de ces plages, reliée par un via à la grille ajourée, sert de plot de soudure pour une connexion extérieure afin d'amener de l'extérieur, à travers la plage métallique et le via, un potentiel de référence sur la grille ajourée.For a color sensor, colored filters are then deposited. In a first variant of the manufacturing method, after cutting the wafer into individual sensors, at least a portion of the metal layer, isolated from the perforated grid and connected to a metal pad, is used as a solder pad for the connection of the sensor. image outside. At least one other portion of the metal layer, connected to the perforated grid and connected to another metal pad, is used to establish an identical potential on the gate and on an electronic circuit part made on the front face. In a second variant, the transfer substrate is a temporary substrate; a transparent final substrate is adhered to the rear face of the wafer; the temporary substrate is eliminated; the metal beaches connected to vias are stripped by the front face of the slice. After cutting the wafer into individual image sensors, at least one of these ranges, connected by a via to the perforated grid, serves as a solder pad for an external connection to bring from the outside, through the beach metallic and the via, a reference potential on the perforated grid.
Le capteur d'image selon l'invention comprend, sur un substrat de report, un substrat semiconducteur aminci sur la face avant duquel sont formés une matrice de zones photosensibles et des circuits électroniques associés, et sur la face arrière duquel est formée une couche conductrice métallique opaque ajourée comportant des ouvertures en regard de chaque zone photosensible, la couche métallique constituant, en regard de la matrice photosensible, une grille ajourée à continuité électrique permettant d'amener un potentiel uniforme, sur la face arrière du substrat aminci, en regard de toute la matrice.The image sensor according to the invention comprises, on a transfer substrate, a thinned semiconductor substrate on the front face of which are formed a matrix of photosensitive zones and associated electronic circuits, and on the rear face of which is formed a conductive layer. perforated opaque metal having apertures facing each photosensitive zone, the metal layer constituting, facing the photosensitive matrix, a perforated grid with electrical continuity for bringing a uniform potential on the rear face of the thinned substrate, facing the whole matrix.
Au moins un via conducteur est prévu dans toute l'épaisseur du substrat semiconducteur aminci pour relier électriquement des portions de la couche métallique à des plages métalliques faisant partie des circuits électroniques associés à la matrice.At least one conductive via is provided throughout the thickness of the thinned semiconductor substrate to electrically connect portions of the metal layer to metal pads forming part of the electronic circuits associated with the matrix.
Dans une première réalisation de l'invention la face avant du substrat aminci est collée contre le substrat de report, et c'est la face arrière du substrat aminci, face qui porte la couche conductrice métallique opaque, qui reste accessible à la fin de la fabrication du capteur d'image, alors que la face avant est inaccessible, enfermée entre le substrat aminci et le substrat de report. Des portions de la couche métallique servent de plots de soudure pour la connexion avec l'extérieur (certaines sont reliées à la grille ajourée, d'autres en sont isolées électriquement). Dans une autre réalisation, le substrat de report est un substrat transparent et c'est la face arrière du substrat aminci qui est collée contre le substrat. La face avant du substrat aminci reste accessible après la fin de la fabrication ; la face arrière et sa couche d'aluminium ajourée deviennent inaccessibles, enfermées entre le substrat aminci et le substrat définitif
transparent. C'est à travers le substrat transparent que le capteur reçoit une image lumineuse à convertir.In a first embodiment of the invention, the front face of the thinned substrate is bonded against the transfer substrate, and it is the rear face of the thinned substrate, which surface bears the opaque metallic conductive layer, which remains accessible at the end of the manufacturing of the image sensor, while the front face is inaccessible, enclosed between the thinned substrate and the transfer substrate. Portions of the metal layer serve as solder pads for the connection with the outside (some are connected to the perforated grid, others are electrically isolated). In another embodiment, the transfer substrate is a transparent substrate and it is the rear face of the thinned substrate which is bonded against the substrate. The front face of the thinned substrate remains accessible after the end of manufacture; the rear face and its perforated aluminum layer become inaccessible, enclosed between the thinned substrate and the final substrate transparent. It is through the transparent substrate that the sensor receives a luminous image to be converted.
De préférence, le substrat semiconducteur est superficiellement surdopé sur une faible profondeur de la face arrière, au moins sous la couche ajourée d'aluminium, avec une quantité d'impuretés de dopage plus élevée sous cette couche que dans les ouvertures de cette couche.Preferably, the semiconductor substrate is superficially overdoped on a shallow depth of the rear face, at least under the perforated layer of aluminum, with a higher amount of doping impurities beneath this layer than in the openings of this layer.
La couche d'aluminium est de préférence revêtue d'un dépôt noir réduisant la réflectivité de la couche. Le substrat aminci peut être recouvert, dans les ouvertures, d'une couche anti-reflet. Le capteur selon l'invention peut être un capteur d'image en couleur. Des filtres colorés sont de préférence déposés sur face arrière du substrat aminci, sur la couche d'aluminium ajourée ; le dépôt est fait postérieurement au dépôt et à la gravure de celle-ci. Il est fait avant report sur le substrat transparent définitif dans le cas où le procédé comporte d'abord un report par la face avant sur un substrat provisoire puis un report par la face arrière sur un substrat définitif.The aluminum layer is preferably coated with a black deposit reducing the reflectivity of the layer. The thinned substrate may be covered in the openings with an anti-reflection layer. The sensor according to the invention may be a color image sensor. Colored filters are preferably deposited on the back side of the thinned substrate, on the perforated aluminum layer; the deposit is made after the deposit and etching thereof. It is done before transfer to the final transparent substrate in the case where the method comprises first a transfer by the front face on a temporary substrate and then a transfer by the rear face on a final substrate.
D'autres caractéristiques et avantages de l'invention apparaîtront à la lecture de la description qui suit et qui est faite en référence aux dessins annexés dans lesquels :Other features and advantages of the invention will appear on reading the description which follows and which is given with reference to the appended drawings in which:
- la figure 1 représente schématiquement une tranche semiconductrice sur la face avant de laquelle on a formé des circuits électroniques parmi lesquels une matrice photosensible et des plages métalliques ; - les figures 2 à 7 représentent les étapes du procédé selon l'invention dans une première variante de réalisation ;- Figure 1 shows schematically a semiconductor wafer on the front side of which formed electronic circuits among which a photosensitive matrix and metal plates; - Figures 2 to 7 show the steps of the method according to the invention in a first embodiment;
- la figure 8 représente un capteur d'image selon l'invention, obtenu dans cette première variante ;FIG. 8 represents an image sensor according to the invention, obtained in this first variant;
- les figures 9 à 11 représentent les étapes du procédé dans une deuxième variante ;- Figures 9 to 11 show the process steps in a second variant;
- la figure 12 représente un capteur selon l'invention dans la deuxième variante, reporté sur une embase par une méthode dite "flip-chip" ;FIG. 12 represents a sensor according to the invention in the second variant, carried on a base by a so-called "flip-chip" method;
- la figure 13 représente un capteur selon l'invention dans la deuxième variante, reporté sur une embase par une méthode avec soudure de fils de connexion.
Pour réaliser un capteur d'image sur un substrat aminci, on part d'une tranche de silicium 10 dont la partie supérieure est constituée par une couche épitaxiale 12 peu dopée (en général de type P, ordre de grandeur 1013 atomes/cm3) de quelques micromètres ou quelques dizaines de micromètres d'épaisseur. On réalise classiquement sur la face avant de cette tranche un ensemble de capteurs d'image destinés à être ultérieurement séparés en puces comportant chacune un capteur individuel. Chaque capteur comporte un réseau matriciel de zones photosensibles, des interconnexions en lignes et en colonnes, des circuits électroniques d'adressage, des circuits de recueil des charges photogénérées, des circuits de conversion de ces charges en signaux électroniques, et des plages métalliques destinées à être reliées à des connexions extérieures du capteur ; les connexions extérieures sont destinées à l'alimentation et à la commande des circuits électroniques du capteur ainsi qu'au recueil des signaux électroniques représentant les images détectées par le capteur. Deux plages métalliques 14 et 15 ont été représentées à titre d'illustration sur la figure 1.FIG. 13 represents a sensor according to the invention in the second variant, carried on a base by a method with soldering of connection wires. To produce an image sensor on a thinned substrate, one starts from a silicon wafer 10 whose upper part is constituted by a slightly doped epitaxial layer 12 (generally of type P, order of magnitude 10 13 atoms / cm 3 ) of a few micrometers or a few tens of micrometers thick. A set of image sensors intended to be subsequently separated into chips, each comprising an individual sensor, is conventionally made on the front face of this slice. Each sensor comprises a matrix array of photosensitive zones, interconnections in lines and columns, electronic addressing circuits, photogenerated charge collection circuits, circuits for converting these charges into electronic signals, and metal pads intended for be connected to external connections of the sensor; the external connections are intended for supplying and controlling the electronic circuits of the sensor as well as for collecting the electronic signals representing the images detected by the sensor. Two metal areas 14 and 15 have been shown for purposes of illustration in FIG.
Les capteurs sont faits par des opérations collectives classiques de microélectronique : dépôts de couches isolantes ou conductrices ou semiconductrices, dopages par implantation, opérations thermiques, gravures, etc. Toutes ces opérations sont faites à partir de la face avant de la tranche qui est située en haut sur la figure 1.The sensors are made by conventional collective microelectronics operations: deposits of insulating or conductive or semiconducting layers, doping by implantation, thermal operations, etchings, etc. All these operations are done from the front face of the slice which is located at the top in Figure 1.
Parmi les opérations qui sont réalisées à partir de la face avant de la tranche pour aboutir à un capteur conforme à l'invention, il y a la formation d'une ou plusieurs couches métalliques d'interconnexion en niveaux superposés, parmi lesquelles l'une au moins permet de constituer les plages métalliques telles que 14 et 15.Among the operations that are performed from the front face of the wafer to result in a sensor according to the invention, there is the formation of one or more interconnect metal layers in superimposed levels, among which one at least makes it possible to constitute the metal areas such as 14 and 15.
Il y a à ce stade deux grandes possibilités de fabrication qui toutes deux commencent par le report de la tranche par sa face avant sur un substrat de report et l'amincissement de la tranche par sa face arrière jusqu'à ne laisser subsister pratiquement que la couche épitaxiale 12 ou même une partie seulement de l'épaisseur de cette couche. La tranche amincie n'aura plus qu'une épaisseur de quelques micromètres, contenant l'ensemble des circuits fabriqués précédemment à partir de la face avant ; cette épaisseur ne
permettrait pas d'assurer une tenue mécanique de la tranche pendant les opérations de fabrication collective s'il n'y avait pas le substrat de report ; la tenue mécanique est assurée par le substrat de report.At this stage, there are two major manufacturing possibilities, both of which begin with the slice being deflected by its front face on a transfer substrate and the thinning of the slice by its rear face until it leaves practically nothing but the epitaxial layer 12 or even only a portion of the thickness of this layer. The slice thinned will have a thickness of a few micrometers, containing all the circuits previously manufactured from the front; this thickness does not would not ensure mechanical strength of the slice during collective manufacturing operations if there was no transfer substrate; the mechanical strength is provided by the transfer substrate.
Par la suite, dans une première variante le substrat de report est un substrat définitif, la face arrière de la tranche amincie est accessible et peut être revêtue de filtres colorés ; elle porte des métallisations pour l'accès électrique extérieur et ces métallisations doivent être reliées électriquement aux circuits de la face avant par des vias conducteurs dont on parlera plus loin, et notamment des vias en regard de plages métalliques telles que 14 et 15 ; l'éclairage du capteur d'image se fait par la face arrière, accessible, de la tranche amincie. Dans une deuxième variante, le substrat de report est un substrat provisoire ; après amincissement de la tranche et dépôt de filtres colorés sur sa face arrière (pour un capteur couleur), on reporte à nouveau celle-ci, mais cette fois par sa face arrière, sur un substrat définitif, et on enlève le substrat provisoire ; la face arrière n'est plus accessible ; la face avant redevient accessible et les plages métalliques telles que 14 et 15 peuvent servir de plots d'accès extérieur puisqu'ils affleurent sur cette face avant ; des vias conducteurs sont encore présents comme on l'expliquera plus loin ; l'éclairage du capteur se fait encore par la face arrière et le substrat définitif doit être transparent.Subsequently, in a first variant, the transfer substrate is a definitive substrate, the rear face of the thinned wafer is accessible and may be coated with colored filters; it carries metallizations for external electrical access and these metallizations must be electrically connected to the circuits of the front face by conductive vias which will be discussed later, and in particular vias opposite metallic areas such as 14 and 15; the illumination of the image sensor is via the accessible rear face of the thinned slice. In a second variant, the transfer substrate is a temporary substrate; after thinning of the wafer and deposition of colored filters on its rear face (for a color sensor), it is carried back again, but this time by its rear face, on a final substrate, and the temporary substrate is removed; the back side is no longer accessible; the front face becomes accessible again and the metal areas such as 14 and 15 can serve as external access pads since they are flush with this front face; conductive vias are still present as will be explained later; the illumination of the sensor is still done by the rear face and the final substrate must be transparent.
On s'intéresse d'abord à la première variante et on va décrire les étapes successives de fabrication correspondant à cette variante.We first look at the first variant and we will describe the successive manufacturing steps corresponding to this variant.
La figure 2 représente le report de la tranche semiconductrice par sa face avant sur un substrat de report définitif 20. La tranche est retournée sur la figure 2, c'est-à-dire que sa face avant est maintenant en bas de la figure tandis que la face arrière est en haut. Le collage est fait avec matière adhésive ou par adhérence moléculaire sans matière adhésive. Dans ce dernier cas, on prévoit de préférence de revêtir au préalable la face avant d'une couche de planarisation 16 avant de la coller contre la face avant du substrat de report ; le substrat de report a pu lui-même être revêtu, si nécessaire, d'une couche de planarisation avant l'étape de collage.FIG. 2 shows the transfer of the semiconductor wafer by its front face onto a definitive transfer substrate 20. The wafer is turned over in FIG. 2, that is to say that its front face is now at the bottom of the figure while that the back side is up. The bonding is done with adhesive material or by molecular adhesion without adhesive material. In the latter case, it is preferably provided to first coat the front face of a planarization layer 16 before gluing it against the front face of the transfer substrate; the transfer substrate could itself be coated, if necessary, with a planarization layer before the bonding step.
La tranche semiconductrice est ensuite amincie à quelques micromètres d'épaisseur. L'amincissement se fait par usinage mécanique complété par un polissage mécanique et/ou chimique. La tranche amincie sera à partir de là désignée par 12 puisqu'elle ne comprend plus, en
pratique, que la couche épitaxiale 12, et même une fraction seulement de la couche épitaxiale originale.The semiconductor wafer is then thinned to a few microns thick. Thinning is done by mechanical machining supplemented by mechanical and / or chemical polishing. The slice thinned will be from there designated by 12 since it does not include, in practical, that the epitaxial layer 12, and even a fraction only of the original epitaxial layer.
On dope alors superficiellement la face arrière de la tranche amincie, avec une impureté de même type que la couche semiconductrice qui reçoit ce dopage (donc une impureté P si la couche est de type P). Ce dopage supplémentaire P+ est destiné à faciliter le contact électrique ultérieur avec une couche métallique. Le dopage est effectué par implantation ionique superficielle, sur une faible profondeur, et il est préférable de prévoir, avant l'opération d'implantation, un dépôt d'oxyde de silicium mince (SiO, quelques centaines de nanomètres), qui évite d'endommager la surface du silicium. Cette couche d'oxyde mince est enlevée ensuite. La figure 3 représente la tranche amincie sur son substrat de report, à ce stade de la fabrication. La couche superficielle implantée (P+) est désignée par 22. Le dopage peut être de l'ordre de 1015 atomes/cm3. On procède alors à une opération de photolithographie pour ouvrir des vias sur toute l'épaisseur de la tranche amincie, afin de mettre à nu des plages métalliques telles que 14 et 15 qui ont été formées à partir de la face avant de la tranche semiconductrice dans les étapes précédant le report. Sur la figure 4, on a représenté un via 24 en regard de la plage métallique 14 et un via 25 en regard de la plage 15. D'autres vias peuvent être prévus. Les vias servent à établir des passages pour relier électriquement les plages métalliques de la face avant à des conducteurs qui vont maintenant être formés sur la face arrière.The back surface of the thinned slice is then superficially doped with an impurity of the same type as the semiconductor layer which receives this doping (hence an impurity P if the layer is of P type). This additional doping P + is intended to facilitate the subsequent electrical contact with a metal layer. The doping is carried out by superficial ion implantation, on shallow depth, and it is preferable to provide, before the implantation operation, a deposit of thin silicon oxide (SiO, a few hundred nanometers), which avoids damage the surface of the silicon. This thin oxide layer is then removed. Figure 3 shows the thinned slice on its transfer substrate at this stage of manufacture. The implanted surface layer (P +) is denoted by 22. The doping can be of the order of 10 15 atoms / cm 3 . A photolithography operation is then performed to open vias over the entire thickness of the thinned wafer, in order to expose metal strips such as 14 and 15 which have been formed from the front face of the semiconductor wafer in the steps preceding the postponement. In Figure 4, there is shown a via 24 opposite the metal strip 14 and a via 25 opposite the range 15. Other vias can be provided. The vias are used to establish passages to electrically connect the metal pads of the front face to conductors that will now be formed on the back side.
On dépose alors une couche métallique fortement conductrice et opaque 26 (en pratique de l'aluminium) sur la face arrière de la tranche. La couche d'aluminium 26 repose sur la face arrière implantée de la tranche amincie 12, et elle vient à l'intérieur des vias 24 et 25 en contact avec les plots 14 et 15 respectivement. En dehors des vias, le contact entre le silicium et l'aluminium est un contact ohmique. La figure 4 représente la tranche à ce stade. Les vias ont été représentés comme des tranchées à flancs inclinés avec de l'aluminium déposé sur ces flancs ; cependant, si la tranche amincie ne fait que quelques micromètres d'épaisseur, les vias peuvent être constitués par des tranchées étroites à flancs verticaux, gravées par attaque plasma, qui se comblent d'aluminium lors du dépôt de la couche d'aluminium.
On peut à ce stade envisager d'effectuer un dépôt noir sur la couche d'aluminium, pour réduire le coefficient de réflexion de ce dernier.A highly conductive and opaque metal layer 26 (in practice aluminum) is then deposited on the rear face of the wafer. The aluminum layer 26 rests on the implanted rear face of the thinned wafer 12, and it comes inside the vias 24 and 25 in contact with the pads 14 and 15 respectively. Outside the vias, the contact between the silicon and the aluminum is an ohmic contact. Figure 4 shows the slice at this stage. The vias were represented as sloping flank trenches with aluminum deposited on these flanks; however, if the thinned slice is only a few micrometers thick, the vias may be constituted by vertical trenches with vertical flanges etched by plasma etching, which are filled with aluminum during the deposition of the aluminum layer. One can at this stage consider making a black deposit on the aluminum layer, to reduce the reflection coefficient of the latter.
On grave alors par photolithographie dans la couche d'aluminium 26 un réseau d'ouvertures distribuées selon un motif régulier. Les ouvertures sont formées en regard des zones photosensibles de la matrice afin qu'elles puissent être éclairées ; elles seront en effet éclairées par le côté où se trouve cette couche d'aluminium. L'aluminium qui subsiste après cette gravure comporte plusieurs zones, parmi lesquelles une grille ajourée 30, électriquement continue, qui permet de répartir sur toute la surface arrière du silicium, dans la région correspondant à la matrice photosensible et notamment en son centre, un potentiel constant imposé de l'extérieur. Le réseau d'aluminium qui subsiste peut-être un réseau de fines lignes ou de fines colonnes ou un réseau croisé de lignes et de colonnes comme on le voit à la figure 6. Les ouvertures dans l'aluminium sont de préférence réparties régulièrement avec le même pas que les pixels de manière que la zone photosensible correspondant à chaque pixel soit la moins masquée possible par le réseau croisé de lignes et colonnes d'aluminium : l'aluminium subsiste uniquement sur le pourtour de chaque pixel photosensible sans le masquer. Les lignes et colonnes de la grille ajourée peuvent avoir une largeur de 0,25 à 1 micromètre pour des pixels ayant un pas de quelques micromètres ; elles peuvent être plus larges pour des pixels ayant un pas de plus de 10 micromètres.Photolithography is then etched in the aluminum layer 26 an array of openings distributed in a regular pattern. The openings are formed opposite the photosensitive areas of the matrix so that they can be illuminated; they will be illuminated by the side where this layer of aluminum is. The aluminum that remains after this etching comprises several zones, among which a perforated grid 30, electrically continuous, which makes it possible to distribute over the entire back surface of the silicon, in the region corresponding to the photosensitive matrix and in particular at its center, a potential constant imposed from the outside. The aluminum network that may remain a network of thin lines or thin columns or a cross network of rows and columns as seen in Figure 6. The openings in the aluminum are preferably distributed regularly with the not even the pixels so that the photosensitive zone corresponding to each pixel is the least masked possible by the crossed network of lines and columns of aluminum: the aluminum remains only around the perimeter of each photosensitive pixel without masking it. The rows and columns of the perforated grid may have a width of 0.25 to 1 micrometer for pixels having a pitch of a few micrometers; they may be wider for pixels having a pitch of more than 10 micrometers.
Bien que la grille ajourée risque de masquer une partie de la surface photosensible, on constate qu'elle a un rôle positif de réduction de la diaphotie entre pixels voisins et donc de la colorimétrie puisqu'elle réduit la proportion de lumière émanant d'un filtre correspondant à un pixel et risquant de tomber sur un pixel voisin.Although the perforated grid may obscure a part of the photosensitive surface, it is found that it has a positive role of reducing the crosstalk between neighboring pixels and thus of the colorimetry since it reduces the proportion of light emanating from a filter corresponding to a pixel and likely to fall on a neighboring pixel.
Outre la grille ajourée d'aluminium 30 subsistent sur la face arrière de la tranche les métailisations 32 dans les vias tels que 24 et 25, éventuellement prolongées par des plots métalliques destinés à la soudure ultérieure de fils de connexion (sauf si les fils peuvent être soudés directement au fond des vias). Sur la figure 5, un plot de soudure 35 est représenté, connecté à la plage 15 par la métallisation 32 du via 25.In addition to the perforated aluminum grid 30 remain on the rear face of the slice the meta-formations 32 in the vias such as 24 and 25, possibly extended by metal studs for the subsequent soldering of connection wires (unless the wires can be welded directly to the bottom of the vias). In FIG. 5, a solder pad 35 is shown, connected to the pad 15 by the metallization 32 of the via 25.
Il y aura plusieurs plots d'accès extérieur tels que 35 sur la puce. Ces plots sont isolés électriquement les uns des autres puisqu'ils
correspondent à des fonctions électriques différentes. Un plot au moins est relié électriquement à la grille d'aluminium 30 recouvrant la matrice pour lui apporter un potentiel de référence venant de l'extérieur (potentiel de masse par exemple). Des vias conducteurs tels que le via 24, qui ne correspondent pas forcément directement à des plots de connexion extérieure, peuvent faire partie d'une série de vias distribués (en principe à la périphérie de la matrice) pour relier de place en place la grille d'aluminium à des conducteurs de face avant (toujours dans un souci d'homogénéité de distribution de potentiels sur la surface de la puce).There will be several outside access pads such as 35 on the chip. These pads are electrically isolated from each other since they correspond to different electrical functions. At least one stud is electrically connected to the aluminum grid 30 covering the matrix to provide it with a reference potential coming from outside (mass potential for example). Conductive vias such as via 24, which do not necessarily correspond directly to external connection pads, can be part of a series of distributed vias (in principle at the periphery of the matrix) to connect the grid from place to place aluminum to front-panel drivers (always with a view to homogeneity of potential distribution on the surface of the chip).
La figure 6 représente, en vue de dessus côté face arrière, la configuration du motif d'aluminium pour un capteur individuel. On y voit les ouvertures correspondant à chaque pixel, dans la grille ajourée 30 qui recouvre toute la partie centrale du capteur. La partie 38 qui entoure immédiatement la matrice est continûment opaque, pour masquer les circuits électroniques situés à la périphérie de la matrice ; elle est reliée électriquement à la grille ajourée. Dans cette partie, on voit les vias tels que le via 24. Enfin, autour de cette partie 38, on voit des plots de soudure tels que 35 pour les connexions extérieures du capteur. Ils sont isolés électriquement les uns des autres et sont reliés chacun par un via respectif à une plage métallique de la face avant ; l'un d'eux peut être relié à la grille ajourée 30.Figure 6 shows, in top view on the back side, the configuration of the aluminum pattern for an individual sensor. It shows the apertures corresponding to each pixel in the perforated grid 30 which covers the entire central portion of the sensor. The portion 38 which immediately surrounds the matrix is continuously opaque, to mask the electronic circuits located at the periphery of the matrix; it is electrically connected to the perforated grid. In this part, we see vias such as via 24. Finally, around this part 38, we see solder pads such as 35 for the external connections of the sensor. They are electrically isolated from each other and are each connected by a respective via to a metal pad of the front face; one of them can be connected to the perforated grid 30.
A ce stade de la fabrication, on grave de préférence uniformément (sans masque) le silicium sur une épaisseur correspondant à peu près à la profondeur de la couche implantée P+, afin de l'éliminer totalement ou partiellement dans les ouvertures de la grille d'aluminium. En effet, la lumière bleue pénètre peu profondément dans le silicium et les électrons qui seraient générés dans la couche P+ auraient du mal à être recueillis par les photodiodes de la matrice. L'implantation P+ ne subsiste alors que sous l'aluminium, où d'une part elle favorise le contact électrique entre la grille et la couche semiconductrice 12, et d'autre part elle limite les risques de migration d'aluminium dans la profondeur de la tranche amincie. L'implantation P+ peut aussi subsister un peu en dehors des ouvertures, mais avec une dose plus faible (ou une profondeur plus faible) que sous l'aluminium.
On peut envisager, à ce stade, de former dans les ouvertures, une couche anti-reflet ou une structure de couches superposées formant couche anti-reflet.At this stage of manufacture, the silicon is preferably uniformly etched (without a mask) to a thickness approximately corresponding to the depth of the implanted layer P +, in order to eliminate it completely or partially in the openings of the grid. aluminum. Indeed, the blue light penetrates shallow into the silicon and the electrons that would be generated in the P + layer would have difficulty to be collected by the photodiodes of the matrix. The implantation P + remains then only under the aluminum, where on the one hand it promotes the electrical contact between the gate and the semiconductor layer 12, and on the other hand it limits the risks of migration of aluminum in the depth of thinned slice. Implantation P + may also remain slightly outside openings, but with a lower dose (or a lower depth) than under aluminum. At this stage, it is conceivable to form in the openings an anti-reflection layer or a structure of superposed layers forming an anti-reflection layer.
Pour un capteur couleur, on procède alors aux opérations suivantes : dépôt d'une couche de planarisation transparente 40 (oxyde de silicium), dépôt et gravure de couches de filtres colorés 42 et dépôt d'une couche de protection transparente 44. On ouvre la couche de protection et la couche de planarisation pour dénuder des plages métalliques 35 de soudure de fils de connexion des capteurs. La figure 7 représente la structure collective à ce stade.For a color sensor, the following operations are then performed: deposition of a transparent planarization layer 40 (silicon oxide), deposition and etching of colored filter layers 42 and deposition of a transparent protective layer 44. protective layer and the planarization layer for stripping wire bonding metal pads of the sensors. Figure 7 shows the collective structure at this stage.
Après toutes ces opérations, effectuées collectivement, on peut procéder à la découpe de la tranche en puces individuelles correspondant chacune à un capteur d'image. Ces puces sont montées dans des boîtiers, et des fils de connexion sont soudés sur les plots de soudure dénudés 35. La figure 8 représente un capteur réalisé et monté sur une embase de boîtier 50 avec un fil de soudure 52. En utilisation, la lumière arrive par le haut, c'est-à- dire par la face arrière de la puce de silicium, le substrat de report 20 étant collé sur l'embase.After all these operations, performed collectively, it is possible to cut the wafer into individual chips each corresponding to an image sensor. These chips are mounted in housings, and connection wires are soldered to the bare solder pads 35. FIG. 8 shows a sensor made and mounted on a housing base 50 with a solder wire 52. In use, the light arrives from above, that is to say from the rear face of the silicon chip, the transfer substrate 20 being stuck to the base.
On a ainsi décrit une première variante de réalisation de l'invention, qui aboutit à un capteur conforme à la figure 8.A first embodiment of the invention has thus been described, which results in a sensor according to FIG. 8.
On va maintenant décrire une deuxième variante en référence aux figures 9 à 13.A second variant will now be described with reference to FIGS. 9 to 13.
Les opérations décrites en référence aux figures 1 à 7 restent les mêmes, à l'exception - du fait que le substrat de report 20 est un substrat de report provisoire et doit pouvoir être enlevé ultérieurement de la tranche, soit par séparation, soit par usinage,The operations described with reference to FIGS. 1 to 7 remain the same, with the exception of the fact that the transfer substrate 20 is a temporary transfer substrate and must be able to be removed later from the wafer, either by separation or by machining. ,
- du fait que les vias tels que 25 et les plots de soudure 35 ne sont plus nécessaires car les plots de soudure seront constitués comme on le verra par les plages métalliques 15 qui ont été constituées à partir de la face avant de la tranche semiconductrice ; le dessin de ces plages doit bien entendu être prévu en conséquence ; les vias 24 destinés à relier électriquement la grille métallique 30 à une plage métallique 14 restent nécessaires, la plage 14 servant de
plot de soudure pour une connexion qui amène un potentiel de référence sur la grille ajourée 30 (connexion de masse par exemple).- Because the vias such as 25 and the solder pads 35 are no longer necessary because the solder pads will be constituted as will be seen by the metal pads 15 which were formed from the front of the semiconductor wafer; the drawing of these beaches must of course be planned accordingly; the vias 24 for electrically connecting the metal grid 30 to a metal strip 14 remain necessary, the range 14 serving as solder pad for a connection which brings a reference potential to the perforated grid 30 (mass connection for example).
En tenant compte de ces différences et à partir de la structure représentée à la figure 7, on colle (figure 9) sur la face arrière de la tranche semiconductrice amincie, revêtue du motif d'aluminium, des filtres colorésTaking into account these differences and from the structure shown in Figure 7, glue (Figure 9) on the back side of the thinned semiconductor wafer, coated with the aluminum pattern, color filters
(pour un capteur couleur) et de la couche de protection 44, un substrat de report définitif transparent 60 (en principe une plaquette de quartz). Le collage peut être fait avec apport de matière adhésive transparente, ou sans apport de matière adhésive, par adhérence moléculaire. Dans ce dernier cas, la couche de protection 44 doit servir de couche de planarisation ou bien il faut déposer au préalable sur la couche 44 une couche de planarisation.(For a color sensor) and the protective layer 44, a transparent final transfer substrate 60 (in principle a quartz wafer). The bonding can be done with the addition of transparent adhesive material, or without addition of adhesive material, by molecular adhesion. In the latter case, the protective layer 44 must serve as a planarization layer or it must first deposit on the layer 44 a planarization layer.
Après ce report sur le substrat définitif, on élimine (figure 10) le substrat de report provisoire, par décollement ou par usinage mécanique puis chimique. Cette opération est faite de manière à mettre à nu les plages métalliques 15 qui doivent servir de plots de soudure pour la connexion avec l'extérieur. S'il y avait une couche de planarisation 16 (cf. figure 2), l'épaisseur de celle-ci doit être réduite jusqu'à affleurement des plages 15.After this transfer to the final substrate, the temporary transfer substrate is removed (FIG. 10) by delamination or by mechanical and chemical machining. This operation is done so as to expose the metal pads 15 which must serve as solder pads for connection with the outside. If there was a planarization layer 16 (see Figure 2), the thickness of the latter must be reduced until the beaches 15 are flush with.
On peut déposer une couche de passivation 62 sur toute la face mise à nu, qui est, on le rappelle, la face avant de la tranche semiconductrice. Cette couche de passivation est alors gravée en regard des plages métalliques 15 qui vont servir de plots de soudure (figure 11).A passivation layer 62 may be deposited on the entire exposed face, which is, as recalled, the front face of the semiconductor wafer. This passivation layer is then etched opposite the metal areas 15 which will serve as solder pads (FIG. 11).
Après avoir effectué collectivement toutes ces opérations, on procède à la découpe de la tranche en puces individuelles correspondant chacune à un capteur d'image. Le capteur d'image est éclairé encore par la face arrière de la tranche, donc à travers le substrat de report transparent 60.After having collectively performed all these operations, the slice is cut into individual chips each corresponding to an image sensor. The image sensor is further illuminated by the rear face of the wafer, thus through the transparent transfer substrate 60.
Le capteur peut être monté sur une embase 50 selon la technique flip-chip dans laquelle les plots de soudure reçoivent des bossages soudables ("solder bumps" en anglais) ; la face avant de la puce est alors tournée vers l'embase et soudée sur celle-ci par l'intermédiaire des bossages. La lumière arrive par le côté (de l'embase) qui porte le capteurThe sensor can be mounted on a base 50 according to the flip-chip technique in which the solder pads receive weldable bosses ("solder bumps" in English); the front face of the chip is then turned towards the base and welded to it via the bosses. The light comes from the side (of the base) that carries the sensor
(figure 12).(Figure 12).
Le capteur peut aussi être classiquement monté selon la technique de soudure par fils ("wire-bonding") ; dans ce cas le substrat transparent 60 repose directement sur l'embase 50 (figure 13) et il est nécessaire que l'embase, si elle n'est pas transparente, comporte une
fenêtre en regard de la matrice photosensible du capteur ; la lumière arrive par l'autre côté de l'embase (côté opposé à celui qui porte le capteur).The sensor can also be conventionally mounted according to the wire-bonding technique; in this case the transparent substrate 60 rests directly on the base 50 (FIG. 13) and it is necessary that the base, if it is not transparent, comprises a window opposite the photosensitive matrix of the sensor; the light comes from the other side of the base (the opposite side to the one carrying the sensor).
Si on revient plus en détail sur l'opération de dépôt et gravure de la couche d'aluminium ajourée (figures 3 à 5), on peut procéder de plusieurs manières, dont deux exemples sont donnés ci-après :If we return in more detail to the operation of deposition and etching of the perforated aluminum layer (Figures 3 to 5), we can proceed in several ways, two examples are given below:
Dans une première manière, le principe est qu'avant dépôt de la couche métallique, on effectue une opération de dopage supplémentaire locale dans les zones qui seront recouvertes par la grille, à travers un masque complémentaire de celui qui définit les ouvertures de la grille lors de la gravure de celle-ci.In a first manner, the principle is that before deposition of the metal layer, an additional local doping operation is performed in the areas to be covered by the grid, through a mask complementary to that which defines the openings of the grid during of the engraving of it.
Pour cela, on dépose d'abord une couche d'oxyde de silicium mince destinée à protéger la surface de la couche épitaxiale amincie, puis on implante des impuretés de type P à faible dose dans le silicium à faible profondeur sous cette couche. Puis on enlève l'oxyde de silicium, et on dépose une couche anti-reflet (de préférence à base de nitrure de silicium). Ensuite, à travers un masque de résine complémentaire de celui qui définira ultérieurement le motif de grille ajourée, on grave la couche de nitrure là où il y aura la grille d'aluminium et on implante dans la zone non protégée par la résine et le nitrure une dose plus importante (en pratique plus profonde) d'impureté de type P qui se trouvera plus tard sous la grille ajourée.For this purpose, a thin silicon oxide layer is first deposited to protect the surface of the thinned epitaxial layer, and then low-dose P-type impurities are implanted in the silicon at a shallow depth below this layer. Then the silicon oxide is removed, and an antireflection layer (preferably based on silicon nitride) is deposited. Then, through a resin mask complementary to that which will later define the perforated grid pattern, the nitride layer is etched where there will be the aluminum grid and is implanted in the non-protected area by the resin and the nitride a larger dose (in practice deeper) P-type impurity that will be later under the perforated grid.
On dépose alors l'aluminium et on forme un nouveau masque de résine qui recouvre les zones d'aluminium à conserver. La surface du substrat aminci à ce stade comprend donc la grille ajourée, l'implantation P+ de faible profondeur et une couche anti-reflet dans les ouvertures de la grille, et une implantation P+ plus profonde sous le métal de la grille.The aluminum is then deposited and a new resin mask is formed which covers the areas of aluminum to be preserved. The surface of the thinned substrate at this stage therefore comprises the perforated grid, the P + implantation of shallow depth and an anti-reflection layer in the openings of the grid, and a deeper P + implantation under the metal of the grid.
Dans une deuxième manière, au lieu d'implanter plus profondément, par une opération spécifique, la zone qui sera ultérieurement recouverte par la grille d'aluminium, on fait une opération d'implantation plus profonde au départ et on élimine ensuite une partie de l'épaisseur implantée. Pour cela on procède comme suit : on dépose d'abord une couche d'oxyde mince de protection, on effectue l'implantation P à travers l'oxyde. Puis on enlève l'oxyde, et on dépose directement la couche d'aluminium. On forme un masque de résine pour graver la couche d'aluminium selon le motif de grille ajourée, on attaque la surface du silicium dans les ouvertures de la grille pour éliminer une partie de l'épaisseur de la couche implantée. Puis, on
dépose une couche antireflet uniforme (par exemple à base de nitrure de silicium) sur la grille et sur la surface de silicium.
In a second way, instead of implanting more deeply, by a specific operation, the area that will subsequently be covered by the aluminum grid, a deeper implantation operation is made initially and then part of the implanted thickness. For this we proceed as follows: first depositing a protective thin oxide layer, the implantation P is carried out through the oxide. Then the oxide is removed, and the aluminum layer is deposited directly. A resin mask is formed to etch the aluminum layer according to the open grid pattern, the silicon surface is etched into the apertures of the grid to remove a portion of the thickness of the implanted layer. Then, we deposits a uniform antireflection layer (for example based on silicon nitride) on the grid and on the silicon surface.
Claims
1. Procédé de fabrication d'un capteur d'image à substrat aminci, comportant :A method of manufacturing a thin-filmed image sensor, comprising:
- la formation, à partir de la face avant d'une tranche de matériau semiconducteur (12), d'une matrice de zones photosensibles et de circuits électroniques associés,- forming, from the front face of a semiconductor material wafer (12), a matrix of photosensitive zones and associated electronic circuits,
- le report de la tranche par sa face avant contre la face avant d'un substrat de support (20),the transfer of the wafer by its front face against the front face of a support substrate (20),
- l'élimination, à partir de la face arrière de la tranche de matériau semiconducteur, de la majeure partie de l'épaisseur de cette tranche, laissant subsister sur le substrat une fine couche semiconductrice comprenant, sur sa face avant, la matrice photosensible et les circuits associés, ce procédé étant caractérisé en ce que, postérieurement à cette élimination, on dépose une couche métallique opaque fortement conductrice (26), et on grave des ouvertures dans cette couche métallique pour éliminer la couche en regard de chacune des zones photosensibles, la couche métallique constituant, en regard de la matrice photosensible, une grille ajourée (30) à continuité électrique permettant d'amener un potentiel uniforme sur la face arrière de la tranche semiconductrice amincie en regard de toute la matrice.the elimination, from the rear face of the slice of semiconductor material, of the major part of the thickness of this slice, leaving on the substrate a thin semiconductor layer comprising, on its front face, the photosensitive matrix and the associated circuits, this method being characterized in that, after this elimination, a highly conductive opaque metal layer (26) is deposited, and openings in this metal layer are etched to eliminate the layer facing each of the photosensitive zones, the metal layer constituting, opposite the photosensitive matrix, a perforated grid (30) with electrical continuity making it possible to bring a uniform potential onto the rear face of the thinned semiconductor wafer facing the entire matrix.
2. Procédé selon la revendication 1 , caractérisé en ce que, après avoir aminci la tranche et avant de déposer la couche métallique (26), on augmente superficiellement le dopage de la face arrière de la tranche, en créant une couche surdopée (22) dont l'épaisseur est une faible fraction de l'épaisseur résiduelle de la tranche.2. Method according to claim 1, characterized in that, after having thinned the wafer and before depositing the metal layer (26), the doping of the back side of the wafer is superficially increased, creating an overdoped layer (22). whose thickness is a small fraction of the residual thickness of the wafer.
3. Procédé selon la revendication 2, caractérisé en ce que, après la réalisation des ouvertures de la couche métallique, on élimine, dans les ouvertures, au moins une partie de l'épaisseur de la couche semiconductrice ainsi surdopée. 3. Method according to claim 2, characterized in that, after making the openings of the metal layer, is removed in the openings, at least a portion of the thickness of the semiconductor layer and overdoped.
4. Procédé selon la revendication 2, caractérisé en ce que, avant dépôt de la couche métallique, on effectue une opération de dopage supplémentaire locale dans les zones qui seront recouvertes par la grille, à travers un masque complémentaire de celui qui définit les ouvertures de la grille lors de la gravure de celle-ci.4. Method according to claim 2, characterized in that, prior to deposition of the metal layer, an additional local doping operation is performed in the areas to be covered by the gate, through a mask complementary to that which defines the openings of the gate. the grid during the engraving thereof.
5. Procédé selon l'une des revendications 1 à 4, caractérisé en ce que, avant le dépôt de la couche métallique fortement conductrice, on ouvre des vias dans la tranche semiconductrice, sur la majeure partie de l'épaisseur de celle-ci, jusqu'à mettre à nu des plages métalliques qui ont été formées à partir de la face avant dans les opérations de réalisation de la matrice et des circuits électroniques associés.5. Method according to one of claims 1 to 4, characterized in that, before the deposition of the highly conductive metal layer is opened vias in the semiconductor wafer, over most of the thickness thereof, until bare metal beaches that have been formed from the front in the operations of realization of the matrix and associated electronic circuits.
6. Procédé selon la revendication 5, caractérisé en ce que, après découpage de la tranche en capteurs individuels, on utilise au moins une portion (35) de la couche métallique, isolée de la grille ajourée et reliée par un via (25) à une plage métallique (15), comme plot de soudure pour la connexion du capteur d'image à l'extérieur.6. Method according to claim 5, characterized in that, after cutting the wafer into individual sensors, at least one portion (35) of the metal layer is used, isolated from the perforated grid and connected via a via (25) to a metal pad (15) as a solder pad for connecting the image sensor to the outside.
7. Procédé selon la revendication 5, caractérisé en ce que le substrat de report (20) est un substrat provisoire, un substrat définitif transparent (60) est collé sur la face arrière de la tranche, le substrat provisoire est éliminé, les plages métalliques (15) reliées à des vias sont dénudées par la face avant de la tranche, et, après découpage de la tranche en capteurs d'image individuels, au moins une de ces plages (15), reliée par un via (25) à la grille ajourée, sert de plot de soudure pour une connexion extérieure afin d'amener de l'extérieur, à travers la plage métallique et le via, un potentiel de référence sur la grille ajourée.7. Method according to claim 5, characterized in that the transfer substrate (20) is a temporary substrate, a transparent final substrate (60) is stuck on the rear face of the wafer, the temporary substrate is eliminated, the metal pads (15) connected to vias are stripped by the front face of the wafer, and, after cutting the wafer into individual image sensors, at least one of these ranges (15), connected via a via (25) to the perforated grid, serves as a weld pad for an external connection to bring from the outside, through the metal strip and via, a reference potential on the perforated grid.
8. Procédé selon l'une des revendications 1 à 7, caractérisé en ce que, pour un capteur couleur, après gravure de la couche métallique, on dépose des filtres colorés.8. Method according to one of claims 1 to 7, characterized in that, for a color sensor, after etching of the metal layer, is deposited color filters.
9. Capteur d'image comportant, sur un substrat de report (20, 60), un substrat semiconducteur aminci (12) sur la face avant duquel sont formés une matrice de zones photosensibles et des circuits électroniques associés, caractérisé en ce que, sur la face arrière du substrat aminci, est formée une couche métallique opaque fortement conductrice, ajourée, comportant des ouvertures en regard de chaque zone photosensible, la couche métallique constituant, en regard de la matrice photosensible, une grille ajourée (30) à continuité électrique permettant d'amener un potentiel uniforme, sur la face arrière du substrat aminci, en regard de toute la matrice.An image sensor comprising, on a transfer substrate (20, 60), a thinned semiconductor substrate (12) on the front face of which are formed a matrix of photosensitive zones and associated electronic circuits, characterized in that, on the rear face of the thinned substrate, is formed a opaque, highly conductive, perforated metallic layer comprising openings facing each photosensitive zone, the metallic layer constituting, facing the photosensitive matrix, a perforated grid (30) with electrical continuity for bringing a uniform potential on the back of the thinned substrate, facing the entire matrix.
10. Capteur d'image selon la revendication 9, caractérisé en qu'au moins un via conducteur (24) est prévu dans toute l'épaisseur du substrat semiconducteur aminci pour relier électriquement des portions de la couche métallique ajourée à des plages métalliques (14) faisant partie des circuits électroniques associés à la matrice.An image sensor according to claim 9, characterized in that at least one conductive via (24) is provided throughout the thickness of the thinned semiconductor substrate to electrically connect portions of the apertured metal layer to metal plates (14). ) forming part of the electronic circuits associated with the matrix.
1 1. Capteur d'image selon l'une des revendications 9 et 10, caractérisé en ce que la face avant du substrat aminci (12) est collée contre le substrat de report (20), et c'est la face arrière du substrat aminci, face qui porte la couche conductrice métallique opaque, qui reste accessible à la fin de la fabrication du capteur d'image, alors que la face avant est inaccessible, enfermée entre le substrat aminci et le substrat de report, des portions (35) de la couche métallique servant de plots de soudure pour la connexion avec l'extérieur.1 1. Image sensor according to one of claims 9 and 10, characterized in that the front face of the thinned substrate (12) is bonded against the transfer substrate (20), and this is the rear face of the substrate thinned, face which carries the opaque metal conductive layer, which remains accessible at the end of the manufacture of the image sensor, while the front face is inaccessible, enclosed between the thinned substrate and the transfer substrate, portions (35). of the metal layer serving as solder pads for connection with the outside.
12. Capteur d'image selon l'une des revendications 9 à 11 , caractérisé en ce que des filtres colorés (42) sont déposés sur la grille ajourée (30).12. Image sensor according to one of claims 9 to 11, characterized in that color filters (42) are deposited on the perforated grid (30).
13. Capteur d'image selon l'une des revendications 9 et 10, caractérisé en ce que le substrat de report (60) est un substrat transparent, la face arrière du substrat aminci étant collée contre le substrat, la face avant du substrat aminci étant accessible et la face arrière et sa couche d'aluminium ajourée étant inaccessibles, enfermées entre le substrat aminci et le substrat définitif transparent. 13. An image sensor according to one of claims 9 and 10, characterized in that the transfer substrate (60) is a transparent substrate, the rear face of the thinned substrate being bonded against the substrate, the front face of the thinned substrate. being accessible and the back face and its perforated aluminum layer being inaccessible, enclosed between the thinned substrate and the transparent final substrate.
14. Capteur d'image selon la revendication 13, caractérisé en ce que des filtres colorés (42) sont interposés entre la grille ajourée (30) et le substrat de report transparent (60).14. An image sensor according to claim 13, characterized in that color filters (42) are interposed between the perforated grid (30) and the transparent transfer substrate (60).
15. Capteur d'image selon l'une des revendications 9 à 14, caractérisé en ce que le substrat semiconducteur est superficiellement surdopé sur une faible profondeur de la face arrière, au moins sous la couche ajourée d'aluminium, avec une quantité d'impuretés de dopage plus élevée sous cette couche que dans les ouvertures de cette couche.15. An image sensor according to one of claims 9 to 14, characterized in that the semiconductor substrate is superficially overdoped over a shallow depth of the rear face, at least under the perforated layer of aluminum, with an amount of doping impurities higher under this layer than in the openings of this layer.
16. Capteur d'image selon l'une des revendications 9 à 15, caractérisé en ce que la grille ajourée (30) est revêtue d'un dépôt noir réduisant la réflectivité de la couche.16. An image sensor according to one of claims 9 to 15, characterized in that the perforated grid (30) is coated with a black deposit reducing the reflectivity of the layer.
17. Capteur d'image selon la revendication 16, caractérisé en ce que le substrat aminci est recouvert, dans les ouvertures de la grille ajourée (30), d'une couche anti-reflet. 17. An image sensor according to claim 16, characterized in that the thinned substrate is covered, in the openings of the perforated grid (30), with an anti-reflection layer.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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FR0505929 | 2005-06-10 | ||
FR0505929A FR2887076B1 (en) | 2005-06-10 | 2005-06-10 | IMAGINE SEMICONDUCTOR SUBSTRATE IMAGE SENSOR WITH REAR METALLIZATION |
Publications (2)
Publication Number | Publication Date |
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WO2006131427A2 true WO2006131427A2 (en) | 2006-12-14 |
WO2006131427A3 WO2006131427A3 (en) | 2007-03-29 |
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PCT/EP2006/062043 WO2006131427A2 (en) | 2005-06-10 | 2006-05-04 | Image sensor provided with a thinned semiconductor substrate with backside metallisation |
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FR (1) | FR2887076B1 (en) |
WO (1) | WO2006131427A2 (en) |
Cited By (2)
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CN112103304A (en) * | 2020-09-22 | 2020-12-18 | 武汉新芯集成电路制造有限公司 | Backside-illuminated sensor, manufacturing method thereof and layout structure |
US11270957B2 (en) | 2018-02-07 | 2022-03-08 | Stmicroelectronics (Rousset) Sas | Method for detecting a breach of the integrity of a semiconductor substrate of an integrated circuit from its rear face, and corresponding device |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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FR2910705B1 (en) * | 2006-12-20 | 2009-02-27 | E2V Semiconductors Soc Par Act | CONNECTION PLATE STRUCTURE FOR IMAGE SENSOR ON AMINED SUBSTRATE |
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DE19838430A1 (en) * | 1998-08-24 | 2000-03-09 | Fraunhofer Ges Forschung | Photodetector array, especially a photodiode array, is produced by forming a common electrode on the radiation incident back face to avoid radiation shadowing by front face wiring of individual electrodes |
US20020000562A1 (en) * | 2000-04-20 | 2002-01-03 | Carlson Lars S. | Fabrication of low leakage-current backside illuminated photodiodes |
US20030209652A1 (en) * | 2002-05-10 | 2003-11-13 | Hamamatsu Photonics K.K. | Back illuminated photodiode array and method of manufacturing the same |
US20040266052A1 (en) * | 2001-08-31 | 2004-12-30 | Eric Pourquier | Method for making a color image sensor with pad-to pad soldered supporting substrate |
US20050032265A1 (en) * | 2001-08-31 | 2005-02-10 | Eric Pourquier | Method for making a color image sensor with recessed contact apertures prior to thinning |
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- 2005-06-10 FR FR0505929A patent/FR2887076B1/en not_active Expired - Fee Related
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DE19838430A1 (en) * | 1998-08-24 | 2000-03-09 | Fraunhofer Ges Forschung | Photodetector array, especially a photodiode array, is produced by forming a common electrode on the radiation incident back face to avoid radiation shadowing by front face wiring of individual electrodes |
US20020000562A1 (en) * | 2000-04-20 | 2002-01-03 | Carlson Lars S. | Fabrication of low leakage-current backside illuminated photodiodes |
US20040266052A1 (en) * | 2001-08-31 | 2004-12-30 | Eric Pourquier | Method for making a color image sensor with pad-to pad soldered supporting substrate |
US20050032265A1 (en) * | 2001-08-31 | 2005-02-10 | Eric Pourquier | Method for making a color image sensor with recessed contact apertures prior to thinning |
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US11270957B2 (en) | 2018-02-07 | 2022-03-08 | Stmicroelectronics (Rousset) Sas | Method for detecting a breach of the integrity of a semiconductor substrate of an integrated circuit from its rear face, and corresponding device |
CN112103304A (en) * | 2020-09-22 | 2020-12-18 | 武汉新芯集成电路制造有限公司 | Backside-illuminated sensor, manufacturing method thereof and layout structure |
CN112103304B (en) * | 2020-09-22 | 2024-02-09 | 武汉新芯集成电路制造有限公司 | Backside illuminated sensor, manufacturing method thereof and layout structure |
Also Published As
Publication number | Publication date |
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FR2887076B1 (en) | 2007-08-31 |
FR2887076A1 (en) | 2006-12-15 |
WO2006131427A3 (en) | 2007-03-29 |
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