CN112103304A - Backside-illuminated sensor, manufacturing method thereof and layout structure - Google Patents
Backside-illuminated sensor, manufacturing method thereof and layout structure Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 178
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 56
- 239000010703 silicon Substances 0.000 claims abstract description 56
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 45
- 238000000034 method Methods 0.000 claims abstract description 25
- 239000010410 layer Substances 0.000 claims description 260
- 239000000758 substrate Substances 0.000 claims description 36
- 239000000463 material Substances 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 239000002131 composite material Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 239000012790 adhesive layer Substances 0.000 claims 1
- 238000004140 cleaning Methods 0.000 abstract description 19
- 239000007788 liquid Substances 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 7
- 230000005540 biological transmission Effects 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1464—Back illuminated imager structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
Abstract
The invention provides a back-illuminated sensor, a manufacturing method thereof and a layout structure, wherein a metal grid layer extends from a pixel region to a silicon perforated layer of a logic region in the process of preparing the back-illuminated sensor by using the back-illuminated layout structure and the manufacturing method, so that a dielectric layer and a plug under the metal grid layer can be protected by using the metal grid layer under the logic region, and the dielectric layer and the plug under the metal grid layer are prevented from being corroded by cleaning liquid in the subsequent wet cleaning process, so that the plug damage is avoided.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a backside illuminated sensor, a manufacturing method thereof and a layout structure.
Background
The light of a backside illuminated (BSI) sensor enters the substrate from the back side of the substrate rather than the front side, and because of the reduced light reflection, the BSI sensor is able to capture more image signals than a front-illuminated sensor. At present, a logic operation chip and a pixel (photodiode) array chip are three-dimensionally integrated by a three-dimensional stacked backside illuminated sensor (UTS) through a Through Silicon Via (TSV), so that the size and the area of the sensor array are improved while the size of the chip is maintained, the metal interconnection among functional chips is greatly shortened, the heat generation, the power consumption and the delay are reduced, and the performance of the chip is improved.
In a three-dimensional stacked backside illuminated sensor (UTS), a metal grid is provided and a crosstalk of light between different pixels (photodiodes) is prevented by using an opaque property of the metal grid, but there have been some problems in such a metal grid layer process. In the prior art, when a metal grid is formed, a metal is deposited to form a metal layer, and then the metal layer is etched to form the metal grid located between pixel points. In the above process, the metal layer in the silicon via region is usually removed, and the oxide layer in the silicon via region is etched and damaged in the etching process of removing the metal layer in the silicon via region by etching, and an acid solution penetrates into the plug structure through the damaged portion of the oxide layer in the subsequent wet cleaning process, thereby causing damage to the plug structure.
Disclosure of Invention
The invention aims to provide a layout structure of a backside illuminated sensor, the backside illuminated sensor and a manufacturing method thereof, so as to solve the problem that a plug positioned in a silicon through hole layer is damaged in the manufacturing process of the conventional backside illuminated (BSI) sensor.
To solve the above problems, the present invention provides a backside-illuminated sensor, including: the pixel structure comprises a logic area and a pixel area, wherein a silicon perforated layer and a dielectric layer at least covering the silicon perforated layer are formed in the logic area, and a plurality of plugs are arranged in the silicon perforated layer; and a pixel layer and a metal grid layer covering the pixel layer are formed in the pixel area, and the metal grid layer extends to the dielectric layer of the logic area and covers the plug.
Optionally, the metal grid layer located in the logic area is arranged in a planar manner and covers all the plugs.
Optionally, the metal grid layer in the logic region includes at least one sub-metal grid, and each sub-metal grid correspondingly covers one plug.
Optionally, the metal grid layer further includes a connection line, and the connection line connects the adjacent sub-metal grids at least partially located in the logic region.
Optionally, the orthographic projection of the plug on the dielectric layer falls into the orthographic projection of the sub-metal grid on the dielectric layer.
Optionally, the maximum width of the sub-metal grid is at least greater than 0.01um greater than the maximum width of the plug.
Optionally, the distance between adjacent sub-metal grids is 0.5um to 20 um.
Optionally, the metal grid layer includes an adhesion layer, a metal layer, and an anti-reflection layer formed in sequence.
In order to solve the above problems, the present invention also provides a method of manufacturing a backside-illuminated sensor, the method including:
providing a substrate with a logic area and a pixel area, and forming a pixel layer in the pixel area;
performing a through silicon via process on the substrate to form a through silicon via layer connecting the pixel layers in the logic region, wherein the through silicon via layer has at least one plug therein;
forming a dielectric layer on the surface of the substrate with the silicon perforated layer, wherein the dielectric layer covers the surface of the silicon perforated layer and exposes the surface of the substrate of the pixel region;
and forming a metal grid layer on the surface of the substrate with the dielectric layer, wherein the metal grid layer extends from the pixel area to the dielectric layer of the logic area and covers at least one plug.
Optionally, the step of forming a dielectric layer on the surface of the substrate having the silicon via layer includes:
depositing a dielectric layer material on the surface of the substrate with the silicon perforated layer;
and removing at least the dielectric layer material in the pixel region by adopting an etching process to form the dielectric layer.
Optionally, the dielectric layer is a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a composite layer structure formed by alternately stacking a silicon oxide layer and a silicon nitride layer.
Optionally, the step of forming a metal grid layer on the surface of the semiconductor substrate with the dielectric layer includes:
forming a metal layer and a mask layer on the surface of the semiconductor substrate with the dielectric layer;
and etching the metal layer by taking the mask layer as a mask to form the metal grid layer, extending the metal grid layer to the dielectric layer of the logic region and covering at least one plug.
In order to solve the above problems, the present invention further provides a layout structure of a backside illuminated sensor, the layout structure being used for manufacturing any one of the backside illuminated sensors, wherein the layout structure has a logic layout region and a pixel layout region, and the layout structure includes:
a through-silicon via layout, wherein the through-silicon via layout has a plurality of plug patterns, and the plurality of plug patterns are located in the logic layout area;
the dielectric layer layout is provided with dielectric layer patterns at least positioned in the logic layout area, and the dielectric layer patterns correspond to the plug patterns;
and the metal grid pattern extends from the pixel layout area to the dielectric layer pattern of the logic layout area, and covers the plug pattern.
Optionally, the metal grid pattern located in the logic layout area is a planar structure, and the planar structure covers all the plug patterns.
Optionally, the metal grid pattern located in the logic layout area includes at least one sub-metal grid pattern, and each sub-metal grid pattern covers one plug pattern correspondingly.
Optionally, the metal grid pattern further includes a connection line pattern, and the connection line pattern is connected to the adjacent sub-metal grid pattern at least partially located in the logic region.
Optionally, an orthographic projection of the plug pattern on the dielectric layer pattern falls within an orthographic projection of the sub-metal grid pattern on the dielectric layer pattern.
Optionally, the maximum width dimension of the sub-metal grid pattern is at least 0.01um greater than the maximum width dimension of the plug pattern.
Optionally, the distance between adjacent sub-metal grid patterns is 0.5um to 20 um.
In the backside illuminated sensor, the metal grid layer extends from the pixel region to the silicon perforated layer of the logic region, so that the metal grid layer positioned in the logic region can be used for protecting the dielectric layer and the plugs positioned below the metal grid layer, and further, the dielectric layer and the plugs positioned below the metal grid layer are prevented from being eroded by cleaning liquid in the subsequent wet cleaning process, so as to avoid the damage of the plugs.
Drawings
FIG. 1 is a schematic top view of a backside illuminated sensor in an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view along AA' of FIG. 1;
FIG. 3 is a schematic top view of a backside illuminated sensor in another embodiment of the present invention;
FIG. 4 is a schematic top view of a backside illuminated sensor in another embodiment of the present invention;
FIG. 5 is a schematic flow chart illustrating the fabrication of a backside illuminated sensor in one embodiment of the present invention;
FIGS. 6-7 are schematic views illustrating the manufacturing process of a backside illuminated sensor according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a layout structure of a backside-illuminated sensor in an embodiment of the present invention;
fig. 9 is a schematic diagram of a layout structure of a backside-illuminated sensor in another embodiment of the present invention;
fig. 10 is a schematic diagram of a layout structure of a backside-illuminated sensor in another embodiment of the present invention;
wherein the reference numbers are as follows:
10-plug pattern;
20-a dielectric layer pattern;
30-pixel layer pattern;
40-a metal grid pattern; 401-clear hole pattern;
41-sub-metal grid pattern; 42-a connection line pattern;
100-a substrate;
200-a silicon perforated layer; 210-a plug;
220-an upper electrode; 230-a lower electrode;
300-a dielectric layer;
400-a pixel layer;
500-a metal grid layer; 501-light holes;
5000-a metal grid material layer;
a1-logical layout area; A2-Pixel layout area;
b1 — logical area; b2-pixel area;
Detailed Description
The backside illuminated sensor, the manufacturing method thereof, and the layout structure thereof according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
FIG. 1 is a schematic top view of a backside illuminated sensor in an embodiment of the present invention; fig. 2 is a schematic cross-sectional view along AA' in fig. 1. The specific structure of the backside-illuminated sensor in the present embodiment is described in detail below with reference to fig. 1 and 2.
As shown in fig. 1 and 2, the backside-illuminated sensor includes: a logic region B1 and a pixel region B2, a silicon via layer 200 and a dielectric layer 300 at least covering the silicon via layer 200 are formed in the logic region B1, the silicon via layer 200 has a plurality of plugs 210 therein, wherein the dielectric layer 300 may be silicon oxide, silicon nitride layer or silicon oxynitride. A pixel layer 400 and a metal grid layer 500 covering the pixel layer 400 are formed in the pixel region B2, and the metal grid layer 500 extends to the dielectric layer 300 of the logic region B1 and covers the plug 210.
In the backside illuminated sensor of the present embodiment, since the metal grid layer 500 extends from the pixel region B2 to the silicon via layer 200 of the logic region B1, the metal grid layer 500 in the logic region B1 can be used to protect the dielectric layer 300 and the plugs 210 under the metal grid layer 500, so as to prevent the cleaning solution from eroding the dielectric layer 300 and the plugs 210 under the metal grid layer 500 in the subsequent wet cleaning process, so as to prevent the plugs 210 from being damaged.
With continued reference to fig. 1 and fig. 2, in the present embodiment, the metal grid layer 500 located in the logic area B1 is a planar structure, and the planar structure covers all the plugs 210, so as to avoid the problem that all the plugs 210 are eroded by the cleaning solution.
Further, with continued reference to fig. 1 and fig. 2, in this embodiment, the backside illuminated sensor further includes a substrate 100, a pixel layer 400 is formed in a pixel region B2 of the substrate 100, the metal grid layer 500 located in the pixel region B2 has a plurality of light holes 501, the light holes 501 correspondingly expose the pixel structures located in the pixel layer 400, so that the pixel structures can sense light passing through the light holes 501, and a portion of the metal grid layer 500 located in the pixel region B2 where the light holes 501 are not located can prevent crosstalk induced between different pixel structures. In addition, in the present embodiment, the through-silicon via layer 200 may be formed in the logic region B1 of the substrate 100 by a through-silicon via process, and the through-silicon via layer may have a plug 210 therein, and an upper electrode 220 and a lower electrode 230 connected to the plug 210.
With continued reference to fig. 1 and 2, in the present embodiment, the metal grid layer 500 includes an adhesion layer, a metal layer, and an anti-reflection layer, which are sequentially formed.
FIG. 3 is a schematic top view of a backside illuminated sensor in another embodiment of the present invention; referring to fig. 3, in the present embodiment, the metal grid layer 500 in the logic region B1 includes at least one sub-metal grid 510, and each sub-metal grid 510 covers one corresponding plug 210. In this way, the metal grid layer 500 in the logic region B1 is distributed in a dot shape, which not only can prevent the plug 210 from being eroded by the cleaning solution, but also can increase the light transmittance of the prepared backside illuminated sensor logic region B1.
In addition, as shown in fig. 3, in the present embodiment, the metal grid layer 500 in the logic area B1 is disconnected from the metal grid layer 500 in the pixel area B2. In which a break region may cross a boundary between the logic region B1 and the pixel region B2, partially located in the logic region B1 and partially located in the pixel region B2 as shown in fig. 3. Alternatively, the metal grid layer 500 in the pixel region B2 may also extend to the logic region B1 and be disconnected from the sub-metal grid 510 in the logic region B1. And, in an alternative embodiment, the metal grid layer 500 on the pixel region B2 may also extend to the logic region B1 and then be connected to a portion of the sub-metal grid 510. In this embodiment, the positions and the connection relationships between the metal grid layer 500 in the logic area B1 and the pixel area B2 are not specifically limited herein, and the practical situation is the standard.
Further, with continued reference to fig. 3, in the present embodiment, the orthographic projection of the plug 210 on the dielectric layer 300 falls within the orthographic projection of the sub-metal grid 510 on the dielectric layer 300. Thus, in the present embodiment, the sub-metal grids 510 in the metal grid layer 500 of the logic region B1 can completely cover the corresponding plugs 210, and thus the plugs 210 can be protected from being corroded by the cleaning solution.
Optionally, in this embodiment, the maximum width dimension of the sub-metal grids 510 is at least 0.01um larger than the maximum width dimension of the plugs 210. And, optionally, the distance between adjacent sub-metal grids 510 is 0.5um to 20 um.
Also, in this embodiment, the sub-metal grids 210 may be circular, rectangular, polygonal, etc., and the specific shape of the sub-metal grids 210 is not specifically limited herein. Preferably, the shape of the sub-metal grid 210 is the same as the shape of the plug 210.
Fig. 4 is a schematic top view of a backside illuminated sensor according to another embodiment of the present invention. As shown in fig. 4, in the present embodiment, the metal grid layer 500 further includes connection lines 520, and the connection lines 520 connect the adjacent sub-metal grids 510 at least partially located in the logic area B1.
In the present embodiment, the metal grid layer 500 in the logic area B1 has not only the sub-metal grids 510 but also the connection lines 520. In this way, not only the plugs 210 can be prevented from being eroded by the cleaning solution, but also various identification patterns can be formed between the sub-metal grids 510 and the connection lines 520 or between the connection lines 520, so as to be used for alignment identification in subsequent processes or be applied to other scenes requiring identification. The shape of the connection lines 520, the identification patterns formed by the connection lines 520 and the sub-metal grids 510 are not specifically limited herein, which is subject to practical considerations.
The present embodiment also discloses a method for manufacturing a backside illuminated sensor, which is described below based on the backside illuminated sensor. FIG. 5 is a schematic flow chart illustrating the fabrication of a backside illuminated sensor in one embodiment of the present invention; fig. 6 to 7 are schematic structural diagrams of a manufacturing process of a backside-illuminated sensor according to an embodiment of the present invention. The steps of the method for manufacturing the backside illuminated sensor according to the present embodiment will be described in detail with reference to fig. 5 to 7.
In step S10, as shown in fig. 6, a substrate 100 having a logic region B1 and a pixel region B2 is provided, and a pixel layer 400 having a plurality of pixel structures within the pixel layer 400 is formed within the pixel region B2.
The substrate may include a semiconductor material, an insulating material, a conductor material, or any combination thereof, and may have a single-layer structure or a multi-layer structure. Thus, the substrate may be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III/V or II/VI compound semiconductors. Layered substrates such as, for example, Si/SiGe, Si/SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator may also be included.
In step S20, with continued reference to fig. 6, a through silicon via process is performed on the substrate 100 to form a through silicon via layer 200 connecting the pixel layers 400 in the logic region B1, wherein the through silicon via layer 200 has at least one plug 210 therein. In the present embodiment, when the silicon via layer 200 is formed, an upper electrode 220 and a lower electrode 230 connected to the plug 210 are formed.
In step S30, with continued reference to fig. 6, a dielectric layer 300 is formed on the surface of the substrate 100 having the through-silicon via layer 200, wherein the dielectric layer 300 covers the surface of the through-silicon via layer 200 and exposes the surface of the substrate 100 in the pixel region B2.
With continued reference to fig. 6, the step of forming the dielectric layer 300 on the surface of the substrate 100 having the silicon via layer 200 includes the following first step and second step.
In step one, a dielectric layer material is deposited to a certain thickness on the surface of the substrate 100 having the silicon via layer 200. The material of the dielectric material layer may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxide, or the like.
In step two, an etching process is used to remove at least the dielectric layer material located in the pixel region B2, so as to form the dielectric layer 300. The dielectric layer 300 is a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a composite layer structure formed by alternately stacking silicon oxide layers and silicon nitride layers.
In step S40, referring to fig. 7 in combination with fig. 6, a metal grid layer 500 is formed on the surface of the substrate 100 having the dielectric layer 300, and the metal grid layer 500 extends from the pixel region B2 to the dielectric layer 300 in the logic region B1 and covers at least one of the plugs 210. The metal grid layer 500 in the pixel region B2 has a plurality of light holes 501, the light holes 501 correspondingly expose the pixel structures in the pixel layer 400, so that the pixel structures can sense the light passing through the light holes 501, and the metal grid layer 500 in the pixel region B2 is not provided with the light holes 501, which can prevent crosstalk induced between different pixel structures.
In the present embodiment, when the metal layer on the dielectric layer 300 is etched to form the metal grid layer 500, at least a portion of the metal on the silicon via layer 200 in the logic region B1 is remained, so as to form the metal grid layer 500 extending from the pixel region B2 to the logic region B1, and overlying the dielectric layer 300 and covering the plug 210. Since the metal grid layer 500 on the dielectric layer 300 in the logic region B1 can protect the dielectric layer 300 and the plugs 210 thereunder, the dielectric layer 300 and the plugs 210 under the metal grid layer 500 are prevented from being corroded by acid liquid in the subsequent wet cleaning process, so as to prevent the plugs 210 from being damaged.
The step of forming the metal grid layer 500 on the surface of the substrate 100 having the dielectric layer 300 includes the following steps one to two.
In step one, as shown in fig. 6, a metal layer 5000 and a mask layer (not shown) are formed on the surface of the substrate 100 having the dielectric layer 300.
In the second step, the mask layer is used as a mask to etch the metal layer 5000 to form the metal grid layer 500, and the metal grid layer 500 extends to the dielectric layer 300 in the logic region B1 and covers at least one plug 210.
In addition, in the present embodiment, a layout structure of a backside illuminated sensor used in the above-described method for manufacturing a backside illuminated sensor is also disclosed. Fig. 8 is a schematic diagram of a layout structure of a backside-illuminated sensor in an embodiment of the present invention; fig. 9 is a schematic diagram of a layout structure of a backside-illuminated sensor in another embodiment of the present invention; fig. 10 is a schematic diagram of a layout structure of a backside-illuminated sensor in another embodiment of the present invention. The layout structure of the present embodiment will be described below with reference to fig. 8 to 10.
As shown in fig. 8, the layout structure of the backside illuminated sensor of the present embodiment has a logic layout area and a pixel layout area, and the layout structure includes:
a through-silicon via layout having a plurality of plug patterns 10 therein, a plurality of the plug patterns 10 being located in the logic layout area a 1;
a dielectric layer layout, wherein the dielectric layer layout is provided with a dielectric layer pattern 20 at least positioned in the logic layout area, and the dielectric layer pattern 20 corresponds to the plurality of plug patterns 10; and the number of the first and second groups,
a metal grid layout having a metal grid pattern 40 therein, the metal grid pattern 40 extending from the pixel layout area a2 to the logic layout area a1 over the dielectric layer pattern 20, and the metal grid pattern covering the plug pattern 10.
In the present embodiment, the metal grid pattern 40 of the metal grid layout extends from the pixel layout area a2 to the dielectric layer pattern 20 of the logic layout area a1 and covers the plug pattern 10. When the metal grid layout of the embodiment is used and the metal layer on the dielectric layer is etched to form the metal grid layer, at least part of the metal on the through-silicon via layer of the logic region is retained, and the metal grid layer which extends from the pixel region to the logic region, is positioned on the dielectric layer and covers the plug is formed. The metal grid layer on the dielectric layer of the logic area can protect the dielectric layer and the plug under the metal grid layer, so that the dielectric layer and the plug under the metal grid layer are prevented from being corroded by cleaning liquid in the subsequent wet cleaning process, and the plug is prevented from being damaged.
With continued reference to fig. 8, in the present embodiment, the metal grid pattern 40 located in the logic layout area a1 is a planar structure, and the planar structure covers all the plug patterns 10. Based on this, the correspondingly formed metal grid layer can cover all the plugs, so that all the plugs are not corroded by a cleaning solution during wet cleaning, and the plugs are prevented from being damaged.
Further, with reference to fig. 8 and with reference to fig. 1, in this embodiment, the layout structure of the backside illuminated sensor further includes: a pixel layout having a pixel pattern 30 for fabricating a pixel layer in a backside illuminated sensor. The pixel pattern 30 has a plurality of pixel structure patterns, and the metal grid pattern 40 in the pixel layout area a2 has a plurality of light hole patterns 401, and the light hole patterns 401 correspondingly expose the pixel structure patterns. Thus, when the layout structure in the embodiment is used for manufacturing a backside illuminated sensor, the metal grid layer 500 is correspondingly formed, the part located in the pixel area B2 is provided with a plurality of light transmission holes 501, the light transmission holes 501 are correspondingly exposed and located in the pixel layer 400, so that the pixel structure can sense light transmitted through the light transmission holes 501, and the metal grid layer 500 in the pixel area B2 is not provided with the part of the light transmission holes 501, and crosstalk of the light sensed between different pixel structures can be prevented.
Referring to fig. 9, in the present embodiment, the metal grid pattern 40 located in the logic layout area a1 includes at least one sub-metal grid pattern 41, and each sub-metal grid pattern 41 covers one plug pattern 10. Therefore, the prepared metal grid layer positioned in the logic area is distributed in a point shape correspondingly, the plug can be protected from being corroded by cleaning liquid when wet cleaning is carried out, and meanwhile, the light transmittance of the prepared backside illuminated sensor in the logic area can be ensured.
Further, with continued reference to fig. 9, in the present embodiment, the metal grid pattern 40 located in the logic layout area a1 is disconnected from the metal grid pattern 40 located in the pixel layout area B2. In which a break region may be located partially in the logic layout area a1 and partially in the pixel layout area B2 across the boundary between the logic layout area a1 and the pixel layout area B2 as shown in fig. 3. Alternatively, the metal grid pattern 40 located in the pixel layout area B2 may be further extended to the logic layout area a1 and then disconnected from the sub-metal grid pattern 41 in the logic layout area a 1. And, in an alternative embodiment, the metal grid pattern 40 located on the pixel layout area B2 may also extend to behind the logic layout area a1 to connect with a portion of the sub-metal grid pattern 41. In this embodiment, the position and connection relationship between the metal grid pattern 40 in the logic layout area a1 and the pixel layout area B2 are not specifically limited, and will be subject to practical considerations.
Further, with continued reference to fig. 9, in the present embodiment, the orthographic projection of the plug pattern 10 on the dielectric layer pattern 20 falls within the orthographic projection of the sub-metal grid pattern 41 on the dielectric layer pattern 20. Therefore, the prepared sub-metal grids in the metal grid layer of the logic area can completely cover the corresponding plugs, and further can protect the plugs in an all-around manner so as to prevent the plugs from being corroded.
Optionally, in this embodiment, the maximum width dimension of the sub-metal grid pattern 41 is at least 0.01um larger than the maximum width dimension of the plug pattern 10. And, optionally, the distance between adjacent sub-metal grid patterns 41 is 0.5um to 20 um. For example, when the shapes of the sub-metal grid pattern 41 and the plugs are both circular, the maximum width dimension of the sub-metal grid pattern 41 and the maximum width dimension of the plug pattern 10 both refer to the diameter of the circle.
Of course, the sub-metal grid pattern 41 may also be rectangular, polygonal, etc., and the specific shape of the sub-metal grid pattern 41 is not specifically limited herein. Preferably, the shape of the sub-metal grid pattern 41 is the same as the shape of the plug pattern 10.
As shown in fig. 10, in the present embodiment, the metal grid pattern 40 further includes a connection line pattern 42, and the connection line pattern 42 connects the adjacent sub-metal grid patterns 41 located at least partially in the logic layout area a 1.
In the present embodiment, the connection lines can be prepared accordingly based on the connection line pattern 42. Therefore, the plug can be prevented from being corroded by cleaning liquid, and various identification patterns can be formed between the sub-metal grids and the connecting lines or between the connecting lines so as to be used for carrying out alignment identification in subsequent processing procedures or be applied to other scenes needing identification. The shapes of the connecting lines, and the identification patterns formed by the connecting lines and the sub-metal grids are not particularly limited, and the actual conditions are taken as the standard.
It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, similar parts between the embodiments may be referred to each other, and different parts between the embodiments may also be used in combination with each other, which is not limited by the present invention.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (19)
1. A backside-illuminated sensor, comprising: the pixel structure comprises a logic area and a pixel area, wherein a silicon perforated layer and a dielectric layer at least covering the silicon perforated layer are formed in the logic area, and a plurality of plugs are arranged in the silicon perforated layer; and a pixel layer and a metal grid layer covering the pixel layer are formed in the pixel area, and the metal grid layer extends to the dielectric layer of the logic area and covers the plug.
2. The backside-illuminated sensor of claim 1, wherein the metal grid layer in the logic area is arranged in a planar shape and covers all the plugs.
3. The backside-illuminated sensor of claim 1, wherein the metal grid layer at the logic region includes at least one sub-metal grid, each of the sub-metal grids covering a corresponding one of the plugs.
4. The backside-illuminated sensor of claim 3, wherein the metal grid layer further comprises connection lines connecting adjacent ones of the sub-metal grids at least partially located in the logic region.
5. The backside-illuminated sensor of claim 3, wherein the orthographic projection of the plug on the dielectric layer falls within the orthographic projection of the sub-metal grid on the dielectric layer.
6. The backside-illuminated sensor of claim 3, wherein the maximum width of the sub-metal grid is at least greater than 0.01um greater than the maximum width of the plug.
7. The backside-illuminated sensor of any one of claims 3 to 6, wherein the distance between adjacent sub-metal grids is 0.5um to 20 um.
8. The backside-illuminated sensor of claim 1, wherein the metal grid layer comprises an adhesive layer, a metal layer, and an anti-reflection layer formed in this order.
9. A method of manufacturing a backside-illuminated sensor, the method comprising:
providing a substrate with a logic area and a pixel area, and forming a pixel layer in the pixel area;
performing a through silicon via process on the substrate to form a through silicon via layer connecting the pixel layers in the logic region, wherein the through silicon via layer has at least one plug therein;
forming a dielectric layer on the surface of the substrate with the silicon perforated layer, wherein the dielectric layer covers the surface of the silicon perforated layer and exposes the surface of the substrate of the pixel region;
and forming a metal grid layer on the surface of the substrate with the dielectric layer, wherein the metal grid layer extends from the pixel area to the dielectric layer of the logic area and covers at least one plug.
10. The method of manufacturing a backside-illuminated sensor according to claim 9, wherein the step of forming a dielectric layer on the surface of the substrate having the silicon via layer comprises:
depositing a dielectric layer material on the surface of the substrate with the silicon perforated layer;
and removing at least the dielectric layer material in the pixel region by adopting an etching process to form the dielectric layer.
11. The method of claim 10, wherein the dielectric layer is a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a composite layer structure in which silicon oxide layers and silicon nitride layers are alternately stacked.
12. The method of manufacturing of claim 9, wherein forming a metal grid layer on the surface of the semiconductor substrate having the dielectric layer comprises:
forming a metal layer and a mask layer on the surface of the semiconductor substrate with the dielectric layer;
and etching the metal layer by taking the mask layer as a mask to form the metal grid layer, extending the metal grid layer to the dielectric layer of the logic region and covering at least one plug.
13. A layout structure of a backside illuminated sensor, wherein the layout structure is used for manufacturing the backside illuminated sensor according to any one of the claims 1 to 8, wherein the layout structure has a logic layout area and a pixel layout area, and the layout structure comprises:
a through-silicon via layout, wherein the through-silicon via layout has a plurality of plug patterns, and the plurality of plug patterns are located in the logic layout area;
the dielectric layer layout is provided with dielectric layer patterns at least positioned in the logic layout area, and the dielectric layer patterns correspond to the plug patterns;
and the metal grid pattern extends from the pixel layout area to the dielectric layer pattern of the logic layout area, and covers the plug pattern.
14. The layout structure of a backside-illuminated sensor as claimed in claim 13, wherein the metal grid pattern located in the logic layout area is a planar structure, and the planar structure covers all the plug patterns.
15. The layout structure of a backside-illuminated sensor according to claim 13, wherein the metal grid pattern located in the logic layout area includes at least one sub-metal grid pattern, each of the sub-metal grid patterns correspondingly covering one of the plug patterns.
16. The layout structure of a backside-illuminated sensor of claim 15, wherein the metal grid pattern further comprises a connection line pattern connecting adjacent ones of the sub-metal grid patterns at least partially located in the logic region.
17. The layout structure of a backside-illuminated sensor according to claim 15, wherein an orthographic projection of the plug pattern on the dielectric layer pattern falls within an orthographic projection of the sub-metal grid pattern on the dielectric layer pattern.
18. The kerf structure of claim 15, wherein a maximum width dimension of the sub-metal grid pattern is at least 0.01um greater than a maximum width dimension of the plug pattern.
19. The layout structure of the backside-illuminated sensor according to any one of claims 15 to 18, wherein the distance between adjacent sub-metal grid patterns is 0.5um to 20 um.
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